cpu.cc (2840:227f7c4f8c81) cpu.cc (2843:19c4c6c2b5b1)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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153
154 globalSeqNum(1),
155
156#if FULL_SYSTEM
157 system(params->system),
158 physmem(system->physmem),
159#endif // FULL_SYSTEM
160 mem(params->mem),
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 144 unchanged lines hidden (view full) ---

153
154 globalSeqNum(1),
155
156#if FULL_SYSTEM
157 system(params->system),
158 physmem(system->physmem),
159#endif // FULL_SYSTEM
160 mem(params->mem),
161 switchCount(0),
161 drainCount(0),
162 deferRegistration(params->deferRegistration),
163 numThreads(number_of_threads)
164{
165 _status = Idle;
166
167 checker = NULL;
168
169 if (params->checker) {

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708 activeThreads.erase(isActive);
709
710 removeThread(tid);
711 }
712*/
713}
714
715template <class Impl>
162 deferRegistration(params->deferRegistration),
163 numThreads(number_of_threads)
164{
165 _status = Idle;
166
167 checker = NULL;
168
169 if (params->checker) {

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708 activeThreads.erase(isActive);
709
710 removeThread(tid);
711 }
712*/
713}
714
715template <class Impl>
716void
717FullO3CPU<Impl>::switchOut()
716bool
717FullO3CPU<Impl>::drain(Event *drain_event)
718{
718{
719 switchCount = 0;
720 fetch.switchOut();
721 decode.switchOut();
722 rename.switchOut();
723 iew.switchOut();
724 commit.switchOut();
719 drainCount = 0;
720 drainEvent = drain_event;
721 fetch.drain();
722 decode.drain();
723 rename.drain();
724 iew.drain();
725 commit.drain();
725
726 // Wake the CPU and record activity so everything can drain out if
727 // the CPU is currently idle.
728 wakeCPU();
729 activityRec.activity();
726
727 // Wake the CPU and record activity so everything can drain out if
728 // the CPU is currently idle.
729 wakeCPU();
730 activityRec.activity();
731
732 return false;
730}
731
732template <class Impl>
733void
733}
734
735template <class Impl>
736void
734FullO3CPU<Impl>::signalSwitched()
737FullO3CPU<Impl>::resume()
735{
738{
736 if (++switchCount == NumStages) {
737 fetch.doSwitchOut();
738 rename.doSwitchOut();
739 commit.doSwitchOut();
740 instList.clear();
741 while (!removeList.empty()) {
742 removeList.pop();
743 }
739 if (_status == SwitchedOut)
740 return;
741 fetch.resume();
742 decode.resume();
743 rename.resume();
744 iew.resume();
745 commit.resume();
744
746
745#if USE_CHECKER
746 if (checker)
747 checker->switchOut();
748#endif
747 if (!tickEvent.scheduled())
748 tickEvent.schedule(curTick);
749 _status = Running;
750}
749
751
752template <class Impl>
753void
754FullO3CPU<Impl>::signalDrained()
755{
756 if (++drainCount == NumStages) {
750 if (tickEvent.scheduled())
751 tickEvent.squash();
757 if (tickEvent.scheduled())
758 tickEvent.squash();
752 _status = SwitchedOut;
759 _status = Drained;
760 drainEvent->process();
753 }
761 }
754 assert(switchCount <= 5);
762 assert(drainCount <= 5);
755}
756
757template <class Impl>
758void
763}
764
765template <class Impl>
766void
767FullO3CPU<Impl>::switchOut()
768{
769 fetch.switchOut();
770 rename.switchOut();
771 commit.switchOut();
772 instList.clear();
773 while (!removeList.empty()) {
774 removeList.pop();
775 }
776
777 _status = SwitchedOut;
778#if USE_CHECKER
779 if (checker)
780 checker->switchOut();
781#endif
782}
783
784template <class Impl>
785void
759FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
760{
761 // Flush out any old data from the time buffers.
762 for (int i = 0; i < 10; ++i) {
763 timeBuffer.advance();
764 fetchQueue.advance();
765 decodeQueue.advance();
766 renameQueue.advance();

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787{
788 // Flush out any old data from the time buffers.
789 for (int i = 0; i < 10; ++i) {
790 timeBuffer.advance();
791 fetchQueue.advance();
792 decodeQueue.advance();
793 renameQueue.advance();

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