cpu.cc (2733:e0eac8fc5774) cpu.cc (2756:7bf0d6481df9)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 12 unchanged lines hidden (view full) ---

21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 12 unchanged lines hidden (view full) ---

21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
29 */
30
31#include "config/full_system.hh"
30 */
31
32#include "config/full_system.hh"
32#include "config/use_checker.hh"
33
34#if FULL_SYSTEM
35#include "sim/system.hh"
36#else
37#include "sim/process.hh"
38#endif
39
40#include "cpu/activity.hh"

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46#include "cpu/o3/cpu.hh"
47
48#include "sim/root.hh"
49#include "sim/stat_control.hh"
50
51using namespace std;
52using namespace TheISA;
53
33
34#if FULL_SYSTEM
35#include "sim/system.hh"
36#else
37#include "sim/process.hh"
38#endif
39
40#include "cpu/activity.hh"

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46#include "cpu/o3/cpu.hh"
47
48#include "sim/root.hh"
49#include "sim/stat_control.hh"
50
51using namespace std;
52using namespace TheISA;
53
54BaseO3CPU::BaseO3CPU(Params *params)
54BaseFullCPU::BaseFullCPU(Params *params)
55 : BaseCPU(params), cpu_id(0)
56{
57}
58
59void
55 : BaseCPU(params), cpu_id(0)
56{
57}
58
59void
60BaseO3CPU::regStats()
60BaseFullCPU::regStats()
61{
62 BaseCPU::regStats();
63}
64
65template <class Impl>
66FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
67 : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
68{

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79const char *
80FullO3CPU<Impl>::TickEvent::description()
81{
82 return "FullO3CPU tick event";
83}
84
85template <class Impl>
86FullO3CPU<Impl>::FullO3CPU(Params *params)
61{
62 BaseCPU::regStats();
63}
64
65template <class Impl>
66FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
67 : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
68{

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79const char *
80FullO3CPU<Impl>::TickEvent::description()
81{
82 return "FullO3CPU tick event";
83}
84
85template <class Impl>
86FullO3CPU<Impl>::FullO3CPU(Params *params)
87 : BaseO3CPU(params),
87 : BaseFullCPU(params),
88 tickEvent(this),
89 removeInstsThisCycle(false),
90 fetch(params),
91 decode(params),
92 rename(params),
93 iew(params),
94 commit(params),
95

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127#endif // FULL_SYSTEM
128 mem(params->mem),
129 switchCount(0),
130 deferRegistration(params->deferRegistration),
131 numThreads(number_of_threads)
132{
133 _status = Idle;
134
88 tickEvent(this),
89 removeInstsThisCycle(false),
90 fetch(params),
91 decode(params),
92 rename(params),
93 iew(params),
94 commit(params),
95

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127#endif // FULL_SYSTEM
128 mem(params->mem),
129 switchCount(0),
130 deferRegistration(params->deferRegistration),
131 numThreads(number_of_threads)
132{
133 _status = Idle;
134
135 checker = NULL;
136
137#if USE_CHECKER
138 if (params->checker) {
139 BaseCPU *temp_checker = params->checker;
140 checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
141 checker->setMemory(mem);
142#if FULL_SYSTEM
143 checker->setSystem(params->system);
144#endif
135 if (params->checker) {
136 BaseCPU *temp_checker = params->checker;
137 checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
138 checker->setMemory(mem);
139#if FULL_SYSTEM
140 checker->setSystem(params->system);
141#endif
142 } else {
143 checker = NULL;
145 }
144 }
146#endif
147
148#if !FULL_SYSTEM
149 thread.resize(number_of_threads);
150 tids.resize(number_of_threads);
151#endif
152
153 // The stages also need their CPU pointer setup. However this
154 // must be done at the upper level CPU because they have pointers

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259FullO3CPU<Impl>::~FullO3CPU()
260{
261}
262
263template <class Impl>
264void
265FullO3CPU<Impl>::fullCPURegStats()
266{
145
146#if !FULL_SYSTEM
147 thread.resize(number_of_threads);
148 tids.resize(number_of_threads);
149#endif
150
151 // The stages also need their CPU pointer setup. However this
152 // must be done at the upper level CPU because they have pointers

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257FullO3CPU<Impl>::~FullO3CPU()
258{
259}
260
261template <class Impl>
262void
263FullO3CPU<Impl>::fullCPURegStats()
264{
267 BaseO3CPU::regStats();
265 BaseFullCPU::regStats();
268
266
269 // Register any of the O3CPU's stats here.
267 // Register any of the FullCPU's stats here.
270 timesIdled
271 .name(name() + ".timesIdled")
272 .desc("Number of times that the entire CPU went into an idle state and"
273 " unscheduled itself")
274 .prereq(timesIdled);
275
276 idleCycles
277 .name(name() + ".idleCycles")

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317 totalIpc = totalCommittedInsts / simTicks;
318
319}
320
321template <class Impl>
322void
323FullO3CPU<Impl>::tick()
324{
268 timesIdled
269 .name(name() + ".timesIdled")
270 .desc("Number of times that the entire CPU went into an idle state and"
271 " unscheduled itself")
272 .prereq(timesIdled);
273
274 idleCycles
275 .name(name() + ".idleCycles")

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315 totalIpc = totalCommittedInsts / simTicks;
316
317}
318
319template <class Impl>
320void
321FullO3CPU<Impl>::tick()
322{
325 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
323 DPRINTF(FullCPU, "\n\nFullCPU: Ticking main, FullO3CPU.\n");
326
327 ++numCycles;
328
329// activity = false;
330
331 //Tick each of the stages
332 fetch.tick();
333

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416
417 commit.setThreads(thread);
418}
419
420template <class Impl>
421void
422FullO3CPU<Impl>::insertThread(unsigned tid)
423{
324
325 ++numCycles;
326
327// activity = false;
328
329 //Tick each of the stages
330 fetch.tick();
331

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414
415 commit.setThreads(thread);
416}
417
418template <class Impl>
419void
420FullO3CPU<Impl>::insertThread(unsigned tid)
421{
424 DPRINTF(O3CPU,"[tid:%i] Initializing thread data");
422 DPRINTF(FullCPU,"[tid:%i] Initializing thread data");
425 // Will change now that the PC and thread state is internal to the CPU
426 // and not in the ThreadContext.
427#if 0
428#if FULL_SYSTEM
429 ThreadContext *src_tc = system->threadContexts[tid];
430#else
431 ThreadContext *src_tc = thread[tid];
432#endif

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463 iew.resetEntries();
464#endif
465}
466
467template <class Impl>
468void
469FullO3CPU<Impl>::removeThread(unsigned tid)
470{
423 // Will change now that the PC and thread state is internal to the CPU
424 // and not in the ThreadContext.
425#if 0
426#if FULL_SYSTEM
427 ThreadContext *src_tc = system->threadContexts[tid];
428#else
429 ThreadContext *src_tc = thread[tid];
430#endif

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461 iew.resetEntries();
462#endif
463}
464
465template <class Impl>
466void
467FullO3CPU<Impl>::removeThread(unsigned tid)
468{
471 DPRINTF(O3CPU,"[tid:%i] Removing thread data");
469 DPRINTF(FullCPU,"[tid:%i] Removing thread data");
472#if 0
473 //Unbind Int Regs from Rename Map
474 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
475 PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
476
477 scoreboard.unsetReg(phys_reg);
478 freeList.addReg(phys_reg);
479 }

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509#endif
510}
511
512
513template <class Impl>
514void
515FullO3CPU<Impl>::activateWhenReady(int tid)
516{
470#if 0
471 //Unbind Int Regs from Rename Map
472 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
473 PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
474
475 scoreboard.unsetReg(phys_reg);
476 freeList.addReg(phys_reg);
477 }

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507#endif
508}
509
510
511template <class Impl>
512void
513FullO3CPU<Impl>::activateWhenReady(int tid)
514{
517 DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming"
515 DPRINTF(FullCPU,"[tid:%i]: Checking if resources are available for incoming"
518 "(e.g. PhysRegs/ROB/IQ/LSQ) \n",
519 tid);
520
521 bool ready = true;
522
523 if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) {
516 "(e.g. PhysRegs/ROB/IQ/LSQ) \n",
517 tid);
518
519 bool ready = true;
520
521 if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) {
524 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
522 DPRINTF(FullCPU,"[tid:%i] Suspending thread due to not enough "
525 "Phys. Int. Regs.\n",
526 tid);
527 ready = false;
528 } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) {
523 "Phys. Int. Regs.\n",
524 tid);
525 ready = false;
526 } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) {
529 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
527 DPRINTF(FullCPU,"[tid:%i] Suspending thread due to not enough "
530 "Phys. Float. Regs.\n",
531 tid);
532 ready = false;
533 } else if (commit.rob->numFreeEntries() >=
534 commit.rob->entryAmount(activeThreads.size() + 1)) {
528 "Phys. Float. Regs.\n",
529 tid);
530 ready = false;
531 } else if (commit.rob->numFreeEntries() >=
532 commit.rob->entryAmount(activeThreads.size() + 1)) {
535 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
533 DPRINTF(FullCPU,"[tid:%i] Suspending thread due to not enough "
536 "ROB entries.\n",
537 tid);
538 ready = false;
539 } else if (iew.instQueue.numFreeEntries() >=
540 iew.instQueue.entryAmount(activeThreads.size() + 1)) {
534 "ROB entries.\n",
535 tid);
536 ready = false;
537 } else if (iew.instQueue.numFreeEntries() >=
538 iew.instQueue.entryAmount(activeThreads.size() + 1)) {
541 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
539 DPRINTF(FullCPU,"[tid:%i] Suspending thread due to not enough "
542 "IQ entries.\n",
543 tid);
544 ready = false;
545 } else if (iew.ldstQueue.numFreeEntries() >=
546 iew.ldstQueue.entryAmount(activeThreads.size() + 1)) {
540 "IQ entries.\n",
541 tid);
542 ready = false;
543 } else if (iew.ldstQueue.numFreeEntries() >=
544 iew.ldstQueue.entryAmount(activeThreads.size() + 1)) {
547 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
545 DPRINTF(FullCPU,"[tid:%i] Suspending thread due to not enough "
548 "LSQ entries.\n",
549 tid);
550 ready = false;
551 }
552
553 if (ready) {
554 insertThread(tid);
555

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573{
574 // Needs to set each stage to running as well.
575 list<unsigned>::iterator isActive = find(
576 activeThreads.begin(), activeThreads.end(), tid);
577
578 if (isActive == activeThreads.end()) {
579 //May Need to Re-code this if the delay variable is the
580 //delay needed for thread to activate
546 "LSQ entries.\n",
547 tid);
548 ready = false;
549 }
550
551 if (ready) {
552 insertThread(tid);
553

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571{
572 // Needs to set each stage to running as well.
573 list<unsigned>::iterator isActive = find(
574 activeThreads.begin(), activeThreads.end(), tid);
575
576 if (isActive == activeThreads.end()) {
577 //May Need to Re-code this if the delay variable is the
578 //delay needed for thread to activate
581 DPRINTF(O3CPU, "Adding Thread %i to active threads list\n",
579 DPRINTF(FullCPU, "Adding Thread %i to active threads list\n",
582 tid);
583
584 activeThreads.push_back(tid);
585 }
586
587 assert(_status == Idle || _status == SwitchedOut);
588
589 scheduleTickEvent(delay);

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595
596 _status = Running;
597}
598
599template <class Impl>
600void
601FullO3CPU<Impl>::suspendContext(int tid)
602{
580 tid);
581
582 activeThreads.push_back(tid);
583 }
584
585 assert(_status == Idle || _status == SwitchedOut);
586
587 scheduleTickEvent(delay);

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593
594 _status = Running;
595}
596
597template <class Impl>
598void
599FullO3CPU<Impl>::suspendContext(int tid)
600{
603 DPRINTF(O3CPU,"[tid: %i]: Suspended ...\n", tid);
601 DPRINTF(FullCPU,"[tid: %i]: Suspended ...\n", tid);
604 unscheduleTickEvent();
605 _status = Idle;
606/*
607 //Remove From Active List, if Active
608 list<unsigned>::iterator isActive = find(
609 activeThreads.begin(), activeThreads.end(), tid);
610
611 if (isActive != activeThreads.end()) {
602 unscheduleTickEvent();
603 _status = Idle;
604/*
605 //Remove From Active List, if Active
606 list<unsigned>::iterator isActive = find(
607 activeThreads.begin(), activeThreads.end(), tid);
608
609 if (isActive != activeThreads.end()) {
612 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
610 DPRINTF(FullCPU,"[tid:%i]: Removing from active threads list\n",
613 tid);
614 activeThreads.erase(isActive);
615 }
616*/
617}
618
619template <class Impl>
620void
621FullO3CPU<Impl>::deallocateContext(int tid)
622{
611 tid);
612 activeThreads.erase(isActive);
613 }
614*/
615}
616
617template <class Impl>
618void
619FullO3CPU<Impl>::deallocateContext(int tid)
620{
623 DPRINTF(O3CPU,"[tid:%i]: Deallocating ...", tid);
621 DPRINTF(FullCPU,"[tid:%i]: Deallocating ...", tid);
624/*
625 //Remove From Active List, if Active
626 list<unsigned>::iterator isActive = find(
627 activeThreads.begin(), activeThreads.end(), tid);
628
629 if (isActive != activeThreads.end()) {
622/*
623 //Remove From Active List, if Active
624 list<unsigned>::iterator isActive = find(
625 activeThreads.begin(), activeThreads.end(), tid);
626
627 if (isActive != activeThreads.end()) {
630 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
628 DPRINTF(FullCPU,"[tid:%i]: Removing from active threads list\n",
631 tid);
632 activeThreads.erase(isActive);
633
634 removeThread(tid);
635 }
636*/
637}
638
639template <class Impl>
640void
641FullO3CPU<Impl>::haltContext(int tid)
642{
629 tid);
630 activeThreads.erase(isActive);
631
632 removeThread(tid);
633 }
634*/
635}
636
637template <class Impl>
638void
639FullO3CPU<Impl>::haltContext(int tid)
640{
643 DPRINTF(O3CPU,"[tid:%i]: Halted ...", tid);
641 DPRINTF(FullCPU,"[tid:%i]: Halted ...", tid);
644/*
645 //Remove From Active List, if Active
646 list<unsigned>::iterator isActive = find(
647 activeThreads.begin(), activeThreads.end(), tid);
648
649 if (isActive != activeThreads.end()) {
642/*
643 //Remove From Active List, if Active
644 list<unsigned>::iterator isActive = find(
645 activeThreads.begin(), activeThreads.end(), tid);
646
647 if (isActive != activeThreads.end()) {
650 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
648 DPRINTF(FullCPU,"[tid:%i]: Removing from active threads list\n",
651 tid);
652 activeThreads.erase(isActive);
653
654 removeThread(tid);
655 }
656*/
657}
658

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728 int tid = 0;
729
730 list<unsigned>::iterator isActive = find(
731 activeThreads.begin(), activeThreads.end(), tid);
732
733 if (isActive == activeThreads.end()) {
734 //May Need to Re-code this if the delay variable is the delay
735 //needed for thread to activate
649 tid);
650 activeThreads.erase(isActive);
651
652 removeThread(tid);
653 }
654*/
655}
656

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726 int tid = 0;
727
728 list<unsigned>::iterator isActive = find(
729 activeThreads.begin(), activeThreads.end(), tid);
730
731 if (isActive == activeThreads.end()) {
732 //May Need to Re-code this if the delay variable is the delay
733 //needed for thread to activate
736 DPRINTF(O3CPU, "Adding Thread %i to active threads list\n",
734 DPRINTF(FullCPU, "Adding Thread %i to active threads list\n",
737 tid);
738
739 activeThreads.push_back(tid);
740 }
741
742 // Set all statuses to active, schedule the CPU's tick event.
743 // @todo: Fix up statuses so this is handled properly
744 for (int i = 0; i < threadContexts.size(); ++i) {

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920
921template <class Impl>
922void
923FullO3CPU<Impl>::setNextPC(uint64_t val,unsigned tid)
924{
925 commit.setNextPC(val, tid);
926}
927
735 tid);
736
737 activeThreads.push_back(tid);
738 }
739
740 // Set all statuses to active, schedule the CPU's tick event.
741 // @todo: Fix up statuses so this is handled properly
742 for (int i = 0; i < threadContexts.size(); ++i) {

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918
919template <class Impl>
920void
921FullO3CPU<Impl>::setNextPC(uint64_t val,unsigned tid)
922{
923 commit.setNextPC(val, tid);
924}
925
926#if THE_ISA != ALPHA_ISA
928template <class Impl>
927template <class Impl>
928uint64_t
929FullO3CPU<Impl>::readNextNPC(unsigned tid)
930{
931 return commit.readNextNPC(tid);
932}
933
934template <class Impl>
935void
936FullO3CPU<Impl>::setNextNNPC(uint64_t val,unsigned tid)
937{
938 commit.setNextNPC(val, tid);
939}
940#endif
941
942template <class Impl>
929typename FullO3CPU<Impl>::ListIt
930FullO3CPU<Impl>::addInst(DynInstPtr &inst)
931{
932 instList.push_back(inst);
933
934 return --(instList.end());
935}
936

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956
957 removeList.push(inst->getInstListIt());
958}
959
960template <class Impl>
961void
962FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
963{
943typename FullO3CPU<Impl>::ListIt
944FullO3CPU<Impl>::addInst(DynInstPtr &inst)
945{
946 instList.push_back(inst);
947
948 return --(instList.end());
949}
950

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970
971 removeList.push(inst->getInstListIt());
972}
973
974template <class Impl>
975void
976FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
977{
964 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %#x "
978 DPRINTF(FullCPU, "FullCPU: Removing committed instruction [tid:%i] PC %#x "
965 "[sn:%lli]\n",
966 inst->threadNumber, inst->readPC(), inst->seqNum);
967
968 removeInstsThisCycle = true;
969
970 // Remove the front instruction.
971 removeList.push(inst->getInstListIt());
972}
973
974template <class Impl>
975void
976FullO3CPU<Impl>::removeInstsNotInROB(unsigned tid)
977{
979 "[sn:%lli]\n",
980 inst->threadNumber, inst->readPC(), inst->seqNum);
981
982 removeInstsThisCycle = true;
983
984 // Remove the front instruction.
985 removeList.push(inst->getInstListIt());
986}
987
988template <class Impl>
989void
990FullO3CPU<Impl>::removeInstsNotInROB(unsigned tid)
991{
978 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
992 DPRINTF(FullCPU, "FullCPU: Thread %i: Deleting instructions from instruction"
979 " list.\n", tid);
980
981 ListIt end_it;
982
983 bool rob_empty = false;
984
985 if (instList.empty()) {
986 return;
987 } else if (rob.isEmpty(/*tid*/)) {
993 " list.\n", tid);
994
995 ListIt end_it;
996
997 bool rob_empty = false;
998
999 if (instList.empty()) {
1000 return;
1001 } else if (rob.isEmpty(/*tid*/)) {
988 DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1002 DPRINTF(FullCPU, "FullCPU: ROB is empty, squashing all insts.\n");
989 end_it = instList.begin();
990 rob_empty = true;
991 } else {
992 end_it = (rob.readTailInst(tid))->getInstListIt();
1003 end_it = instList.begin();
1004 rob_empty = true;
1005 } else {
1006 end_it = (rob.readTailInst(tid))->getInstListIt();
993 DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1007 DPRINTF(FullCPU, "FullCPU: ROB is not empty, squashing insts not in ROB.\n");
994 }
995
996 removeInstsThisCycle = true;
997
998 ListIt inst_it = instList.end();
999
1000 inst_it--;
1001

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1024 assert(!instList.empty());
1025
1026 removeInstsThisCycle = true;
1027
1028 ListIt inst_iter = instList.end();
1029
1030 inst_iter--;
1031
1008 }
1009
1010 removeInstsThisCycle = true;
1011
1012 ListIt inst_it = instList.end();
1013
1014 inst_it--;
1015

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1038 assert(!instList.empty());
1039
1040 removeInstsThisCycle = true;
1041
1042 ListIt inst_iter = instList.end();
1043
1044 inst_iter--;
1045
1032 DPRINTF(O3CPU, "Deleting instructions from instruction "
1046 DPRINTF(FullCPU, "FullCPU: Deleting instructions from instruction "
1033 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1034 tid, seq_num, (*inst_iter)->seqNum);
1035
1036 while ((*inst_iter)->seqNum > seq_num) {
1037
1038 bool break_loop = (inst_iter == instList.begin());
1039
1040 squashInstIt(inst_iter, tid);

--- 5 unchanged lines hidden (view full) ---

1046 }
1047}
1048
1049template <class Impl>
1050inline void
1051FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, const unsigned &tid)
1052{
1053 if ((*instIt)->threadNumber == tid) {
1047 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1048 tid, seq_num, (*inst_iter)->seqNum);
1049
1050 while ((*inst_iter)->seqNum > seq_num) {
1051
1052 bool break_loop = (inst_iter == instList.begin());
1053
1054 squashInstIt(inst_iter, tid);

--- 5 unchanged lines hidden (view full) ---

1060 }
1061}
1062
1063template <class Impl>
1064inline void
1065FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, const unsigned &tid)
1066{
1067 if ((*instIt)->threadNumber == tid) {
1054 DPRINTF(O3CPU, "Squashing instruction, "
1068 DPRINTF(FullCPU, "FullCPU: Squashing instruction, "
1055 "[tid:%i] [sn:%lli] PC %#x\n",
1056 (*instIt)->threadNumber,
1057 (*instIt)->seqNum,
1058 (*instIt)->readPC());
1059
1060 // Mark it as squashed.
1061 (*instIt)->setSquashed();
1062

--- 4 unchanged lines hidden (view full) ---

1067 }
1068}
1069
1070template <class Impl>
1071void
1072FullO3CPU<Impl>::cleanUpRemovedInsts()
1073{
1074 while (!removeList.empty()) {
1069 "[tid:%i] [sn:%lli] PC %#x\n",
1070 (*instIt)->threadNumber,
1071 (*instIt)->seqNum,
1072 (*instIt)->readPC());
1073
1074 // Mark it as squashed.
1075 (*instIt)->setSquashed();
1076

--- 4 unchanged lines hidden (view full) ---

1081 }
1082}
1083
1084template <class Impl>
1085void
1086FullO3CPU<Impl>::cleanUpRemovedInsts()
1087{
1088 while (!removeList.empty()) {
1075 DPRINTF(O3CPU, "Removing instruction, "
1089 DPRINTF(FullCPU, "FullCPU: Removing instruction, "
1076 "[tid:%i] [sn:%lli] PC %#x\n",
1077 (*removeList.front())->threadNumber,
1078 (*removeList.front())->seqNum,
1079 (*removeList.front())->readPC());
1080
1081 instList.erase(removeList.front());
1082
1083 removeList.pop();

--- 108 unchanged lines hidden --- 		1090 "[tid:%i] [sn:%lli] PC %#x\n",
1091 (*removeList.front())->threadNumber,
1092 (*removeList.front())->seqNum,
1093 (*removeList.front())->readPC());
1094
1095 instList.erase(removeList.front());
1096
1097 removeList.pop();

--- 108 unchanged lines hidden ---