cpu.cc (2690:f4337c0d9e6f) cpu.cc (2733:e0eac8fc5774)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include "config/full_system.hh"
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include "config/full_system.hh"
32#include "config/use_checker.hh"
32
33#if FULL_SYSTEM
34#include "sim/system.hh"
35#else
36#include "sim/process.hh"
37#endif
38
39#include "cpu/activity.hh"

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45#include "cpu/o3/cpu.hh"
46
47#include "sim/root.hh"
48#include "sim/stat_control.hh"
49
50using namespace std;
51using namespace TheISA;
52
33
34#if FULL_SYSTEM
35#include "sim/system.hh"
36#else
37#include "sim/process.hh"
38#endif
39
40#include "cpu/activity.hh"

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46#include "cpu/o3/cpu.hh"
47
48#include "sim/root.hh"
49#include "sim/stat_control.hh"
50
51using namespace std;
52using namespace TheISA;
53
53BaseFullCPU::BaseFullCPU(Params *params)
54BaseO3CPU::BaseO3CPU(Params *params)
54 : BaseCPU(params), cpu_id(0)
55{
56}
57
58void
55 : BaseCPU(params), cpu_id(0)
56{
57}
58
59void
59BaseFullCPU::regStats()
60BaseO3CPU::regStats()
60{
61 BaseCPU::regStats();
62}
63
64template <class Impl>
65FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
66 : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
67{

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78const char *
79FullO3CPU<Impl>::TickEvent::description()
80{
81 return "FullO3CPU tick event";
82}
83
84template <class Impl>
85FullO3CPU<Impl>::FullO3CPU(Params *params)
61{
62 BaseCPU::regStats();
63}
64
65template <class Impl>
66FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
67 : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
68{

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79const char *
80FullO3CPU<Impl>::TickEvent::description()
81{
82 return "FullO3CPU tick event";
83}
84
85template <class Impl>
86FullO3CPU<Impl>::FullO3CPU(Params *params)
86 : BaseFullCPU(params),
87 : BaseO3CPU(params),
87 tickEvent(this),
88 removeInstsThisCycle(false),
89 fetch(params),
90 decode(params),
91 rename(params),
92 iew(params),
93 commit(params),
94

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126#endif // FULL_SYSTEM
127 mem(params->mem),
128 switchCount(0),
129 deferRegistration(params->deferRegistration),
130 numThreads(number_of_threads)
131{
132 _status = Idle;
133
88 tickEvent(this),
89 removeInstsThisCycle(false),
90 fetch(params),
91 decode(params),
92 rename(params),
93 iew(params),
94 commit(params),
95

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127#endif // FULL_SYSTEM
128 mem(params->mem),
129 switchCount(0),
130 deferRegistration(params->deferRegistration),
131 numThreads(number_of_threads)
132{
133 _status = Idle;
134
135 checker = NULL;
136
137#if USE_CHECKER
134 if (params->checker) {
135 BaseCPU *temp_checker = params->checker;
136 checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
137 checker->setMemory(mem);
138#if FULL_SYSTEM
139 checker->setSystem(params->system);
140#endif
138 if (params->checker) {
139 BaseCPU *temp_checker = params->checker;
140 checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
141 checker->setMemory(mem);
142#if FULL_SYSTEM
143 checker->setSystem(params->system);
144#endif
141 } else {
142 checker = NULL;
143 }
145 }
146#endif
144
145#if !FULL_SYSTEM
146 thread.resize(number_of_threads);
147 tids.resize(number_of_threads);
148#endif
149
150 // The stages also need their CPU pointer setup. However this
151 // must be done at the upper level CPU because they have pointers

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256FullO3CPU<Impl>::~FullO3CPU()
257{
258}
259
260template <class Impl>
261void
262FullO3CPU<Impl>::fullCPURegStats()
263{
147
148#if !FULL_SYSTEM
149 thread.resize(number_of_threads);
150 tids.resize(number_of_threads);
151#endif
152
153 // The stages also need their CPU pointer setup. However this
154 // must be done at the upper level CPU because they have pointers

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259FullO3CPU<Impl>::~FullO3CPU()
260{
261}
262
263template <class Impl>
264void
265FullO3CPU<Impl>::fullCPURegStats()
266{
264 BaseFullCPU::regStats();
267 BaseO3CPU::regStats();
265
268
266 // Register any of the FullCPU's stats here.
269 // Register any of the O3CPU's stats here.
267 timesIdled
268 .name(name() + ".timesIdled")
269 .desc("Number of times that the entire CPU went into an idle state and"
270 " unscheduled itself")
271 .prereq(timesIdled);
272
273 idleCycles
274 .name(name() + ".idleCycles")

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314 totalIpc = totalCommittedInsts / simTicks;
315
316}
317
318template <class Impl>
319void
320FullO3CPU<Impl>::tick()
321{
270 timesIdled
271 .name(name() + ".timesIdled")
272 .desc("Number of times that the entire CPU went into an idle state and"
273 " unscheduled itself")
274 .prereq(timesIdled);
275
276 idleCycles
277 .name(name() + ".idleCycles")

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317 totalIpc = totalCommittedInsts / simTicks;
318
319}
320
321template <class Impl>
322void
323FullO3CPU<Impl>::tick()
324{
322 DPRINTF(FullCPU, "\n\nFullCPU: Ticking main, FullO3CPU.\n");
325 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
323
324 ++numCycles;
325
326// activity = false;
327
328 //Tick each of the stages
329 fetch.tick();
330

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413
414 commit.setThreads(thread);
415}
416
417template <class Impl>
418void
419FullO3CPU<Impl>::insertThread(unsigned tid)
420{
326
327 ++numCycles;
328
329// activity = false;
330
331 //Tick each of the stages
332 fetch.tick();
333

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416
417 commit.setThreads(thread);
418}
419
420template <class Impl>
421void
422FullO3CPU<Impl>::insertThread(unsigned tid)
423{
421 DPRINTF(FullCPU,"[tid:%i] Initializing thread data");
424 DPRINTF(O3CPU,"[tid:%i] Initializing thread data");
422 // Will change now that the PC and thread state is internal to the CPU
423 // and not in the ThreadContext.
424#if 0
425#if FULL_SYSTEM
426 ThreadContext *src_tc = system->threadContexts[tid];
427#else
428 ThreadContext *src_tc = thread[tid];
429#endif

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460 iew.resetEntries();
461#endif
462}
463
464template <class Impl>
465void
466FullO3CPU<Impl>::removeThread(unsigned tid)
467{
425 // Will change now that the PC and thread state is internal to the CPU
426 // and not in the ThreadContext.
427#if 0
428#if FULL_SYSTEM
429 ThreadContext *src_tc = system->threadContexts[tid];
430#else
431 ThreadContext *src_tc = thread[tid];
432#endif

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463 iew.resetEntries();
464#endif
465}
466
467template <class Impl>
468void
469FullO3CPU<Impl>::removeThread(unsigned tid)
470{
468 DPRINTF(FullCPU,"[tid:%i] Removing thread data");
471 DPRINTF(O3CPU,"[tid:%i] Removing thread data");
469#if 0
470 //Unbind Int Regs from Rename Map
471 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
472 PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
473
474 scoreboard.unsetReg(phys_reg);
475 freeList.addReg(phys_reg);
476 }

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506#endif
507}
508
509
510template <class Impl>
511void
512FullO3CPU<Impl>::activateWhenReady(int tid)
513{
472#if 0
473 //Unbind Int Regs from Rename Map
474 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
475 PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
476
477 scoreboard.unsetReg(phys_reg);
478 freeList.addReg(phys_reg);
479 }

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509#endif
510}
511
512
513template <class Impl>
514void
515FullO3CPU<Impl>::activateWhenReady(int tid)
516{
514 DPRINTF(FullCPU,"[tid:%i]: Checking if resources are available for incoming"
517 DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming"
515 "(e.g. PhysRegs/ROB/IQ/LSQ) \n",
516 tid);
517
518 bool ready = true;
519
520 if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) {
518 "(e.g. PhysRegs/ROB/IQ/LSQ) \n",
519 tid);
520
521 bool ready = true;
522
523 if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) {
521 DPRINTF(FullCPU,"[tid:%i] Suspending thread due to not enough "
524 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
522 "Phys. Int. Regs.\n",
523 tid);
524 ready = false;
525 } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) {
525 "Phys. Int. Regs.\n",
526 tid);
527 ready = false;
528 } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) {
526 DPRINTF(FullCPU,"[tid:%i] Suspending thread due to not enough "
529 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
527 "Phys. Float. Regs.\n",
528 tid);
529 ready = false;
530 } else if (commit.rob->numFreeEntries() >=
531 commit.rob->entryAmount(activeThreads.size() + 1)) {
530 "Phys. Float. Regs.\n",
531 tid);
532 ready = false;
533 } else if (commit.rob->numFreeEntries() >=
534 commit.rob->entryAmount(activeThreads.size() + 1)) {
532 DPRINTF(FullCPU,"[tid:%i] Suspending thread due to not enough "
535 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
533 "ROB entries.\n",
534 tid);
535 ready = false;
536 } else if (iew.instQueue.numFreeEntries() >=
537 iew.instQueue.entryAmount(activeThreads.size() + 1)) {
536 "ROB entries.\n",
537 tid);
538 ready = false;
539 } else if (iew.instQueue.numFreeEntries() >=
540 iew.instQueue.entryAmount(activeThreads.size() + 1)) {
538 DPRINTF(FullCPU,"[tid:%i] Suspending thread due to not enough "
541 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
539 "IQ entries.\n",
540 tid);
541 ready = false;
542 } else if (iew.ldstQueue.numFreeEntries() >=
543 iew.ldstQueue.entryAmount(activeThreads.size() + 1)) {
542 "IQ entries.\n",
543 tid);
544 ready = false;
545 } else if (iew.ldstQueue.numFreeEntries() >=
546 iew.ldstQueue.entryAmount(activeThreads.size() + 1)) {
544 DPRINTF(FullCPU,"[tid:%i] Suspending thread due to not enough "
547 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
545 "LSQ entries.\n",
546 tid);
547 ready = false;
548 }
549
550 if (ready) {
551 insertThread(tid);
552

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570{
571 // Needs to set each stage to running as well.
572 list<unsigned>::iterator isActive = find(
573 activeThreads.begin(), activeThreads.end(), tid);
574
575 if (isActive == activeThreads.end()) {
576 //May Need to Re-code this if the delay variable is the
577 //delay needed for thread to activate
548 "LSQ entries.\n",
549 tid);
550 ready = false;
551 }
552
553 if (ready) {
554 insertThread(tid);
555

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573{
574 // Needs to set each stage to running as well.
575 list<unsigned>::iterator isActive = find(
576 activeThreads.begin(), activeThreads.end(), tid);
577
578 if (isActive == activeThreads.end()) {
579 //May Need to Re-code this if the delay variable is the
580 //delay needed for thread to activate
578 DPRINTF(FullCPU, "Adding Thread %i to active threads list\n",
581 DPRINTF(O3CPU, "Adding Thread %i to active threads list\n",
579 tid);
580
581 activeThreads.push_back(tid);
582 }
583
584 assert(_status == Idle || _status == SwitchedOut);
585
586 scheduleTickEvent(delay);

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592
593 _status = Running;
594}
595
596template <class Impl>
597void
598FullO3CPU<Impl>::suspendContext(int tid)
599{
582 tid);
583
584 activeThreads.push_back(tid);
585 }
586
587 assert(_status == Idle || _status == SwitchedOut);
588
589 scheduleTickEvent(delay);

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595
596 _status = Running;
597}
598
599template <class Impl>
600void
601FullO3CPU<Impl>::suspendContext(int tid)
602{
600 DPRINTF(FullCPU,"[tid: %i]: Suspended ...\n", tid);
603 DPRINTF(O3CPU,"[tid: %i]: Suspended ...\n", tid);
601 unscheduleTickEvent();
602 _status = Idle;
603/*
604 //Remove From Active List, if Active
605 list<unsigned>::iterator isActive = find(
606 activeThreads.begin(), activeThreads.end(), tid);
607
608 if (isActive != activeThreads.end()) {
604 unscheduleTickEvent();
605 _status = Idle;
606/*
607 //Remove From Active List, if Active
608 list<unsigned>::iterator isActive = find(
609 activeThreads.begin(), activeThreads.end(), tid);
610
611 if (isActive != activeThreads.end()) {
609 DPRINTF(FullCPU,"[tid:%i]: Removing from active threads list\n",
612 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
610 tid);
611 activeThreads.erase(isActive);
612 }
613*/
614}
615
616template <class Impl>
617void
618FullO3CPU<Impl>::deallocateContext(int tid)
619{
613 tid);
614 activeThreads.erase(isActive);
615 }
616*/
617}
618
619template <class Impl>
620void
621FullO3CPU<Impl>::deallocateContext(int tid)
622{
620 DPRINTF(FullCPU,"[tid:%i]: Deallocating ...", tid);
623 DPRINTF(O3CPU,"[tid:%i]: Deallocating ...", tid);
621/*
622 //Remove From Active List, if Active
623 list<unsigned>::iterator isActive = find(
624 activeThreads.begin(), activeThreads.end(), tid);
625
626 if (isActive != activeThreads.end()) {
624/*
625 //Remove From Active List, if Active
626 list<unsigned>::iterator isActive = find(
627 activeThreads.begin(), activeThreads.end(), tid);
628
629 if (isActive != activeThreads.end()) {
627 DPRINTF(FullCPU,"[tid:%i]: Removing from active threads list\n",
630 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
628 tid);
629 activeThreads.erase(isActive);
630
631 removeThread(tid);
632 }
633*/
634}
635
636template <class Impl>
637void
638FullO3CPU<Impl>::haltContext(int tid)
639{
631 tid);
632 activeThreads.erase(isActive);
633
634 removeThread(tid);
635 }
636*/
637}
638
639template <class Impl>
640void
641FullO3CPU<Impl>::haltContext(int tid)
642{
640 DPRINTF(FullCPU,"[tid:%i]: Halted ...", tid);
643 DPRINTF(O3CPU,"[tid:%i]: Halted ...", tid);
641/*
642 //Remove From Active List, if Active
643 list<unsigned>::iterator isActive = find(
644 activeThreads.begin(), activeThreads.end(), tid);
645
646 if (isActive != activeThreads.end()) {
644/*
645 //Remove From Active List, if Active
646 list<unsigned>::iterator isActive = find(
647 activeThreads.begin(), activeThreads.end(), tid);
648
649 if (isActive != activeThreads.end()) {
647 DPRINTF(FullCPU,"[tid:%i]: Removing from active threads list\n",
650 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
648 tid);
649 activeThreads.erase(isActive);
650
651 removeThread(tid);
652 }
653*/
654}
655

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725 int tid = 0;
726
727 list<unsigned>::iterator isActive = find(
728 activeThreads.begin(), activeThreads.end(), tid);
729
730 if (isActive == activeThreads.end()) {
731 //May Need to Re-code this if the delay variable is the delay
732 //needed for thread to activate
651 tid);
652 activeThreads.erase(isActive);
653
654 removeThread(tid);
655 }
656*/
657}
658

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728 int tid = 0;
729
730 list<unsigned>::iterator isActive = find(
731 activeThreads.begin(), activeThreads.end(), tid);
732
733 if (isActive == activeThreads.end()) {
734 //May Need to Re-code this if the delay variable is the delay
735 //needed for thread to activate
733 DPRINTF(FullCPU, "Adding Thread %i to active threads list\n",
736 DPRINTF(O3CPU, "Adding Thread %i to active threads list\n",
734 tid);
735
736 activeThreads.push_back(tid);
737 }
738
739 // Set all statuses to active, schedule the CPU's tick event.
740 // @todo: Fix up statuses so this is handled properly
741 for (int i = 0; i < threadContexts.size(); ++i) {

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953
954 removeList.push(inst->getInstListIt());
955}
956
957template <class Impl>
958void
959FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
960{
737 tid);
738
739 activeThreads.push_back(tid);
740 }
741
742 // Set all statuses to active, schedule the CPU's tick event.
743 // @todo: Fix up statuses so this is handled properly
744 for (int i = 0; i < threadContexts.size(); ++i) {

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956
957 removeList.push(inst->getInstListIt());
958}
959
960template <class Impl>
961void
962FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
963{
961 DPRINTF(FullCPU, "FullCPU: Removing committed instruction [tid:%i] PC %#x "
964 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %#x "
962 "[sn:%lli]\n",
963 inst->threadNumber, inst->readPC(), inst->seqNum);
964
965 removeInstsThisCycle = true;
966
967 // Remove the front instruction.
968 removeList.push(inst->getInstListIt());
969}
970
971template <class Impl>
972void
973FullO3CPU<Impl>::removeInstsNotInROB(unsigned tid)
974{
965 "[sn:%lli]\n",
966 inst->threadNumber, inst->readPC(), inst->seqNum);
967
968 removeInstsThisCycle = true;
969
970 // Remove the front instruction.
971 removeList.push(inst->getInstListIt());
972}
973
974template <class Impl>
975void
976FullO3CPU<Impl>::removeInstsNotInROB(unsigned tid)
977{
975 DPRINTF(FullCPU, "FullCPU: Thread %i: Deleting instructions from instruction"
978 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
976 " list.\n", tid);
977
978 ListIt end_it;
979
980 bool rob_empty = false;
981
982 if (instList.empty()) {
983 return;
984 } else if (rob.isEmpty(/*tid*/)) {
979 " list.\n", tid);
980
981 ListIt end_it;
982
983 bool rob_empty = false;
984
985 if (instList.empty()) {
986 return;
987 } else if (rob.isEmpty(/*tid*/)) {
985 DPRINTF(FullCPU, "FullCPU: ROB is empty, squashing all insts.\n");
988 DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
986 end_it = instList.begin();
987 rob_empty = true;
988 } else {
989 end_it = (rob.readTailInst(tid))->getInstListIt();
989 end_it = instList.begin();
990 rob_empty = true;
991 } else {
992 end_it = (rob.readTailInst(tid))->getInstListIt();
990 DPRINTF(FullCPU, "FullCPU: ROB is not empty, squashing insts not in ROB.\n");
993 DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
991 }
992
993 removeInstsThisCycle = true;
994
995 ListIt inst_it = instList.end();
996
997 inst_it--;
998

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1021 assert(!instList.empty());
1022
1023 removeInstsThisCycle = true;
1024
1025 ListIt inst_iter = instList.end();
1026
1027 inst_iter--;
1028
994 }
995
996 removeInstsThisCycle = true;
997
998 ListIt inst_it = instList.end();
999
1000 inst_it--;
1001

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1024 assert(!instList.empty());
1025
1026 removeInstsThisCycle = true;
1027
1028 ListIt inst_iter = instList.end();
1029
1030 inst_iter--;
1031
1029 DPRINTF(FullCPU, "FullCPU: Deleting instructions from instruction "
1032 DPRINTF(O3CPU, "Deleting instructions from instruction "
1030 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1031 tid, seq_num, (*inst_iter)->seqNum);
1032
1033 while ((*inst_iter)->seqNum > seq_num) {
1034
1035 bool break_loop = (inst_iter == instList.begin());
1036
1037 squashInstIt(inst_iter, tid);

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1043 }
1044}
1045
1046template <class Impl>
1047inline void
1048FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, const unsigned &tid)
1049{
1050 if ((*instIt)->threadNumber == tid) {
1033 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1034 tid, seq_num, (*inst_iter)->seqNum);
1035
1036 while ((*inst_iter)->seqNum > seq_num) {
1037
1038 bool break_loop = (inst_iter == instList.begin());
1039
1040 squashInstIt(inst_iter, tid);

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1046 }
1047}
1048
1049template <class Impl>
1050inline void
1051FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, const unsigned &tid)
1052{
1053 if ((*instIt)->threadNumber == tid) {
1051 DPRINTF(FullCPU, "FullCPU: Squashing instruction, "
1054 DPRINTF(O3CPU, "Squashing instruction, "
1052 "[tid:%i] [sn:%lli] PC %#x\n",
1053 (*instIt)->threadNumber,
1054 (*instIt)->seqNum,
1055 (*instIt)->readPC());
1056
1057 // Mark it as squashed.
1058 (*instIt)->setSquashed();
1059

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1064 }
1065}
1066
1067template <class Impl>
1068void
1069FullO3CPU<Impl>::cleanUpRemovedInsts()
1070{
1071 while (!removeList.empty()) {
1055 "[tid:%i] [sn:%lli] PC %#x\n",
1056 (*instIt)->threadNumber,
1057 (*instIt)->seqNum,
1058 (*instIt)->readPC());
1059
1060 // Mark it as squashed.
1061 (*instIt)->setSquashed();
1062

--- 4 unchanged lines hidden (view full) ---

1067 }
1068}
1069
1070template <class Impl>
1071void
1072FullO3CPU<Impl>::cleanUpRemovedInsts()
1073{
1074 while (!removeList.empty()) {
1072 DPRINTF(FullCPU, "FullCPU: Removing instruction, "
1075 DPRINTF(O3CPU, "Removing instruction, "
1073 "[tid:%i] [sn:%lli] PC %#x\n",
1074 (*removeList.front())->threadNumber,
1075 (*removeList.front())->seqNum,
1076 (*removeList.front())->readPC());
1077
1078 instList.erase(removeList.front());
1079
1080 removeList.pop();

--- 108 unchanged lines hidden --- 		1076 "[tid:%i] [sn:%lli] PC %#x\n",
1077 (*removeList.front())->threadNumber,
1078 (*removeList.front())->seqNum,
1079 (*removeList.front())->readPC());
1080
1081 instList.erase(removeList.front());
1082
1083 removeList.pop();

--- 108 unchanged lines hidden ---