cpu.cc (14194:967b9c450b04) cpu.cc (14195:c5efdb3319aa)
1/*
2 * Copyright (c) 2011-2012, 2014, 2016, 2017, 2019 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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85}
86
87void
88BaseO3CPU::regStats()
89{
90 BaseCPU::regStats();
91}
92
1/*
2 * Copyright (c) 2011-2012, 2014, 2016, 2017, 2019 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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85}
86
87void
88BaseO3CPU::regStats()
89{
90 BaseCPU::regStats();
91}
92
93template<class Impl>
94bool
95FullO3CPU<Impl>::IcachePort::recvTimingResp(PacketPtr pkt)
96{
97 DPRINTF(O3CPU, "Fetch unit received timing\n");
98 // We shouldn't ever get a cacheable block in Modified state
99 assert(pkt->req->isUncacheable() ||
100 !(pkt->cacheResponding() && !pkt->hasSharers()));
101 fetch->processCacheCompletion(pkt);
102
103 return true;
104}
105
106template<class Impl>
107void
108FullO3CPU<Impl>::IcachePort::recvReqRetry()
109{
110 fetch->recvReqRetry();
111}
112
113template <class Impl>
114FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
115 : BaseO3CPU(params),
116 itb(params->itb),
117 dtb(params->dtb),
118 tickEvent([this]{ tick(); }, "FullO3CPU tick",
119 false, Event::CPU_Tick_Pri),
120 threadExitEvent([this]{ exitThreads(); }, "FullO3CPU exit threads",

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143
144 rob(this, params),
145
146 scoreboard(name() + ".scoreboard",
147 regFile.totalNumPhysRegs()),
148
149 isa(numThreads, NULL),
150
93template <class Impl>
94FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
95 : BaseO3CPU(params),
96 itb(params->itb),
97 dtb(params->dtb),
98 tickEvent([this]{ tick(); }, "FullO3CPU tick",
99 false, Event::CPU_Tick_Pri),
100 threadExitEvent([this]{ exitThreads(); }, "FullO3CPU exit threads",

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123
124 rob(this, params),
125
126 scoreboard(name() + ".scoreboard",
127 regFile.totalNumPhysRegs()),
128
129 isa(numThreads, NULL),
130
151 icachePort(&fetch, this),
152
153 timeBuffer(params->backComSize, params->forwardComSize),
154 fetchQueue(params->backComSize, params->forwardComSize),
155 decodeQueue(params->backComSize, params->forwardComSize),
156 renameQueue(params->backComSize, params->forwardComSize),
157 iewQueue(params->backComSize, params->forwardComSize),
158 activityRec(name(), NumStages,
159 params->backComSize + params->forwardComSize,
160 params->activity),

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167 _status = Running;
168 } else {
169 _status = SwitchedOut;
170 }
171
172 if (params->checker) {
173 BaseCPU *temp_checker = params->checker;
174 checker = dynamic_cast<Checker<Impl> *>(temp_checker);
131 timeBuffer(params->backComSize, params->forwardComSize),
132 fetchQueue(params->backComSize, params->forwardComSize),
133 decodeQueue(params->backComSize, params->forwardComSize),
134 renameQueue(params->backComSize, params->forwardComSize),
135 iewQueue(params->backComSize, params->forwardComSize),
136 activityRec(name(), NumStages,
137 params->backComSize + params->forwardComSize,
138 params->activity),

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145 _status = Running;
146 } else {
147 _status = SwitchedOut;
148 }
149
150 if (params->checker) {
151 BaseCPU *temp_checker = params->checker;
152 checker = dynamic_cast<Checker<Impl> *>(temp_checker);
175 checker->setIcachePort(&icachePort);
153 checker->setIcachePort(&this->fetch.getInstPort());
176 checker->setSystem(params->system);
177 } else {
178 checker = NULL;
179 }
180
181 if (!FullSystem) {
182 thread.resize(numThreads);
183 tids.resize(numThreads);

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155 } else {
156 checker = NULL;
157 }
158
159 if (!FullSystem) {
160 thread.resize(numThreads);
161 tids.resize(numThreads);

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