cpu.cc (13611:c8b7847b4171) cpu.cc (13622:ba31c2a23eca)
1/*
2 * Copyright (c) 2011-2012, 2014, 2016, 2017, 2019 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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1374FullO3CPU<Impl>::getWritableVecPredReg(PhysRegIdPtr phys_reg)
1375 -> VecPredRegContainer&
1376{
1377 vecPredRegfileWrites++;
1378 return regFile.getWritableVecPredReg(phys_reg);
1379}
1380
1381template <class Impl>
1/*
2 * Copyright (c) 2011-2012, 2014, 2016, 2017, 2019 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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1374FullO3CPU<Impl>::getWritableVecPredReg(PhysRegIdPtr phys_reg)
1375 -> VecPredRegContainer&
1376{
1377 vecPredRegfileWrites++;
1378 return regFile.getWritableVecPredReg(phys_reg);
1379}
1380
1381template <class Impl>
1382CCReg
1382RegVal
1383FullO3CPU<Impl>::readCCReg(PhysRegIdPtr phys_reg)
1384{
1385 ccRegfileReads++;
1386 return regFile.readCCReg(phys_reg);
1387}
1388
1389template <class Impl>
1390void

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1424 const VecPredRegContainer& val)
1425{
1426 vecPredRegfileWrites++;
1427 regFile.setVecPredReg(phys_reg, val);
1428}
1429
1430template <class Impl>
1431void
1383FullO3CPU<Impl>::readCCReg(PhysRegIdPtr phys_reg)
1384{
1385 ccRegfileReads++;
1386 return regFile.readCCReg(phys_reg);
1387}
1388
1389template <class Impl>
1390void

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1424 const VecPredRegContainer& val)
1425{
1426 vecPredRegfileWrites++;
1427 regFile.setVecPredReg(phys_reg, val);
1428}
1429
1430template <class Impl>
1431void
1432FullO3CPU<Impl>::setCCReg(PhysRegIdPtr phys_reg, CCReg val)
1432FullO3CPU<Impl>::setCCReg(PhysRegIdPtr phys_reg, RegVal val)
1433{
1434 ccRegfileWrites++;
1435 regFile.setCCReg(phys_reg, val);
1436}
1437
1438template <class Impl>
1439RegVal
1440FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)

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1503 -> VecPredRegContainer&
1504{
1505 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1506 RegId(VecPredRegClass, reg_idx));
1507 return getWritableVecPredReg(phys_reg);
1508}
1509
1510template <class Impl>
1433{
1434 ccRegfileWrites++;
1435 regFile.setCCReg(phys_reg, val);
1436}
1437
1438template <class Impl>
1439RegVal
1440FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)

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1503 -> VecPredRegContainer&
1504{
1505 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1506 RegId(VecPredRegClass, reg_idx));
1507 return getWritableVecPredReg(phys_reg);
1508}
1509
1510template <class Impl>
1511CCReg
1511RegVal
1512FullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid)
1513{
1514 ccRegfileReads++;
1515 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1516 RegId(CCRegClass, reg_idx));
1517
1518 return regFile.readCCReg(phys_reg);
1519}

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1567{
1568 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1569 RegId(VecPredRegClass, reg_idx));
1570 setVecPredReg(phys_reg, val);
1571}
1572
1573template <class Impl>
1574void
1512FullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid)
1513{
1514 ccRegfileReads++;
1515 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1516 RegId(CCRegClass, reg_idx));
1517
1518 return regFile.readCCReg(phys_reg);
1519}

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1567{
1568 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1569 RegId(VecPredRegClass, reg_idx));
1570 setVecPredReg(phys_reg, val);
1571}
1572
1573template <class Impl>
1574void
1575FullO3CPU<Impl>::setArchCCReg(int reg_idx, CCReg val, ThreadID tid)
1575FullO3CPU<Impl>::setArchCCReg(int reg_idx, RegVal val, ThreadID tid)
1576{
1577 ccRegfileWrites++;
1578 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1579 RegId(CCRegClass, reg_idx));
1580
1581 regFile.setCCReg(phys_reg, val);
1582}
1583

--- 305 unchanged lines hidden --- 		1576{
1577 ccRegfileWrites++;
1578 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1579 RegId(CCRegClass, reg_idx));
1580
1581 regFile.setCCReg(phys_reg, val);
1582}
1583

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