cpu.cc (13546:6cd6d7b19498) cpu.cc (13557:fc33e6048b25)
1/*
2 * Copyright (c) 2011-2012, 2014, 2016, 2017 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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1239{
1240 if (!system->isTimingMode()) {
1241 fatal("The O3 CPU requires the memory system to be in "
1242 "'timing' mode.\n");
1243 }
1244}
1245
1246template <class Impl>
1/*
2 * Copyright (c) 2011-2012, 2014, 2016, 2017 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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1239{
1240 if (!system->isTimingMode()) {
1241 fatal("The O3 CPU requires the memory system to be in "
1242 "'timing' mode.\n");
1243 }
1244}
1245
1246template <class Impl>
1247TheISA::MiscReg
1247RegVal
1248FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
1249{
1250 return this->isa[tid]->readMiscRegNoEffect(misc_reg);
1251}
1252
1253template <class Impl>
1248FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
1249{
1250 return this->isa[tid]->readMiscRegNoEffect(misc_reg);
1251}
1252
1253template <class Impl>
1254TheISA::MiscReg
1254RegVal
1255FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
1256{
1257 miscRegfileReads++;
1258 return this->isa[tid]->readMiscReg(misc_reg, tcBase(tid));
1259}
1260
1261template <class Impl>
1262void
1263FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
1255FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
1256{
1257 miscRegfileReads++;
1258 return this->isa[tid]->readMiscReg(misc_reg, tcBase(tid));
1259}
1260
1261template <class Impl>
1262void
1263FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
1264 const TheISA::MiscReg &val, ThreadID tid)
1264 const RegVal &val, ThreadID tid)
1265{
1266 this->isa[tid]->setMiscRegNoEffect(misc_reg, val);
1267}
1268
1269template <class Impl>
1270void
1271FullO3CPU<Impl>::setMiscReg(int misc_reg,
1265{
1266 this->isa[tid]->setMiscRegNoEffect(misc_reg, val);
1267}
1268
1269template <class Impl>
1270void
1271FullO3CPU<Impl>::setMiscReg(int misc_reg,
1272 const TheISA::MiscReg &val, ThreadID tid)
1272 const RegVal &val, ThreadID tid)
1273{
1274 miscRegfileWrites++;
1275 this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid));
1276}
1277
1278template <class Impl>
1273{
1274 miscRegfileWrites++;
1275 this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid));
1276}
1277
1278template <class Impl>
1279uint64_t
1279RegVal
1280FullO3CPU<Impl>::readIntReg(PhysRegIdPtr phys_reg)
1281{
1282 intRegfileReads++;
1283 return regFile.readIntReg(phys_reg);
1284}
1285
1286template <class Impl>
1280FullO3CPU<Impl>::readIntReg(PhysRegIdPtr phys_reg)
1281{
1282 intRegfileReads++;
1283 return regFile.readIntReg(phys_reg);
1284}
1285
1286template <class Impl>
1287FloatRegBits
1287RegVal
1288FullO3CPU<Impl>::readFloatRegBits(PhysRegIdPtr phys_reg)
1289{
1290 fpRegfileReads++;
1291 return regFile.readFloatRegBits(phys_reg);
1292}
1293
1294template <class Impl>
1295auto

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1322FullO3CPU<Impl>::readCCReg(PhysRegIdPtr phys_reg)
1323{
1324 ccRegfileReads++;
1325 return regFile.readCCReg(phys_reg);
1326}
1327
1328template <class Impl>
1329void
1288FullO3CPU<Impl>::readFloatRegBits(PhysRegIdPtr phys_reg)
1289{
1290 fpRegfileReads++;
1291 return regFile.readFloatRegBits(phys_reg);
1292}
1293
1294template <class Impl>
1295auto

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1322FullO3CPU<Impl>::readCCReg(PhysRegIdPtr phys_reg)
1323{
1324 ccRegfileReads++;
1325 return regFile.readCCReg(phys_reg);
1326}
1327
1328template <class Impl>
1329void
1330FullO3CPU<Impl>::setIntReg(PhysRegIdPtr phys_reg, uint64_t val)
1330FullO3CPU<Impl>::setIntReg(PhysRegIdPtr phys_reg, RegVal val)
1331{
1332 intRegfileWrites++;
1333 regFile.setIntReg(phys_reg, val);
1334}
1335
1336template <class Impl>
1337void
1331{
1332 intRegfileWrites++;
1333 regFile.setIntReg(phys_reg, val);
1334}
1335
1336template <class Impl>
1337void
1338FullO3CPU<Impl>::setFloatRegBits(PhysRegIdPtr phys_reg, FloatRegBits val)
1338FullO3CPU<Impl>::setFloatRegBits(PhysRegIdPtr phys_reg, RegVal val)
1339{
1340 fpRegfileWrites++;
1341 regFile.setFloatRegBits(phys_reg, val);
1342}
1343
1344template <class Impl>
1345void
1346FullO3CPU<Impl>::setVecReg(PhysRegIdPtr phys_reg, const VecRegContainer& val)

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1361void
1362FullO3CPU<Impl>::setCCReg(PhysRegIdPtr phys_reg, CCReg val)
1363{
1364 ccRegfileWrites++;
1365 regFile.setCCReg(phys_reg, val);
1366}
1367
1368template <class Impl>
1339{
1340 fpRegfileWrites++;
1341 regFile.setFloatRegBits(phys_reg, val);
1342}
1343
1344template <class Impl>
1345void
1346FullO3CPU<Impl>::setVecReg(PhysRegIdPtr phys_reg, const VecRegContainer& val)

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1361void
1362FullO3CPU<Impl>::setCCReg(PhysRegIdPtr phys_reg, CCReg val)
1363{
1364 ccRegfileWrites++;
1365 regFile.setCCReg(phys_reg, val);
1366}
1367
1368template <class Impl>
1369uint64_t
1369RegVal
1370FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1371{
1372 intRegfileReads++;
1373 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1374 RegId(IntRegClass, reg_idx));
1375
1376 return regFile.readIntReg(phys_reg);
1377}
1378
1379template <class Impl>
1370FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1371{
1372 intRegfileReads++;
1373 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1374 RegId(IntRegClass, reg_idx));
1375
1376 return regFile.readIntReg(phys_reg);
1377}
1378
1379template <class Impl>
1380uint64_t
1380RegVal
1381FullO3CPU<Impl>::readArchFloatRegBits(int reg_idx, ThreadID tid)
1382{
1383 fpRegfileReads++;
1384 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1385 RegId(FloatRegClass, reg_idx));
1386
1387 return regFile.readFloatRegBits(phys_reg);
1388}

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1425 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1426 RegId(CCRegClass, reg_idx));
1427
1428 return regFile.readCCReg(phys_reg);
1429}
1430
1431template <class Impl>
1432void
1381FullO3CPU<Impl>::readArchFloatRegBits(int reg_idx, ThreadID tid)
1382{
1383 fpRegfileReads++;
1384 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1385 RegId(FloatRegClass, reg_idx));
1386
1387 return regFile.readFloatRegBits(phys_reg);
1388}

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1425 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1426 RegId(CCRegClass, reg_idx));
1427
1428 return regFile.readCCReg(phys_reg);
1429}
1430
1431template <class Impl>
1432void
1433FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
1433FullO3CPU<Impl>::setArchIntReg(int reg_idx, RegVal val, ThreadID tid)
1434{
1435 intRegfileWrites++;
1436 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1437 RegId(IntRegClass, reg_idx));
1438
1439 regFile.setIntReg(phys_reg, val);
1440}
1441
1442template <class Impl>
1443void
1434{
1435 intRegfileWrites++;
1436 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1437 RegId(IntRegClass, reg_idx));
1438
1439 regFile.setIntReg(phys_reg, val);
1440}
1441
1442template <class Impl>
1443void
1444FullO3CPU<Impl>::setArchFloatRegBits(int reg_idx, uint64_t val, ThreadID tid)
1444FullO3CPU<Impl>::setArchFloatRegBits(int reg_idx, RegVal val, ThreadID tid)
1445{
1446 fpRegfileWrites++;
1447 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1448 RegId(FloatRegClass, reg_idx));
1449
1450 regFile.setFloatRegBits(phys_reg, val);
1451}
1452

--- 336 unchanged lines hidden --- 		1445{
1446 fpRegfileWrites++;
1447 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1448 RegId(FloatRegClass, reg_idx));
1449
1450 regFile.setFloatRegBits(phys_reg, val);
1451}
1452

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