cpu.cc (13500:6e0a2a7c6d8c) cpu.cc (13546:6cd6d7b19498)
1/*
2 * Copyright (c) 2011-2012, 2014, 2016, 2017 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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1461}
1462
1463template <class Impl>
1464void
1465FullO3CPU<Impl>::setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
1466 const VecElem& val, ThreadID tid)
1467{
1468 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1/*
2 * Copyright (c) 2011-2012, 2014, 2016, 2017 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 1452 unchanged lines hidden (view full) ---

1461}
1462
1463template <class Impl>
1464void
1465FullO3CPU<Impl>::setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
1466 const VecElem& val, ThreadID tid)
1467{
1468 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1469 RegId(VecRegClass, reg_idx, ldx));
1469 RegId(VecElemClass, reg_idx, ldx));
1470 setVecElem(phys_reg, val);
1471}
1472
1473template <class Impl>
1474void
1475FullO3CPU<Impl>::setArchCCReg(int reg_idx, CCReg val, ThreadID tid)
1476{
1477 ccRegfileWrites++;

--- 311 unchanged lines hidden --- 		1470 setVecElem(phys_reg, val);
1471}
1472
1473template <class Impl>
1474void
1475FullO3CPU<Impl>::setArchCCReg(int reg_idx, CCReg val, ThreadID tid)
1476{
1477 ccRegfileWrites++;

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