cpu.cc (12284:b91c036913da) cpu.cc (13429:a1e199fd8122)
1/*
2 * Copyright (c) 2011-2012, 2014, 2016, 2017 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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1559FullO3CPU<Impl>::squashFromTC(ThreadID tid)
1560{
1561 this->thread[tid]->noSquashFromTC = true;
1562 this->commit.generateTCEvent(tid);
1563}
1564
1565template <class Impl>
1566typename FullO3CPU<Impl>::ListIt
1/*
2 * Copyright (c) 2011-2012, 2014, 2016, 2017 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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1559FullO3CPU<Impl>::squashFromTC(ThreadID tid)
1560{
1561 this->thread[tid]->noSquashFromTC = true;
1562 this->commit.generateTCEvent(tid);
1563}
1564
1565template <class Impl>
1566typename FullO3CPU<Impl>::ListIt
1567FullO3CPU::addInst(DynInstPtr &inst)
1567FullO3CPU<Impl>::addInst(const DynInstPtr &inst)
1568{
1569 instList.push_back(inst);
1570
1571 return --(instList.end());
1572}
1573
1574template <class Impl>
1575void
1568{
1569 instList.push_back(inst);
1570
1571 return --(instList.end());
1572}
1573
1574template <class Impl>
1575void
1576FullO3CPU::instDone(ThreadID tid, DynInstPtr &inst)
1576FullO3CPU<Impl>::instDone(ThreadID tid, const DynInstPtr &inst)
1577{
1578 // Keep an instruction count.
1579 if (!inst->isMicroop() || inst->isLastMicroop()) {
1580 thread[tid]->numInst++;
1581 thread[tid]->numInsts++;
1582 committedInsts[tid]++;
1583 system->totalNumInsts++;
1584

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1590 thread[tid]->numOps++;
1591 committedOps[tid]++;
1592
1593 probeInstCommit(inst->staticInst);
1594}
1595
1596template <class Impl>
1597void
1577{
1578 // Keep an instruction count.
1579 if (!inst->isMicroop() || inst->isLastMicroop()) {
1580 thread[tid]->numInst++;
1581 thread[tid]->numInsts++;
1582 committedInsts[tid]++;
1583 system->totalNumInsts++;
1584

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1590 thread[tid]->numOps++;
1591 committedOps[tid]++;
1592
1593 probeInstCommit(inst->staticInst);
1594}
1595
1596template <class Impl>
1597void
1598FullO3CPU::removeFrontInst(DynInstPtr &inst)
1598FullO3CPU<Impl>::removeFrontInst(const DynInstPtr &inst)
1599{
1600 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s "
1601 "[sn:%lli]\n",
1602 inst->threadNumber, inst->pcState(), inst->seqNum);
1603
1604 removeInstsThisCycle = true;
1605
1606 // Remove the front instruction.

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1746 (*inst_list_it)->isSquashed());
1747 inst_list_it++;
1748 ++num;
1749 }
1750}
1751/*
1752template <class Impl>
1753void
1599{
1600 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s "
1601 "[sn:%lli]\n",
1602 inst->threadNumber, inst->pcState(), inst->seqNum);
1603
1604 removeInstsThisCycle = true;
1605
1606 // Remove the front instruction.

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1746 (*inst_list_it)->isSquashed());
1747 inst_list_it++;
1748 ++num;
1749 }
1750}
1751/*
1752template <class Impl>
1753void
1754FullO3CPU::wakeDependents(DynInstPtr &inst)
1754FullO3CPU<Impl>::wakeDependents(const DynInstPtr &inst)
1755{
1756 iew.wakeDependents(inst);
1757}
1758*/
1759template <class Impl>
1760void
1761FullO3CPU<Impl>::wakeCPU()
1762{

--- 64 unchanged lines hidden --- 		1755{
1756 iew.wakeDependents(inst);
1757}
1758*/
1759template <class Impl>
1760void
1761FullO3CPU<Impl>::wakeCPU()
1762{

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