cpu.cc (12106:7784fac1b159) cpu.cc (12109:f29e9c5418aa)
1/*
1/*
2 * Copyright (c) 2011-2012, 2014 ARM Limited
2 * Copyright (c) 2011-2012, 2014, 2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license

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41 *
42 * Authors: Kevin Lim
43 * Korey Sewell
44 * Rick Strong
45 */
46
47#include "cpu/o3/cpu.hh"
48
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license

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41 *
42 * Authors: Kevin Lim
43 * Korey Sewell
44 * Rick Strong
45 */
46
47#include "cpu/o3/cpu.hh"
48
49#include "arch/generic/traits.hh"
49#include "arch/kernel_stats.hh"
50#include "config/the_isa.hh"
51#include "cpu/activity.hh"
52#include "cpu/checker/cpu.hh"
53#include "cpu/checker/thread_context.hh"
54#include "cpu/o3/isa_specific.hh"
55#include "cpu/o3/thread_context.hh"
56#include "cpu/quiesce_event.hh"

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166#endif
167 removeInstsThisCycle(false),
168 fetch(this, params),
169 decode(this, params),
170 rename(this, params),
171 iew(this, params),
172 commit(this, params),
173
50#include "arch/kernel_stats.hh"
51#include "config/the_isa.hh"
52#include "cpu/activity.hh"
53#include "cpu/checker/cpu.hh"
54#include "cpu/checker/thread_context.hh"
55#include "cpu/o3/isa_specific.hh"
56#include "cpu/o3/thread_context.hh"
57#include "cpu/quiesce_event.hh"

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167#endif
168 removeInstsThisCycle(false),
169 fetch(this, params),
170 decode(this, params),
171 rename(this, params),
172 iew(this, params),
173 commit(this, params),
174
175 /* It is mandatory that all SMT threads use the same renaming mode as
176 * they are sharing registers and rename */
177 vecMode(initRenameMode<TheISA::ISA>::mode(params->isa[0])),
174 regFile(params->numPhysIntRegs,
175 params->numPhysFloatRegs,
178 regFile(params->numPhysIntRegs,
179 params->numPhysFloatRegs,
176 params->numPhysCCRegs),
180 params->numPhysVecRegs,
181 params->numPhysCCRegs,
182 vecMode),
177
178 freeList(name() + ".freelist", &regFile),
179
180 rob(this, params),
181
182 scoreboard(name() + ".scoreboard",
183 regFile.totalNumPhysRegs()),
184

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265 "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) "
266 "or edit your workload size.");
267 }
268 }
269
270 //Make Sure That this a Valid Architeture
271 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs);
272 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
183
184 freeList(name() + ".freelist", &regFile),
185
186 rob(this, params),
187
188 scoreboard(name() + ".scoreboard",
189 regFile.totalNumPhysRegs()),
190

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271 "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) "
272 "or edit your workload size.");
273 }
274 }
275
276 //Make Sure That this a Valid Architeture
277 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs);
278 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
279 assert(params->numPhysVecRegs >= numThreads * TheISA::NumVecRegs);
273 assert(params->numPhysCCRegs >= numThreads * TheISA::NumCCRegs);
274
275 rename.setScoreboard(&scoreboard);
276 iew.setScoreboard(&scoreboard);
277
278 // Setup the rename map for whichever stages need it.
279 for (ThreadID tid = 0; tid < numThreads; tid++) {
280 isa[tid] = params->isa[tid];
280 assert(params->numPhysCCRegs >= numThreads * TheISA::NumCCRegs);
281
282 rename.setScoreboard(&scoreboard);
283 iew.setScoreboard(&scoreboard);
284
285 // Setup the rename map for whichever stages need it.
286 for (ThreadID tid = 0; tid < numThreads; tid++) {
287 isa[tid] = params->isa[tid];
288 assert(initRenameMode<TheISA::ISA>::equals(isa[tid], isa[0]));
281
282 // Only Alpha has an FP zero register, so for other ISAs we
283 // use an invalid FP register index to avoid special treatment
284 // of any valid FP reg.
285 RegIndex invalidFPReg = TheISA::NumFloatRegs + 1;
286 RegIndex fpZeroReg =
287 (THE_ISA == ALPHA_ISA) ? TheISA::ZeroReg : invalidFPReg;
288
289 commitRenameMap[tid].init(&regFile, TheISA::ZeroReg, fpZeroReg,
289
290 // Only Alpha has an FP zero register, so for other ISAs we
291 // use an invalid FP register index to avoid special treatment
292 // of any valid FP reg.
293 RegIndex invalidFPReg = TheISA::NumFloatRegs + 1;
294 RegIndex fpZeroReg =
295 (THE_ISA == ALPHA_ISA) ? TheISA::ZeroReg : invalidFPReg;
296
297 commitRenameMap[tid].init(&regFile, TheISA::ZeroReg, fpZeroReg,
290 &freeList);
298 &freeList,
299 vecMode);
291
292 renameMap[tid].init(&regFile, TheISA::ZeroReg, fpZeroReg,
300
301 renameMap[tid].init(&regFile, TheISA::ZeroReg, fpZeroReg,
293 &freeList);
302 &freeList, vecMode);
294 }
295
296 // Initialize rename map to assign physical registers to the
297 // architectural registers for active threads only.
298 for (ThreadID tid = 0; tid < active_threads; tid++) {
299 for (RegIndex ridx = 0; ridx < TheISA::NumIntRegs; ++ridx) {
300 // Note that we can't use the rename() method because we don't
301 // want special treatment for the zero register at this point

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306
307 for (RegIndex ridx = 0; ridx < TheISA::NumFloatRegs; ++ridx) {
308 PhysRegIdPtr phys_reg = freeList.getFloatReg();
309 renameMap[tid].setEntry(RegId(FloatRegClass, ridx), phys_reg);
310 commitRenameMap[tid].setEntry(
311 RegId(FloatRegClass, ridx), phys_reg);
312 }
313
303 }
304
305 // Initialize rename map to assign physical registers to the
306 // architectural registers for active threads only.
307 for (ThreadID tid = 0; tid < active_threads; tid++) {
308 for (RegIndex ridx = 0; ridx < TheISA::NumIntRegs; ++ridx) {
309 // Note that we can't use the rename() method because we don't
310 // want special treatment for the zero register at this point

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315
316 for (RegIndex ridx = 0; ridx < TheISA::NumFloatRegs; ++ridx) {
317 PhysRegIdPtr phys_reg = freeList.getFloatReg();
318 renameMap[tid].setEntry(RegId(FloatRegClass, ridx), phys_reg);
319 commitRenameMap[tid].setEntry(
320 RegId(FloatRegClass, ridx), phys_reg);
321 }
322
323 /* Here we need two 'interfaces' the 'whole register' and the
324 * 'register element'. At any point only one of them will be
325 * active. */
326 if (vecMode == Enums::Full) {
327 /* Initialize the full-vector interface */
328 for (RegIndex ridx = 0; ridx < TheISA::NumVecRegs; ++ridx) {
329 RegId rid = RegId(VecRegClass, ridx);
330 PhysRegIdPtr phys_reg = freeList.getVecReg();
331 renameMap[tid].setEntry(rid, phys_reg);
332 commitRenameMap[tid].setEntry(rid, phys_reg);
333 }
334 } else {
335 /* Initialize the vector-element interface */
336 for (RegIndex ridx = 0; ridx < TheISA::NumVecRegs; ++ridx) {
337 for (ElemIndex ldx = 0; ldx < TheISA::NumVecElemPerVecReg;
338 ++ldx) {
339 RegId lrid = RegId(VecElemClass, ridx, ldx);
340 PhysRegIdPtr phys_elem = freeList.getVecElem();
341 renameMap[tid].setEntry(lrid, phys_elem);
342 commitRenameMap[tid].setEntry(lrid, phys_elem);
343 }
344 }
345 }
346
314 for (RegIndex ridx = 0; ridx < TheISA::NumCCRegs; ++ridx) {
315 PhysRegIdPtr phys_reg = freeList.getCCReg();
316 renameMap[tid].setEntry(RegId(CCRegClass, ridx), phys_reg);
317 commitRenameMap[tid].setEntry(RegId(CCRegClass, ridx), phys_reg);
318 }
319 }
320
321 rename.setRenameMap(renameMap);

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509 .desc("number of floating regfile reads")
510 .prereq(fpRegfileReads);
511
512 fpRegfileWrites
513 .name(name() + ".fp_regfile_writes")
514 .desc("number of floating regfile writes")
515 .prereq(fpRegfileWrites);
516
347 for (RegIndex ridx = 0; ridx < TheISA::NumCCRegs; ++ridx) {
348 PhysRegIdPtr phys_reg = freeList.getCCReg();
349 renameMap[tid].setEntry(RegId(CCRegClass, ridx), phys_reg);
350 commitRenameMap[tid].setEntry(RegId(CCRegClass, ridx), phys_reg);
351 }
352 }
353
354 rename.setRenameMap(renameMap);

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542 .desc("number of floating regfile reads")
543 .prereq(fpRegfileReads);
544
545 fpRegfileWrites
546 .name(name() + ".fp_regfile_writes")
547 .desc("number of floating regfile writes")
548 .prereq(fpRegfileWrites);
549
550 vecRegfileReads
551 .name(name() + ".vec_regfile_reads")
552 .desc("number of vector regfile reads")
553 .prereq(vecRegfileReads);
554
555 vecRegfileWrites
556 .name(name() + ".vec_regfile_writes")
557 .desc("number of vector regfile writes")
558 .prereq(vecRegfileWrites);
559
517 ccRegfileReads
518 .name(name() + ".cc_regfile_reads")
519 .desc("number of cc regfile reads")
520 .prereq(ccRegfileReads);
521
522 ccRegfileWrites
523 .name(name() + ".cc_regfile_writes")
524 .desc("number of cc regfile writes")

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1252FloatRegBits
1253FullO3CPU<Impl>::readFloatRegBits(PhysRegIdPtr phys_reg)
1254{
1255 fpRegfileReads++;
1256 return regFile.readFloatRegBits(phys_reg);
1257}
1258
1259template <class Impl>
560 ccRegfileReads
561 .name(name() + ".cc_regfile_reads")
562 .desc("number of cc regfile reads")
563 .prereq(ccRegfileReads);
564
565 ccRegfileWrites
566 .name(name() + ".cc_regfile_writes")
567 .desc("number of cc regfile writes")

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1295FloatRegBits
1296FullO3CPU<Impl>::readFloatRegBits(PhysRegIdPtr phys_reg)
1297{
1298 fpRegfileReads++;
1299 return regFile.readFloatRegBits(phys_reg);
1300}
1301
1302template <class Impl>
1303auto
1304FullO3CPU<Impl>::readVecReg(PhysRegIdPtr phys_reg) const
1305 -> const VecRegContainer&
1306{
1307 vecRegfileReads++;
1308 return regFile.readVecReg(phys_reg);
1309}
1310
1311template <class Impl>
1312auto
1313FullO3CPU<Impl>::getWritableVecReg(PhysRegIdPtr phys_reg)
1314 -> VecRegContainer&
1315{
1316 vecRegfileWrites++;
1317 return regFile.getWritableVecReg(phys_reg);
1318}
1319
1320template <class Impl>
1321auto
1322FullO3CPU<Impl>::readVecElem(PhysRegIdPtr phys_reg) const -> const VecElem&
1323{
1324 vecRegfileReads++;
1325 return regFile.readVecElem(phys_reg);
1326}
1327
1328template <class Impl>
1260CCReg
1261FullO3CPU<Impl>::readCCReg(PhysRegIdPtr phys_reg)
1262{
1263 ccRegfileReads++;
1264 return regFile.readCCReg(phys_reg);
1265}
1266
1267template <class Impl>

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1285FullO3CPU<Impl>::setFloatRegBits(PhysRegIdPtr phys_reg, FloatRegBits val)
1286{
1287 fpRegfileWrites++;
1288 regFile.setFloatRegBits(phys_reg, val);
1289}
1290
1291template <class Impl>
1292void
1329CCReg
1330FullO3CPU<Impl>::readCCReg(PhysRegIdPtr phys_reg)
1331{
1332 ccRegfileReads++;
1333 return regFile.readCCReg(phys_reg);
1334}
1335
1336template <class Impl>

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1354FullO3CPU<Impl>::setFloatRegBits(PhysRegIdPtr phys_reg, FloatRegBits val)
1355{
1356 fpRegfileWrites++;
1357 regFile.setFloatRegBits(phys_reg, val);
1358}
1359
1360template <class Impl>
1361void
1362FullO3CPU<Impl>::setVecReg(PhysRegIdPtr phys_reg, const VecRegContainer& val)
1363{
1364 vecRegfileWrites++;
1365 regFile.setVecReg(phys_reg, val);
1366}
1367
1368template <class Impl>
1369void
1370FullO3CPU<Impl>::setVecElem(PhysRegIdPtr phys_reg, const VecElem& val)
1371{
1372 vecRegfileWrites++;
1373 regFile.setVecElem(phys_reg, val);
1374}
1375
1376template <class Impl>
1377void
1293FullO3CPU<Impl>::setCCReg(PhysRegIdPtr phys_reg, CCReg val)
1294{
1295 ccRegfileWrites++;
1296 regFile.setCCReg(phys_reg, val);
1297}
1298
1299template <class Impl>
1300uint64_t

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1325 fpRegfileReads++;
1326 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1327 RegId(FloatRegClass, reg_idx));
1328
1329 return regFile.readFloatRegBits(phys_reg);
1330}
1331
1332template <class Impl>
1378FullO3CPU<Impl>::setCCReg(PhysRegIdPtr phys_reg, CCReg val)
1379{
1380 ccRegfileWrites++;
1381 regFile.setCCReg(phys_reg, val);
1382}
1383
1384template <class Impl>
1385uint64_t

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1410 fpRegfileReads++;
1411 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1412 RegId(FloatRegClass, reg_idx));
1413
1414 return regFile.readFloatRegBits(phys_reg);
1415}
1416
1417template <class Impl>
1418auto
1419FullO3CPU<Impl>::readArchVecReg(int reg_idx, ThreadID tid) const
1420 -> const VecRegContainer&
1421{
1422 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1423 RegId(VecRegClass, reg_idx));
1424 return readVecReg(phys_reg);
1425}
1426
1427template <class Impl>
1428auto
1429FullO3CPU<Impl>::getWritableArchVecReg(int reg_idx, ThreadID tid)
1430 -> VecRegContainer&
1431{
1432 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1433 RegId(VecRegClass, reg_idx));
1434 return getWritableVecReg(phys_reg);
1435}
1436
1437template <class Impl>
1438auto
1439FullO3CPU<Impl>::readArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
1440 ThreadID tid) const -> const VecElem&
1441{
1442 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1443 RegId(VecRegClass, reg_idx, ldx));
1444 return readVecElem(phys_reg);
1445}
1446
1447template <class Impl>
1333CCReg
1334FullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid)
1335{
1336 ccRegfileReads++;
1337 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1338 RegId(CCRegClass, reg_idx));
1339
1340 return regFile.readCCReg(phys_reg);

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1370 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1371 RegId(FloatRegClass, reg_idx));
1372
1373 regFile.setFloatRegBits(phys_reg, val);
1374}
1375
1376template <class Impl>
1377void
1448CCReg
1449FullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid)
1450{
1451 ccRegfileReads++;
1452 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1453 RegId(CCRegClass, reg_idx));
1454
1455 return regFile.readCCReg(phys_reg);

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1485 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1486 RegId(FloatRegClass, reg_idx));
1487
1488 regFile.setFloatRegBits(phys_reg, val);
1489}
1490
1491template <class Impl>
1492void
1493FullO3CPU<Impl>::setArchVecReg(int reg_idx, const VecRegContainer& val,
1494 ThreadID tid)
1495{
1496 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1497 RegId(VecRegClass, reg_idx));
1498 setVecReg(phys_reg, val);
1499}
1500
1501template <class Impl>
1502void
1503FullO3CPU<Impl>::setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
1504 const VecElem& val, ThreadID tid)
1505{
1506 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1507 RegId(VecRegClass, reg_idx, ldx));
1508 setVecElem(phys_reg, val);
1509}
1510
1511template <class Impl>
1512void
1378FullO3CPU<Impl>::setArchCCReg(int reg_idx, CCReg val, ThreadID tid)
1379{
1380 ccRegfileWrites++;
1381 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1382 RegId(CCRegClass, reg_idx));
1383
1384 regFile.setCCReg(phys_reg, val);
1385}

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1514{
1515 ccRegfileWrites++;
1516 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1517 RegId(CCRegClass, reg_idx));
1518
1519 regFile.setCCReg(phys_reg, val);
1520}

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