cpu.cc (12105:742d80361989) cpu.cc (12106:7784fac1b159)
1/*
2 * Copyright (c) 2011-2012, 2014 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 286 unchanged lines hidden (view full) ---

295
296 // Initialize rename map to assign physical registers to the
297 // architectural registers for active threads only.
298 for (ThreadID tid = 0; tid < active_threads; tid++) {
299 for (RegIndex ridx = 0; ridx < TheISA::NumIntRegs; ++ridx) {
300 // Note that we can't use the rename() method because we don't
301 // want special treatment for the zero register at this point
302 PhysRegIdPtr phys_reg = freeList.getIntReg();
1/*
2 * Copyright (c) 2011-2012, 2014 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 286 unchanged lines hidden (view full) ---

295
296 // Initialize rename map to assign physical registers to the
297 // architectural registers for active threads only.
298 for (ThreadID tid = 0; tid < active_threads; tid++) {
299 for (RegIndex ridx = 0; ridx < TheISA::NumIntRegs; ++ridx) {
300 // Note that we can't use the rename() method because we don't
301 // want special treatment for the zero register at this point
302 PhysRegIdPtr phys_reg = freeList.getIntReg();
303 renameMap[tid].setIntEntry(ridx, phys_reg);
304 commitRenameMap[tid].setIntEntry(ridx, phys_reg);
303 renameMap[tid].setEntry(RegId(IntRegClass, ridx), phys_reg);
304 commitRenameMap[tid].setEntry(RegId(IntRegClass, ridx), phys_reg);
305 }
306
307 for (RegIndex ridx = 0; ridx < TheISA::NumFloatRegs; ++ridx) {
308 PhysRegIdPtr phys_reg = freeList.getFloatReg();
305 }
306
307 for (RegIndex ridx = 0; ridx < TheISA::NumFloatRegs; ++ridx) {
308 PhysRegIdPtr phys_reg = freeList.getFloatReg();
309 renameMap[tid].setFloatEntry(ridx, phys_reg);
310 commitRenameMap[tid].setFloatEntry(ridx, phys_reg);
309 renameMap[tid].setEntry(RegId(FloatRegClass, ridx), phys_reg);
310 commitRenameMap[tid].setEntry(
311 RegId(FloatRegClass, ridx), phys_reg);
311 }
312
313 for (RegIndex ridx = 0; ridx < TheISA::NumCCRegs; ++ridx) {
314 PhysRegIdPtr phys_reg = freeList.getCCReg();
312 }
313
314 for (RegIndex ridx = 0; ridx < TheISA::NumCCRegs; ++ridx) {
315 PhysRegIdPtr phys_reg = freeList.getCCReg();
315 renameMap[tid].setCCEntry(ridx, phys_reg);
316 commitRenameMap[tid].setCCEntry(ridx, phys_reg);
316 renameMap[tid].setEntry(RegId(CCRegClass, ridx), phys_reg);
317 commitRenameMap[tid].setEntry(RegId(CCRegClass, ridx), phys_reg);
317 }
318 }
319
320 rename.setRenameMap(renameMap);
321 commit.setRenameMap(commitRenameMap);
322 rename.setFreeList(&freeList);
323
324 // Setup the ROB for whichever stages need it.

--- 458 unchanged lines hidden (view full) ---

783 ThreadContext *src_tc;
784 if (FullSystem)
785 src_tc = system->threadContexts[tid];
786 else
787 src_tc = tcBase(tid);
788
789 //Bind Int Regs to Rename Map
790
318 }
319 }
320
321 rename.setRenameMap(renameMap);
322 commit.setRenameMap(commitRenameMap);
323 rename.setFreeList(&freeList);
324
325 // Setup the ROB for whichever stages need it.

--- 458 unchanged lines hidden (view full) ---

784 ThreadContext *src_tc;
785 if (FullSystem)
786 src_tc = system->threadContexts[tid];
787 else
788 src_tc = tcBase(tid);
789
790 //Bind Int Regs to Rename Map
791
791 for (RegId reg_id(IntRegClass, 0); reg_id.regIdx < TheISA::NumIntRegs;
792 reg_id.regIdx++) {
792 for (RegId reg_id(IntRegClass, 0); reg_id.index() < TheISA::NumIntRegs;
793 reg_id.index()++) {
793 PhysRegIdPtr phys_reg = freeList.getIntReg();
794 renameMap[tid].setEntry(reg_id, phys_reg);
795 scoreboard.setReg(phys_reg);
796 }
797
798 //Bind Float Regs to Rename Map
794 PhysRegIdPtr phys_reg = freeList.getIntReg();
795 renameMap[tid].setEntry(reg_id, phys_reg);
796 scoreboard.setReg(phys_reg);
797 }
798
799 //Bind Float Regs to Rename Map
799 for (RegId reg_id(FloatRegClass, 0); reg_id.regIdx < TheISA::NumFloatRegs;
800 reg_id.regIdx++) {
800 for (RegId reg_id(FloatRegClass, 0); reg_id.index() < TheISA::NumFloatRegs;
801 reg_id.index()++) {
801 PhysRegIdPtr phys_reg = freeList.getFloatReg();
802 renameMap[tid].setEntry(reg_id, phys_reg);
803 scoreboard.setReg(phys_reg);
804 }
805
806 //Bind condition-code Regs to Rename Map
802 PhysRegIdPtr phys_reg = freeList.getFloatReg();
803 renameMap[tid].setEntry(reg_id, phys_reg);
804 scoreboard.setReg(phys_reg);
805 }
806
807 //Bind condition-code Regs to Rename Map
807 for (RegId reg_id(CCRegClass, 0); reg_id.regIdx < TheISA::NumCCRegs;
808 reg_id.regIdx++) {
808 for (RegId reg_id(CCRegClass, 0); reg_id.index() < TheISA::NumCCRegs;
809 reg_id.index()++) {
809 PhysRegIdPtr phys_reg = freeList.getCCReg();
810 renameMap[tid].setEntry(reg_id, phys_reg);
811 scoreboard.setReg(phys_reg);
812 }
813
814 //Copy Thread Data Into RegFile
815 //this->copyFromTC(tid);
816

--- 20 unchanged lines hidden (view full) ---

837 // this->copyToTC(tid);
838
839
840 // @todo: 2-27-2008: Fix how we free up rename mappings
841 // here to alleviate the case for double-freeing registers
842 // in SMT workloads.
843
844 // Unbind Int Regs from Rename Map
810 PhysRegIdPtr phys_reg = freeList.getCCReg();
811 renameMap[tid].setEntry(reg_id, phys_reg);
812 scoreboard.setReg(phys_reg);
813 }
814
815 //Copy Thread Data Into RegFile
816 //this->copyFromTC(tid);
817

--- 20 unchanged lines hidden (view full) ---

838 // this->copyToTC(tid);
839
840
841 // @todo: 2-27-2008: Fix how we free up rename mappings
842 // here to alleviate the case for double-freeing registers
843 // in SMT workloads.
844
845 // Unbind Int Regs from Rename Map
845 for (RegId reg_id(IntRegClass, 0); reg_id.regIdx < TheISA::NumIntRegs;
846 reg_id.regIdx++) {
846 for (RegId reg_id(IntRegClass, 0); reg_id.index() < TheISA::NumIntRegs;
847 reg_id.index()++) {
847 PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id);
848 scoreboard.unsetReg(phys_reg);
849 freeList.addReg(phys_reg);
850 }
851
852 // Unbind Float Regs from Rename Map
848 PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id);
849 scoreboard.unsetReg(phys_reg);
850 freeList.addReg(phys_reg);
851 }
852
853 // Unbind Float Regs from Rename Map
853 for (RegId reg_id(FloatRegClass, 0); reg_id.regIdx < TheISA::NumFloatRegs;
854 reg_id.regIdx++) {
854 for (RegId reg_id(FloatRegClass, 0); reg_id.index() < TheISA::NumFloatRegs;
855 reg_id.index()++) {
855 PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id);
856 scoreboard.unsetReg(phys_reg);
857 freeList.addReg(phys_reg);
858 }
859
860 // Unbind condition-code Regs from Rename Map
856 PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id);
857 scoreboard.unsetReg(phys_reg);
858 freeList.addReg(phys_reg);
859 }
860
861 // Unbind condition-code Regs from Rename Map
861 for (RegId reg_id(CCRegClass, 0); reg_id.regIdx < TheISA::NumCCRegs;
862 reg_id.regIdx++) {
862 for (RegId reg_id(CCRegClass, 0); reg_id.index() < TheISA::NumCCRegs;
863 reg_id.index()++) {
863 PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id);
864 scoreboard.unsetReg(phys_reg);
865 freeList.addReg(phys_reg);
866 }
867
868 // Squash Throughout Pipeline
869 DynInstPtr inst = commit.rob->readHeadInst(tid);
870 InstSeqNum squash_seq_num = inst->seqNum;

--- 424 unchanged lines hidden (view full) ---

1295 regFile.setCCReg(phys_reg, val);
1296}
1297
1298template <class Impl>
1299uint64_t
1300FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1301{
1302 intRegfileReads++;
864 PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id);
865 scoreboard.unsetReg(phys_reg);
866 freeList.addReg(phys_reg);
867 }
868
869 // Squash Throughout Pipeline
870 DynInstPtr inst = commit.rob->readHeadInst(tid);
871 InstSeqNum squash_seq_num = inst->seqNum;

--- 424 unchanged lines hidden (view full) ---

1296 regFile.setCCReg(phys_reg, val);
1297}
1298
1299template <class Impl>
1300uint64_t
1301FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1302{
1303 intRegfileReads++;
1303 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookupInt(reg_idx);
1304 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1305 RegId(IntRegClass, reg_idx));
1304
1305 return regFile.readIntReg(phys_reg);
1306}
1307
1308template <class Impl>
1309float
1310FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
1311{
1312 fpRegfileReads++;
1306
1307 return regFile.readIntReg(phys_reg);
1308}
1309
1310template <class Impl>
1311float
1312FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
1313{
1314 fpRegfileReads++;
1313 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1315 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1316 RegId(FloatRegClass, reg_idx));
1314
1315 return regFile.readFloatReg(phys_reg);
1316}
1317
1318template <class Impl>
1319uint64_t
1320FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid)
1321{
1322 fpRegfileReads++;
1317
1318 return regFile.readFloatReg(phys_reg);
1319}
1320
1321template <class Impl>
1322uint64_t
1323FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid)
1324{
1325 fpRegfileReads++;
1323 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1326 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1327 RegId(FloatRegClass, reg_idx));
1324
1325 return regFile.readFloatRegBits(phys_reg);
1326}
1327
1328template <class Impl>
1329CCReg
1330FullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid)
1331{
1332 ccRegfileReads++;
1328
1329 return regFile.readFloatRegBits(phys_reg);
1330}
1331
1332template <class Impl>
1333CCReg
1334FullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid)
1335{
1336 ccRegfileReads++;
1333 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookupCC(reg_idx);
1337 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1338 RegId(CCRegClass, reg_idx));
1334
1335 return regFile.readCCReg(phys_reg);
1336}
1337
1338template <class Impl>
1339void
1340FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
1341{
1342 intRegfileWrites++;
1339
1340 return regFile.readCCReg(phys_reg);
1341}
1342
1343template <class Impl>
1344void
1345FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
1346{
1347 intRegfileWrites++;
1343 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookupInt(reg_idx);
1348 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1349 RegId(IntRegClass, reg_idx));
1344
1345 regFile.setIntReg(phys_reg, val);
1346}
1347
1348template <class Impl>
1349void
1350FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid)
1351{
1352 fpRegfileWrites++;
1350
1351 regFile.setIntReg(phys_reg, val);
1352}
1353
1354template <class Impl>
1355void
1356FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid)
1357{
1358 fpRegfileWrites++;
1353 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1359 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1360 RegId(FloatRegClass, reg_idx));
1354
1355 regFile.setFloatReg(phys_reg, val);
1356}
1357
1358template <class Impl>
1359void
1360FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid)
1361{
1362 fpRegfileWrites++;
1361
1362 regFile.setFloatReg(phys_reg, val);
1363}
1364
1365template <class Impl>
1366void
1367FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid)
1368{
1369 fpRegfileWrites++;
1363 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1370 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1371 RegId(FloatRegClass, reg_idx));
1364
1365 regFile.setFloatRegBits(phys_reg, val);
1366}
1367
1368template <class Impl>
1369void
1370FullO3CPU<Impl>::setArchCCReg(int reg_idx, CCReg val, ThreadID tid)
1371{
1372 ccRegfileWrites++;
1372
1373 regFile.setFloatRegBits(phys_reg, val);
1374}
1375
1376template <class Impl>
1377void
1378FullO3CPU<Impl>::setArchCCReg(int reg_idx, CCReg val, ThreadID tid)
1379{
1380 ccRegfileWrites++;
1373 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookupCC(reg_idx);
1381 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1382 RegId(CCRegClass, reg_idx));
1374
1375 regFile.setCCReg(phys_reg, val);
1376}
1377
1378template <class Impl>
1379TheISA::PCState
1380FullO3CPU<Impl>::pcState(ThreadID tid)
1381{

--- 302 unchanged lines hidden --- 		1383
1384 regFile.setCCReg(phys_reg, val);
1385}
1386
1387template <class Impl>
1388TheISA::PCState
1389FullO3CPU<Impl>::pcState(ThreadID tid)
1390{

--- 302 unchanged lines hidden ---