cpu.cc (12104:edd63f9c6184) cpu.cc (12105:742d80361989)
1/*
2 * Copyright (c) 2011-2012, 2014 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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175 params->numPhysFloatRegs,
176 params->numPhysCCRegs),
177
178 freeList(name() + ".freelist", &regFile),
179
180 rob(this, params),
181
182 scoreboard(name() + ".scoreboard",
1/*
2 * Copyright (c) 2011-2012, 2014 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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175 params->numPhysFloatRegs,
176 params->numPhysCCRegs),
177
178 freeList(name() + ".freelist", &regFile),
179
180 rob(this, params),
181
182 scoreboard(name() + ".scoreboard",
183 regFile.totalNumPhysRegs(), TheISA::NumMiscRegs,
184 TheISA::ZeroReg, TheISA::ZeroReg),
183 regFile.totalNumPhysRegs()),
185
186 isa(numThreads, NULL),
187
188 icachePort(&fetch, this),
189 dcachePort(&iew.ldstQueue, this),
190
191 timeBuffer(params->backComSize, params->forwardComSize),
192 fetchQueue(params->backComSize, params->forwardComSize),

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295 }
296
297 // Initialize rename map to assign physical registers to the
298 // architectural registers for active threads only.
299 for (ThreadID tid = 0; tid < active_threads; tid++) {
300 for (RegIndex ridx = 0; ridx < TheISA::NumIntRegs; ++ridx) {
301 // Note that we can't use the rename() method because we don't
302 // want special treatment for the zero register at this point
184
185 isa(numThreads, NULL),
186
187 icachePort(&fetch, this),
188 dcachePort(&iew.ldstQueue, this),
189
190 timeBuffer(params->backComSize, params->forwardComSize),
191 fetchQueue(params->backComSize, params->forwardComSize),

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294 }
295
296 // Initialize rename map to assign physical registers to the
297 // architectural registers for active threads only.
298 for (ThreadID tid = 0; tid < active_threads; tid++) {
299 for (RegIndex ridx = 0; ridx < TheISA::NumIntRegs; ++ridx) {
300 // Note that we can't use the rename() method because we don't
301 // want special treatment for the zero register at this point
303 PhysRegIndex phys_reg = freeList.getIntReg();
302 PhysRegIdPtr phys_reg = freeList.getIntReg();
304 renameMap[tid].setIntEntry(ridx, phys_reg);
305 commitRenameMap[tid].setIntEntry(ridx, phys_reg);
306 }
307
308 for (RegIndex ridx = 0; ridx < TheISA::NumFloatRegs; ++ridx) {
303 renameMap[tid].setIntEntry(ridx, phys_reg);
304 commitRenameMap[tid].setIntEntry(ridx, phys_reg);
305 }
306
307 for (RegIndex ridx = 0; ridx < TheISA::NumFloatRegs; ++ridx) {
309 PhysRegIndex phys_reg = freeList.getFloatReg();
308 PhysRegIdPtr phys_reg = freeList.getFloatReg();
310 renameMap[tid].setFloatEntry(ridx, phys_reg);
311 commitRenameMap[tid].setFloatEntry(ridx, phys_reg);
312 }
313
314 for (RegIndex ridx = 0; ridx < TheISA::NumCCRegs; ++ridx) {
309 renameMap[tid].setFloatEntry(ridx, phys_reg);
310 commitRenameMap[tid].setFloatEntry(ridx, phys_reg);
311 }
312
313 for (RegIndex ridx = 0; ridx < TheISA::NumCCRegs; ++ridx) {
315 PhysRegIndex phys_reg = freeList.getCCReg();
314 PhysRegIdPtr phys_reg = freeList.getCCReg();
316 renameMap[tid].setCCEntry(ridx, phys_reg);
317 commitRenameMap[tid].setCCEntry(ridx, phys_reg);
318 }
319 }
320
321 rename.setRenameMap(renameMap);
322 commit.setRenameMap(commitRenameMap);
323 rename.setFreeList(&freeList);

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786 src_tc = system->threadContexts[tid];
787 else
788 src_tc = tcBase(tid);
789
790 //Bind Int Regs to Rename Map
791
792 for (RegId reg_id(IntRegClass, 0); reg_id.regIdx < TheISA::NumIntRegs;
793 reg_id.regIdx++) {
315 renameMap[tid].setCCEntry(ridx, phys_reg);
316 commitRenameMap[tid].setCCEntry(ridx, phys_reg);
317 }
318 }
319
320 rename.setRenameMap(renameMap);
321 commit.setRenameMap(commitRenameMap);
322 rename.setFreeList(&freeList);

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785 src_tc = system->threadContexts[tid];
786 else
787 src_tc = tcBase(tid);
788
789 //Bind Int Regs to Rename Map
790
791 for (RegId reg_id(IntRegClass, 0); reg_id.regIdx < TheISA::NumIntRegs;
792 reg_id.regIdx++) {
794 PhysRegIndex phys_reg = freeList.getIntReg();
793 PhysRegIdPtr phys_reg = freeList.getIntReg();
795 renameMap[tid].setEntry(reg_id, phys_reg);
796 scoreboard.setReg(phys_reg);
797 }
798
799 //Bind Float Regs to Rename Map
800 for (RegId reg_id(FloatRegClass, 0); reg_id.regIdx < TheISA::NumFloatRegs;
801 reg_id.regIdx++) {
794 renameMap[tid].setEntry(reg_id, phys_reg);
795 scoreboard.setReg(phys_reg);
796 }
797
798 //Bind Float Regs to Rename Map
799 for (RegId reg_id(FloatRegClass, 0); reg_id.regIdx < TheISA::NumFloatRegs;
800 reg_id.regIdx++) {
802 PhysRegIndex phys_reg = freeList.getFloatReg();
801 PhysRegIdPtr phys_reg = freeList.getFloatReg();
803 renameMap[tid].setEntry(reg_id, phys_reg);
804 scoreboard.setReg(phys_reg);
805 }
806
807 //Bind condition-code Regs to Rename Map
808 for (RegId reg_id(CCRegClass, 0); reg_id.regIdx < TheISA::NumCCRegs;
809 reg_id.regIdx++) {
802 renameMap[tid].setEntry(reg_id, phys_reg);
803 scoreboard.setReg(phys_reg);
804 }
805
806 //Bind condition-code Regs to Rename Map
807 for (RegId reg_id(CCRegClass, 0); reg_id.regIdx < TheISA::NumCCRegs;
808 reg_id.regIdx++) {
810 PhysRegIndex phys_reg = freeList.getCCReg();
809 PhysRegIdPtr phys_reg = freeList.getCCReg();
811 renameMap[tid].setEntry(reg_id, phys_reg);
812 scoreboard.setReg(phys_reg);
813 }
814
815 //Copy Thread Data Into RegFile
816 //this->copyFromTC(tid);
817
818 //Set PC/NPC/NNPC

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840
841 // @todo: 2-27-2008: Fix how we free up rename mappings
842 // here to alleviate the case for double-freeing registers
843 // in SMT workloads.
844
845 // Unbind Int Regs from Rename Map
846 for (RegId reg_id(IntRegClass, 0); reg_id.regIdx < TheISA::NumIntRegs;
847 reg_id.regIdx++) {
810 renameMap[tid].setEntry(reg_id, phys_reg);
811 scoreboard.setReg(phys_reg);
812 }
813
814 //Copy Thread Data Into RegFile
815 //this->copyFromTC(tid);
816
817 //Set PC/NPC/NNPC

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839
840 // @todo: 2-27-2008: Fix how we free up rename mappings
841 // here to alleviate the case for double-freeing registers
842 // in SMT workloads.
843
844 // Unbind Int Regs from Rename Map
845 for (RegId reg_id(IntRegClass, 0); reg_id.regIdx < TheISA::NumIntRegs;
846 reg_id.regIdx++) {
848 PhysRegIndex phys_reg = renameMap[tid].lookup(reg_id);
847 PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id);
849 scoreboard.unsetReg(phys_reg);
850 freeList.addReg(phys_reg);
851 }
852
853 // Unbind Float Regs from Rename Map
854 for (RegId reg_id(FloatRegClass, 0); reg_id.regIdx < TheISA::NumFloatRegs;
855 reg_id.regIdx++) {
848 scoreboard.unsetReg(phys_reg);
849 freeList.addReg(phys_reg);
850 }
851
852 // Unbind Float Regs from Rename Map
853 for (RegId reg_id(FloatRegClass, 0); reg_id.regIdx < TheISA::NumFloatRegs;
854 reg_id.regIdx++) {
856 PhysRegIndex phys_reg = renameMap[tid].lookup(reg_id);
855 PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id);
857 scoreboard.unsetReg(phys_reg);
858 freeList.addReg(phys_reg);
859 }
860
861 // Unbind condition-code Regs from Rename Map
862 for (RegId reg_id(CCRegClass, 0); reg_id.regIdx < TheISA::NumCCRegs;
863 reg_id.regIdx++) {
856 scoreboard.unsetReg(phys_reg);
857 freeList.addReg(phys_reg);
858 }
859
860 // Unbind condition-code Regs from Rename Map
861 for (RegId reg_id(CCRegClass, 0); reg_id.regIdx < TheISA::NumCCRegs;
862 reg_id.regIdx++) {
864 PhysRegIndex phys_reg = renameMap[tid].lookup(reg_id);
863 PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id);
865 scoreboard.unsetReg(phys_reg);
866 freeList.addReg(phys_reg);
867 }
868
869 // Squash Throughout Pipeline
870 DynInstPtr inst = commit.rob->readHeadInst(tid);
871 InstSeqNum squash_seq_num = inst->seqNum;
872 fetch.squash(0, squash_seq_num, inst, tid);

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1229 const TheISA::MiscReg &val, ThreadID tid)
1230{
1231 miscRegfileWrites++;
1232 this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid));
1233}
1234
1235template <class Impl>
1236uint64_t
864 scoreboard.unsetReg(phys_reg);
865 freeList.addReg(phys_reg);
866 }
867
868 // Squash Throughout Pipeline
869 DynInstPtr inst = commit.rob->readHeadInst(tid);
870 InstSeqNum squash_seq_num = inst->seqNum;
871 fetch.squash(0, squash_seq_num, inst, tid);

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1228 const TheISA::MiscReg &val, ThreadID tid)
1229{
1230 miscRegfileWrites++;
1231 this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid));
1232}
1233
1234template <class Impl>
1235uint64_t
1237FullO3CPU<Impl>::readIntReg(int reg_idx)
1236FullO3CPU<Impl>::readIntReg(PhysRegIdPtr phys_reg)
1238{
1239 intRegfileReads++;
1237{
1238 intRegfileReads++;
1240 return regFile.readIntReg(reg_idx);
1239 return regFile.readIntReg(phys_reg);
1241}
1242
1243template <class Impl>
1244FloatReg
1240}
1241
1242template <class Impl>
1243FloatReg
1245FullO3CPU<Impl>::readFloatReg(int reg_idx)
1244FullO3CPU<Impl>::readFloatReg(PhysRegIdPtr phys_reg)
1246{
1247 fpRegfileReads++;
1245{
1246 fpRegfileReads++;
1248 return regFile.readFloatReg(reg_idx);
1247 return regFile.readFloatReg(phys_reg);
1249}
1250
1251template <class Impl>
1252FloatRegBits
1248}
1249
1250template <class Impl>
1251FloatRegBits
1253FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
1252FullO3CPU<Impl>::readFloatRegBits(PhysRegIdPtr phys_reg)
1254{
1255 fpRegfileReads++;
1253{
1254 fpRegfileReads++;
1256 return regFile.readFloatRegBits(reg_idx);
1255 return regFile.readFloatRegBits(phys_reg);
1257}
1258
1259template <class Impl>
1260CCReg
1256}
1257
1258template <class Impl>
1259CCReg
1261FullO3CPU<Impl>::readCCReg(int reg_idx)
1260FullO3CPU<Impl>::readCCReg(PhysRegIdPtr phys_reg)
1262{
1263 ccRegfileReads++;
1261{
1262 ccRegfileReads++;
1264 return regFile.readCCReg(reg_idx);
1263 return regFile.readCCReg(phys_reg);
1265}
1266
1267template <class Impl>
1268void
1264}
1265
1266template <class Impl>
1267void
1269FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
1268FullO3CPU<Impl>::setIntReg(PhysRegIdPtr phys_reg, uint64_t val)
1270{
1271 intRegfileWrites++;
1269{
1270 intRegfileWrites++;
1272 regFile.setIntReg(reg_idx, val);
1271 regFile.setIntReg(phys_reg, val);
1273}
1274
1275template <class Impl>
1276void
1272}
1273
1274template <class Impl>
1275void
1277FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
1276FullO3CPU<Impl>::setFloatReg(PhysRegIdPtr phys_reg, FloatReg val)
1278{
1279 fpRegfileWrites++;
1277{
1278 fpRegfileWrites++;
1280 regFile.setFloatReg(reg_idx, val);
1279 regFile.setFloatReg(phys_reg, val);
1281}
1282
1283template <class Impl>
1284void
1280}
1281
1282template <class Impl>
1283void
1285FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
1284FullO3CPU<Impl>::setFloatRegBits(PhysRegIdPtr phys_reg, FloatRegBits val)
1286{
1287 fpRegfileWrites++;
1285{
1286 fpRegfileWrites++;
1288 regFile.setFloatRegBits(reg_idx, val);
1287 regFile.setFloatRegBits(phys_reg, val);
1289}
1290
1291template <class Impl>
1292void
1288}
1289
1290template <class Impl>
1291void
1293FullO3CPU<Impl>::setCCReg(int reg_idx, CCReg val)
1292FullO3CPU<Impl>::setCCReg(PhysRegIdPtr phys_reg, CCReg val)
1294{
1295 ccRegfileWrites++;
1293{
1294 ccRegfileWrites++;
1296 regFile.setCCReg(reg_idx, val);
1295 regFile.setCCReg(phys_reg, val);
1297}
1298
1299template <class Impl>
1300uint64_t
1301FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1302{
1303 intRegfileReads++;
1296}
1297
1298template <class Impl>
1299uint64_t
1300FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1301{
1302 intRegfileReads++;
1304 PhysRegIndex phys_reg = commitRenameMap[tid].lookupInt(reg_idx);
1303 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookupInt(reg_idx);
1305
1306 return regFile.readIntReg(phys_reg);
1307}
1308
1309template <class Impl>
1310float
1311FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
1312{
1313 fpRegfileReads++;
1304
1305 return regFile.readIntReg(phys_reg);
1306}
1307
1308template <class Impl>
1309float
1310FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
1311{
1312 fpRegfileReads++;
1314 PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1313 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1315
1316 return regFile.readFloatReg(phys_reg);
1317}
1318
1319template <class Impl>
1320uint64_t
1321FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid)
1322{
1323 fpRegfileReads++;
1314
1315 return regFile.readFloatReg(phys_reg);
1316}
1317
1318template <class Impl>
1319uint64_t
1320FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid)
1321{
1322 fpRegfileReads++;
1324 PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1323 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1325
1326 return regFile.readFloatRegBits(phys_reg);
1327}
1328
1329template <class Impl>
1330CCReg
1331FullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid)
1332{
1333 ccRegfileReads++;
1324
1325 return regFile.readFloatRegBits(phys_reg);
1326}
1327
1328template <class Impl>
1329CCReg
1330FullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid)
1331{
1332 ccRegfileReads++;
1334 PhysRegIndex phys_reg = commitRenameMap[tid].lookupCC(reg_idx);
1333 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookupCC(reg_idx);
1335
1336 return regFile.readCCReg(phys_reg);
1337}
1338
1339template <class Impl>
1340void
1341FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
1342{
1343 intRegfileWrites++;
1334
1335 return regFile.readCCReg(phys_reg);
1336}
1337
1338template <class Impl>
1339void
1340FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
1341{
1342 intRegfileWrites++;
1344 PhysRegIndex phys_reg = commitRenameMap[tid].lookupInt(reg_idx);
1343 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookupInt(reg_idx);
1345
1346 regFile.setIntReg(phys_reg, val);
1347}
1348
1349template <class Impl>
1350void
1351FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid)
1352{
1353 fpRegfileWrites++;
1344
1345 regFile.setIntReg(phys_reg, val);
1346}
1347
1348template <class Impl>
1349void
1350FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid)
1351{
1352 fpRegfileWrites++;
1354 PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1353 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1355
1356 regFile.setFloatReg(phys_reg, val);
1357}
1358
1359template <class Impl>
1360void
1361FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid)
1362{
1363 fpRegfileWrites++;
1354
1355 regFile.setFloatReg(phys_reg, val);
1356}
1357
1358template <class Impl>
1359void
1360FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid)
1361{
1362 fpRegfileWrites++;
1364 PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1363 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1365
1366 regFile.setFloatRegBits(phys_reg, val);
1367}
1368
1369template <class Impl>
1370void
1371FullO3CPU<Impl>::setArchCCReg(int reg_idx, CCReg val, ThreadID tid)
1372{
1373 ccRegfileWrites++;
1364
1365 regFile.setFloatRegBits(phys_reg, val);
1366}
1367
1368template <class Impl>
1369void
1370FullO3CPU<Impl>::setArchCCReg(int reg_idx, CCReg val, ThreadID tid)
1371{
1372 ccRegfileWrites++;
1374 PhysRegIndex phys_reg = commitRenameMap[tid].lookupCC(reg_idx);
1373 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookupCC(reg_idx);
1375
1376 regFile.setCCReg(phys_reg, val);
1377}
1378
1379template <class Impl>
1380TheISA::PCState
1381FullO3CPU<Impl>::pcState(ThreadID tid)
1382{

--- 302 unchanged lines hidden --- 		1374
1375 regFile.setCCReg(phys_reg, val);
1376}
1377
1378template <class Impl>
1379TheISA::PCState
1380FullO3CPU<Impl>::pcState(ThreadID tid)
1381{

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