cpu.cc (11877:5ea85692a53e) cpu.cc (12104:edd63f9c6184)
1/*
2 * Copyright (c) 2011-2012, 2014 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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783 // and not in the ThreadContext.
784 ThreadContext *src_tc;
785 if (FullSystem)
786 src_tc = system->threadContexts[tid];
787 else
788 src_tc = tcBase(tid);
789
790 //Bind Int Regs to Rename Map
1/*
2 * Copyright (c) 2011-2012, 2014 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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783 // and not in the ThreadContext.
784 ThreadContext *src_tc;
785 if (FullSystem)
786 src_tc = system->threadContexts[tid];
787 else
788 src_tc = tcBase(tid);
789
790 //Bind Int Regs to Rename Map
791 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
792 PhysRegIndex phys_reg = freeList.getIntReg();
793
791
794 renameMap[tid].setEntry(ireg,phys_reg);
792 for (RegId reg_id(IntRegClass, 0); reg_id.regIdx < TheISA::NumIntRegs;
793 reg_id.regIdx++) {
794 PhysRegIndex phys_reg = freeList.getIntReg();
795 renameMap[tid].setEntry(reg_id, phys_reg);
795 scoreboard.setReg(phys_reg);
796 }
797
798 //Bind Float Regs to Rename Map
796 scoreboard.setReg(phys_reg);
797 }
798
799 //Bind Float Regs to Rename Map
799 int max_reg = TheISA::FP_Reg_Base + TheISA::NumFloatRegs;
800 for (int freg = TheISA::FP_Reg_Base; freg < max_reg; freg++) {
800 for (RegId reg_id(FloatRegClass, 0); reg_id.regIdx < TheISA::NumFloatRegs;
801 reg_id.regIdx++) {
801 PhysRegIndex phys_reg = freeList.getFloatReg();
802 PhysRegIndex phys_reg = freeList.getFloatReg();
802
803 renameMap[tid].setEntry(freg,phys_reg);
803 renameMap[tid].setEntry(reg_id, phys_reg);
804 scoreboard.setReg(phys_reg);
805 }
806
807 //Bind condition-code Regs to Rename Map
804 scoreboard.setReg(phys_reg);
805 }
806
807 //Bind condition-code Regs to Rename Map
808 max_reg = TheISA::CC_Reg_Base + TheISA::NumCCRegs;
809 for (int creg = TheISA::CC_Reg_Base;
810 creg < max_reg; creg++) {
808 for (RegId reg_id(CCRegClass, 0); reg_id.regIdx < TheISA::NumCCRegs;
809 reg_id.regIdx++) {
811 PhysRegIndex phys_reg = freeList.getCCReg();
810 PhysRegIndex phys_reg = freeList.getCCReg();
812
813 renameMap[tid].setEntry(creg,phys_reg);
811 renameMap[tid].setEntry(reg_id, phys_reg);
814 scoreboard.setReg(phys_reg);
815 }
816
817 //Copy Thread Data Into RegFile
818 //this->copyFromTC(tid);
819
820 //Set PC/NPC/NNPC
821 pcState(src_tc->pcState(), tid);

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840 // this->copyToTC(tid);
841
842
843 // @todo: 2-27-2008: Fix how we free up rename mappings
844 // here to alleviate the case for double-freeing registers
845 // in SMT workloads.
846
847 // Unbind Int Regs from Rename Map
812 scoreboard.setReg(phys_reg);
813 }
814
815 //Copy Thread Data Into RegFile
816 //this->copyFromTC(tid);
817
818 //Set PC/NPC/NNPC
819 pcState(src_tc->pcState(), tid);

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838 // this->copyToTC(tid);
839
840
841 // @todo: 2-27-2008: Fix how we free up rename mappings
842 // here to alleviate the case for double-freeing registers
843 // in SMT workloads.
844
845 // Unbind Int Regs from Rename Map
848 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
849 PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
846 for (RegId reg_id(IntRegClass, 0); reg_id.regIdx < TheISA::NumIntRegs;
847 reg_id.regIdx++) {
848 PhysRegIndex phys_reg = renameMap[tid].lookup(reg_id);
850 scoreboard.unsetReg(phys_reg);
851 freeList.addReg(phys_reg);
852 }
853
854 // Unbind Float Regs from Rename Map
849 scoreboard.unsetReg(phys_reg);
850 freeList.addReg(phys_reg);
851 }
852
853 // Unbind Float Regs from Rename Map
855 int max_reg = TheISA::FP_Reg_Base + TheISA::NumFloatRegs;
856 for (int freg = TheISA::FP_Reg_Base; freg < max_reg; freg++) {
857 PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
854 for (RegId reg_id(FloatRegClass, 0); reg_id.regIdx < TheISA::NumFloatRegs;
855 reg_id.regIdx++) {
856 PhysRegIndex phys_reg = renameMap[tid].lookup(reg_id);
858 scoreboard.unsetReg(phys_reg);
859 freeList.addReg(phys_reg);
860 }
861
862 // Unbind condition-code Regs from Rename Map
857 scoreboard.unsetReg(phys_reg);
858 freeList.addReg(phys_reg);
859 }
860
861 // Unbind condition-code Regs from Rename Map
863 max_reg = TheISA::CC_Reg_Base + TheISA::NumCCRegs;
864 for (int creg = TheISA::CC_Reg_Base; creg < max_reg; creg++) {
865 PhysRegIndex phys_reg = renameMap[tid].lookup(creg);
862 for (RegId reg_id(CCRegClass, 0); reg_id.regIdx < TheISA::NumCCRegs;
863 reg_id.regIdx++) {
864 PhysRegIndex phys_reg = renameMap[tid].lookup(reg_id);
866 scoreboard.unsetReg(phys_reg);
867 freeList.addReg(phys_reg);
868 }
869
870 // Squash Throughout Pipeline
871 DynInstPtr inst = commit.rob->readHeadInst(tid);
872 InstSeqNum squash_seq_num = inst->seqNum;
873 fetch.squash(0, squash_seq_num, inst, tid);

--- 812 unchanged lines hidden --- 		865 scoreboard.unsetReg(phys_reg);
866 freeList.addReg(phys_reg);
867 }
868
869 // Squash Throughout Pipeline
870 DynInstPtr inst = commit.rob->readHeadInst(tid);
871 InstSeqNum squash_seq_num = inst->seqNum;
872 fetch.squash(0, squash_seq_num, inst, tid);

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