cpu.cc (10905:a6ca6831e775) cpu.cc (10910:32f3d1c454ec)
1/*
2 * Copyright (c) 2011-2012, 2014 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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534}
535
536template <class Impl>
537void
538FullO3CPU<Impl>::tick()
539{
540 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
541 assert(!switchedOut());
1/*
2 * Copyright (c) 2011-2012, 2014 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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534}
535
536template <class Impl>
537void
538FullO3CPU<Impl>::tick()
539{
540 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
541 assert(!switchedOut());
542 assert(getDrainState() != Drainable::Drained);
542 assert(getDrainState() != DrainState::Drained);
543
544 ++numCycles;
545 ppCycles->notify(1);
546
547// activity = false;
548
549 //Tick each of the stages
550 fetch.tick();

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707 assert(!switchedOut());
708
709 // Needs to set each stage to running as well.
710 activateThread(tid);
711
712 // We don't want to wake the CPU if it is drained. In that case,
713 // we just want to flag the thread as active and schedule the tick
714 // event from drainResume() instead.
543
544 ++numCycles;
545 ppCycles->notify(1);
546
547// activity = false;
548
549 //Tick each of the stages
550 fetch.tick();

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707 assert(!switchedOut());
708
709 // Needs to set each stage to running as well.
710 activateThread(tid);
711
712 // We don't want to wake the CPU if it is drained. In that case,
713 // we just want to flag the thread as active and schedule the tick
714 // event from drainResume() instead.
715 if (getDrainState() == Drainable::Drained)
715 if (getDrainState() == DrainState::Drained)
716 return;
717
718 // If we are time 0 or if the last activation time is in the past,
719 // schedule the next tick and wake up the fetch unit
720 if (lastActivatedCycle == 0 || lastActivatedCycle < curTick()) {
721 scheduleTickEvent(Cycles(0));
722
723 // Be sure to signal that there's some activity so the CPU doesn't

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999}
1000
1001template <class Impl>
1002unsigned int
1003FullO3CPU<Impl>::drain(DrainManager *drain_manager)
1004{
1005 // If the CPU isn't doing anything, then return immediately.
1006 if (switchedOut()) {
716 return;
717
718 // If we are time 0 or if the last activation time is in the past,
719 // schedule the next tick and wake up the fetch unit
720 if (lastActivatedCycle == 0 || lastActivatedCycle < curTick()) {
721 scheduleTickEvent(Cycles(0));
722
723 // Be sure to signal that there's some activity so the CPU doesn't

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999}
1000
1001template <class Impl>
1002unsigned int
1003FullO3CPU<Impl>::drain(DrainManager *drain_manager)
1004{
1005 // If the CPU isn't doing anything, then return immediately.
1006 if (switchedOut()) {
1007 setDrainState(Drainable::Drained);
1007 setDrainState(DrainState::Drained);
1008 return 0;
1009 }
1010
1011 DPRINTF(Drain, "Draining...\n");
1008 return 0;
1009 }
1010
1011 DPRINTF(Drain, "Draining...\n");
1012 setDrainState(Drainable::Draining);
1012 setDrainState(DrainState::Draining);
1013
1014 // We only need to signal a drain to the commit stage as this
1015 // initiates squashing controls the draining. Once the commit
1016 // stage commits an instruction where it is safe to stop, it'll
1017 // squash the rest of the instructions in the pipeline and force
1018 // the fetch stage to stall. The pipeline will be drained once all
1019 // in-flight instructions have retired.
1020 commit.drain();

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1026
1027 wakeCPU();
1028 activityRec.activity();
1029
1030 DPRINTF(Drain, "CPU not drained\n");
1031
1032 return 1;
1033 } else {
1013
1014 // We only need to signal a drain to the commit stage as this
1015 // initiates squashing controls the draining. Once the commit
1016 // stage commits an instruction where it is safe to stop, it'll
1017 // squash the rest of the instructions in the pipeline and force
1018 // the fetch stage to stall. The pipeline will be drained once all
1019 // in-flight instructions have retired.
1020 commit.drain();

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1026
1027 wakeCPU();
1028 activityRec.activity();
1029
1030 DPRINTF(Drain, "CPU not drained\n");
1031
1032 return 1;
1033 } else {
1034 setDrainState(Drainable::Drained);
1034 setDrainState(DrainState::Drained);
1035 DPRINTF(Drain, "CPU is already drained\n");
1036 if (tickEvent.scheduled())
1037 deschedule(tickEvent);
1038
1039 // Flush out any old data from the time buffers. In
1040 // particular, there might be some data in flight from the
1041 // fetch stage that isn't visible in any of the CPU buffers we
1042 // test in isDrained().

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1127{
1128 fetch.drainStall(tid);
1129}
1130
1131template <class Impl>
1132void
1133FullO3CPU<Impl>::drainResume()
1134{
1035 DPRINTF(Drain, "CPU is already drained\n");
1036 if (tickEvent.scheduled())
1037 deschedule(tickEvent);
1038
1039 // Flush out any old data from the time buffers. In
1040 // particular, there might be some data in flight from the
1041 // fetch stage that isn't visible in any of the CPU buffers we
1042 // test in isDrained().

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1127{
1128 fetch.drainStall(tid);
1129}
1130
1131template <class Impl>
1132void
1133FullO3CPU<Impl>::drainResume()
1134{
1135 setDrainState(Drainable::Running);
1135 setDrainState(DrainState::Running);
1136 if (switchedOut())
1137 return;
1138
1139 DPRINTF(Drain, "Resuming...\n");
1140 verifyMemoryMode();
1141
1142 fetch.drainResume();
1143 commit.drainResume();

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1137 return;
1138
1139 DPRINTF(Drain, "Resuming...\n");
1140 verifyMemoryMode();
1141
1142 fetch.drainResume();
1143 commit.drainResume();

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