cpu.cc (10774:68d688cbe26c) cpu.cc (10821:581fb2484bd6)
1/*
2 * Copyright (c) 2011-2012, 2014 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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87 BaseCPU::regStats();
88}
89
90template<class Impl>
91bool
92FullO3CPU<Impl>::IcachePort::recvTimingResp(PacketPtr pkt)
93{
94 DPRINTF(O3CPU, "Fetch unit received timing\n");
1/*
2 * Copyright (c) 2011-2012, 2014 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 78 unchanged lines hidden (view full) ---

87 BaseCPU::regStats();
88}
89
90template<class Impl>
91bool
92FullO3CPU<Impl>::IcachePort::recvTimingResp(PacketPtr pkt)
93{
94 DPRINTF(O3CPU, "Fetch unit received timing\n");
95 // We shouldn't ever get a block in ownership state
96 assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted()));
95 // We shouldn't ever get a cacheable block in ownership state
96 assert(pkt->req->isUncacheable() ||
97 !(pkt->memInhibitAsserted() && !pkt->sharedAsserted()));
97 fetch->processCacheCompletion(pkt);
98
99 return true;
100}
101
102template<class Impl>
103void
104FullO3CPU<Impl>::IcachePort::recvReqRetry()

--- 1583 unchanged lines hidden --- 		98 fetch->processCacheCompletion(pkt);
99
100 return true;
101}
102
103template<class Impl>
104void
105FullO3CPU<Impl>::IcachePort::recvReqRetry()

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