cpu.cc (10487:5914229e6b16) cpu.cc (10529:05b5a6cf3521)
1/*
2 * Copyright (c) 2011-2012, 2014 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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112{
113 return lsq->recvTimingResp(pkt);
114}
115
116template <class Impl>
117void
118FullO3CPU<Impl>::DcachePort::recvTimingSnoopReq(PacketPtr pkt)
119{
1/*
2 * Copyright (c) 2011-2012, 2014 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 103 unchanged lines hidden (view full) ---

112{
113 return lsq->recvTimingResp(pkt);
114}
115
116template <class Impl>
117void
118FullO3CPU<Impl>::DcachePort::recvTimingSnoopReq(PacketPtr pkt)
119{
120 // X86 ISA: Snooping an invalidation for monitor/mwait
121 if(cpu->getCpuAddrMonitor()->doMonitor(pkt)) {
122 cpu->wakeup();
123 }
120 lsq->recvTimingSnoopReq(pkt);
121}
122
123template <class Impl>
124void
125FullO3CPU<Impl>::DcachePort::recvRetry()
126{
127 lsq->recvRetry();

--- 1555 unchanged lines hidden --- 		124 lsq->recvTimingSnoopReq(pkt);
125}
126
127template <class Impl>
128void
129FullO3CPU<Impl>::DcachePort::recvRetry()
130{
131 lsq->recvRetry();

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