cpu.cc (10464:2a0fe8bca031) cpu.cc (10487:5914229e6b16)
1/*
2 * Copyright (c) 2011-2012, 2014 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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830
831 // @todo: 2-27-2008: Fix how we free up rename mappings
832 // here to alleviate the case for double-freeing registers
833 // in SMT workloads.
834
835 // Unbind Int Regs from Rename Map
836 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
837 PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
1/*
2 * Copyright (c) 2011-2012, 2014 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 821 unchanged lines hidden (view full) ---

830
831 // @todo: 2-27-2008: Fix how we free up rename mappings
832 // here to alleviate the case for double-freeing registers
833 // in SMT workloads.
834
835 // Unbind Int Regs from Rename Map
836 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
837 PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
838
839 scoreboard.unsetReg(phys_reg);
840 freeList.addReg(phys_reg);
841 }
842
843 // Unbind Float Regs from Rename Map
838 scoreboard.unsetReg(phys_reg);
839 freeList.addReg(phys_reg);
840 }
841
842 // Unbind Float Regs from Rename Map
844 int max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs;
845 for (int freg = TheISA::NumIntRegs; freg < max_reg; freg++) {
843 int max_reg = TheISA::FP_Reg_Base + TheISA::NumFloatRegs;
844 for (int freg = TheISA::FP_Reg_Base; freg < max_reg; freg++) {
846 PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
845 PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
847
848 scoreboard.unsetReg(phys_reg);
849 freeList.addReg(phys_reg);
850 }
851
852 // Unbind condition-code Regs from Rename Map
846 scoreboard.unsetReg(phys_reg);
847 freeList.addReg(phys_reg);
848 }
849
850 // Unbind condition-code Regs from Rename Map
853 max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs + TheISA::NumCCRegs;
854 for (int creg = TheISA::NumIntRegs + TheISA::NumFloatRegs;
855 creg < max_reg; creg++) {
851 max_reg = TheISA::CC_Reg_Base + TheISA::NumCCRegs;
852 for (int creg = TheISA::CC_Reg_Base; creg < max_reg; creg++) {
856 PhysRegIndex phys_reg = renameMap[tid].lookup(creg);
853 PhysRegIndex phys_reg = renameMap[tid].lookup(creg);
857
858 scoreboard.unsetReg(phys_reg);
859 freeList.addReg(phys_reg);
860 }
861
862 // Squash Throughout Pipeline
863 DynInstPtr inst = commit.rob->readHeadInst(tid);
864 InstSeqNum squash_seq_num = inst->seqNum;
865 fetch.squash(0, squash_seq_num, inst, tid);

--- 821 unchanged lines hidden --- 		854 scoreboard.unsetReg(phys_reg);
855 freeList.addReg(phys_reg);
856 }
857
858 // Squash Throughout Pipeline
859 DynInstPtr inst = commit.rob->readHeadInst(tid);
860 InstSeqNum squash_seq_num = inst->seqNum;
861 fetch.squash(0, squash_seq_num, inst, tid);

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