66{ 67} 68 69void 70BaseO3CPU::regStats() 71{ 72 BaseCPU::regStats(); 73} 74 75template <class Impl> 76FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 77 : Event(CPU_Tick_Pri), cpu(c) 78{ 79} 80 81template <class Impl> 82void 83FullO3CPU<Impl>::TickEvent::process() 84{ 85 cpu->tick(); 86} 87 88template <class Impl> 89const char * 90FullO3CPU<Impl>::TickEvent::description() const 91{ 92 return "FullO3CPU tick"; 93} 94 95template <class Impl> 96FullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent() 97 : Event(CPU_Switch_Pri) 98{ 99} 100 101template <class Impl> 102void 103FullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num, 104 FullO3CPU<Impl> *thread_cpu) 105{ 106 tid = thread_num; 107 cpu = thread_cpu; 108} 109 110template <class Impl> 111void 112FullO3CPU<Impl>::ActivateThreadEvent::process() 113{ 114 cpu->activateThread(tid); 115} 116 117template <class Impl> 118const char * 119FullO3CPU<Impl>::ActivateThreadEvent::description() const 120{ 121 return "FullO3CPU \"Activate Thread\""; 122} 123 124template <class Impl> 125FullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent() 126 : Event(CPU_Tick_Pri), tid(0), remove(false), cpu(NULL) 127{ 128} 129 130template <class Impl> 131void 132FullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num, 133 FullO3CPU<Impl> *thread_cpu) 134{ 135 tid = thread_num; 136 cpu = thread_cpu; 137 remove = false; 138} 139 140template <class Impl> 141void 142FullO3CPU<Impl>::DeallocateContextEvent::process() 143{ 144 cpu->deactivateThread(tid); 145 if (remove) 146 cpu->removeThread(tid); 147} 148 149template <class Impl> 150const char * 151FullO3CPU<Impl>::DeallocateContextEvent::description() const 152{ 153 return "FullO3CPU \"Deallocate Context\""; 154} 155 156template <class Impl> 157FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) 158 : BaseO3CPU(params), 159 itb(params->itb), 160 dtb(params->dtb), 161 tickEvent(this), 162 removeInstsThisCycle(false), 163 fetch(this, params), 164 decode(this, params), 165 rename(this, params), 166 iew(this, params), 167 commit(this, params), 168 169 regFile(this, params->numPhysIntRegs, 170 params->numPhysFloatRegs), 171 172 freeList(params->numThreads, 173 TheISA::NumIntRegs, params->numPhysIntRegs, 174 TheISA::NumFloatRegs, params->numPhysFloatRegs), 175 176 rob(this, 177 params->numROBEntries, params->squashWidth, 178 params->smtROBPolicy, params->smtROBThreshold, 179 params->numThreads), 180 181 scoreboard(params->numThreads, 182 TheISA::NumIntRegs, params->numPhysIntRegs, 183 TheISA::NumFloatRegs, params->numPhysFloatRegs, 184 TheISA::NumMiscRegs * number_of_threads, 185 TheISA::ZeroReg), 186 187 timeBuffer(params->backComSize, params->forwardComSize), 188 fetchQueue(params->backComSize, params->forwardComSize), 189 decodeQueue(params->backComSize, params->forwardComSize), 190 renameQueue(params->backComSize, params->forwardComSize), 191 iewQueue(params->backComSize, params->forwardComSize), 192 activityRec(NumStages, 193 params->backComSize + params->forwardComSize, 194 params->activity), 195 196 globalSeqNum(1), 197#if FULL_SYSTEM 198 system(params->system), 199 physmem(system->physmem), 200#endif // FULL_SYSTEM 201 drainCount(0), 202 deferRegistration(params->defer_registration), 203 numThreads(number_of_threads) 204{ 205 if (!deferRegistration) { 206 _status = Running; 207 } else { 208 _status = Idle; 209 } 210 211#if USE_CHECKER 212 if (params->checker) { 213 BaseCPU *temp_checker = params->checker; 214 checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker); 215#if FULL_SYSTEM 216 checker->setSystem(params->system); 217#endif 218 } else { 219 checker = NULL; 220 } 221#endif // USE_CHECKER 222 223#if !FULL_SYSTEM 224 thread.resize(number_of_threads); 225 tids.resize(number_of_threads); 226#endif 227 228 // The stages also need their CPU pointer setup. However this 229 // must be done at the upper level CPU because they have pointers 230 // to the upper level CPU, and not this FullO3CPU. 231 232 // Set up Pointers to the activeThreads list for each stage 233 fetch.setActiveThreads(&activeThreads); 234 decode.setActiveThreads(&activeThreads); 235 rename.setActiveThreads(&activeThreads); 236 iew.setActiveThreads(&activeThreads); 237 commit.setActiveThreads(&activeThreads); 238 239 // Give each of the stages the time buffer they will use. 240 fetch.setTimeBuffer(&timeBuffer); 241 decode.setTimeBuffer(&timeBuffer); 242 rename.setTimeBuffer(&timeBuffer); 243 iew.setTimeBuffer(&timeBuffer); 244 commit.setTimeBuffer(&timeBuffer); 245 246 // Also setup each of the stages' queues. 247 fetch.setFetchQueue(&fetchQueue); 248 decode.setFetchQueue(&fetchQueue); 249 commit.setFetchQueue(&fetchQueue); 250 decode.setDecodeQueue(&decodeQueue); 251 rename.setDecodeQueue(&decodeQueue); 252 rename.setRenameQueue(&renameQueue); 253 iew.setRenameQueue(&renameQueue); 254 iew.setIEWQueue(&iewQueue); 255 commit.setIEWQueue(&iewQueue); 256 commit.setRenameQueue(&renameQueue); 257 258 commit.setIEWStage(&iew); 259 rename.setIEWStage(&iew); 260 rename.setCommitStage(&commit); 261 262#if !FULL_SYSTEM 263 int active_threads = params->workload.size(); 264 265 if (active_threads > Impl::MaxThreads) { 266 panic("Workload Size too large. Increase the 'MaxThreads'" 267 "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or " 268 "edit your workload size."); 269 } 270#else 271 int active_threads = 1; 272#endif 273 274 //Make Sure That this a Valid Architeture 275 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 276 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 277 278 rename.setScoreboard(&scoreboard); 279 iew.setScoreboard(&scoreboard); 280 281 // Setup the rename map for whichever stages need it. 282 PhysRegIndex lreg_idx = 0; 283 PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs 284 285 for (int tid=0; tid < numThreads; tid++) { 286 bool bindRegs = (tid <= active_threads - 1); 287 288 commitRenameMap[tid].init(TheISA::NumIntRegs, 289 params->numPhysIntRegs, 290 lreg_idx, //Index for Logical. Regs 291 292 TheISA::NumFloatRegs, 293 params->numPhysFloatRegs, 294 freg_idx, //Index for Float Regs 295 296 TheISA::NumMiscRegs, 297 298 TheISA::ZeroReg, 299 TheISA::ZeroReg, 300 301 tid, 302 false); 303 304 renameMap[tid].init(TheISA::NumIntRegs, 305 params->numPhysIntRegs, 306 lreg_idx, //Index for Logical. Regs 307 308 TheISA::NumFloatRegs, 309 params->numPhysFloatRegs, 310 freg_idx, //Index for Float Regs 311 312 TheISA::NumMiscRegs, 313 314 TheISA::ZeroReg, 315 TheISA::ZeroReg, 316 317 tid, 318 bindRegs); 319 320 activateThreadEvent[tid].init(tid, this); 321 deallocateContextEvent[tid].init(tid, this); 322 } 323 324 rename.setRenameMap(renameMap); 325 commit.setRenameMap(commitRenameMap); 326 327 // Give renameMap & rename stage access to the freeList; 328 for (int i=0; i < numThreads; i++) { 329 renameMap[i].setFreeList(&freeList); 330 } 331 rename.setFreeList(&freeList); 332 333 // Setup the ROB for whichever stages need it. 334 commit.setROB(&rob); 335 336 lastRunningCycle = curTick; 337 338 lastActivatedCycle = -1; 339 340 // Give renameMap & rename stage access to the freeList; 341 //for (int i=0; i < numThreads; i++) { 342 //globalSeqNum[i] = 1; 343 //} 344 345 contextSwitch = false; 346 DPRINTF(O3CPU, "Creating O3CPU object.\n"); 347 348 // Setup any thread state. 349 this->thread.resize(this->numThreads); 350 351 for (int i = 0; i < this->numThreads; ++i) { 352#if FULL_SYSTEM 353 // SMT is not supported in FS mode yet. 354 assert(this->numThreads == 1); 355 this->thread[i] = new Thread(this, 0); 356 this->thread[i]->setStatus(ThreadContext::Suspended); 357#else 358 if (i < params->workload.size()) { 359 DPRINTF(O3CPU, "Workload[%i] process is %#x", 360 i, this->thread[i]); 361 this->thread[i] = new typename FullO3CPU<Impl>::Thread( 362 (typename Impl::O3CPU *)(this), 363 i, params->workload[i], i); 364 365 this->thread[i]->setStatus(ThreadContext::Suspended); 366 367 //usedTids[i] = true; 368 //threadMap[i] = i; 369 } else { 370 //Allocate Empty thread so M5 can use later 371 //when scheduling threads to CPU 372 Process* dummy_proc = NULL; 373 374 this->thread[i] = new typename FullO3CPU<Impl>::Thread( 375 (typename Impl::O3CPU *)(this), 376 i, dummy_proc, i); 377 //usedTids[i] = false; 378 } 379#endif // !FULL_SYSTEM 380 381 ThreadContext *tc; 382 383 // Setup the TC that will serve as the interface to the threads/CPU. 384 O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>; 385 386 tc = o3_tc; 387 388 // If we're using a checker, then the TC should be the 389 // CheckerThreadContext. 390#if USE_CHECKER 391 if (params->checker) { 392 tc = new CheckerThreadContext<O3ThreadContext<Impl> >( 393 o3_tc, this->checker); 394 } 395#endif 396 397 o3_tc->cpu = (typename Impl::O3CPU *)(this); 398 assert(o3_tc->cpu); 399 o3_tc->thread = this->thread[i]; 400 401#if FULL_SYSTEM 402 // Setup quiesce event. 403 this->thread[i]->quiesceEvent = new EndQuiesceEvent(tc); 404#endif 405 // Give the thread the TC. 406 this->thread[i]->tc = tc;
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614#endif 615 } 616 617 // Clear inSyscall. 618 for (int i = 0; i < number_of_threads; ++i) 619 thread[i]->inSyscall = false; 620 621 // Initialize stages. 622 fetch.initStage(); 623 iew.initStage(); 624 rename.initStage(); 625 commit.initStage(); 626 627 commit.setThreads(thread); 628} 629 630template <class Impl> 631void 632FullO3CPU<Impl>::activateThread(unsigned tid) 633{ 634 std::list<unsigned>::iterator isActive = 635 std::find(activeThreads.begin(), activeThreads.end(), tid); 636 637 DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid); 638 639 if (isActive == activeThreads.end()) { 640 DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n", 641 tid); 642 643 activeThreads.push_back(tid); 644 } 645} 646 647template <class Impl> 648void 649FullO3CPU<Impl>::deactivateThread(unsigned tid) 650{ 651 //Remove From Active List, if Active 652 std::list<unsigned>::iterator thread_it = 653 std::find(activeThreads.begin(), activeThreads.end(), tid); 654 655 DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid); 656 657 if (thread_it != activeThreads.end()) { 658 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 659 tid); 660 activeThreads.erase(thread_it); 661 } 662} 663 664template <class Impl> 665void 666FullO3CPU<Impl>::activateContext(int tid, int delay) 667{ 668 // Needs to set each stage to running as well. 669 if (delay){ 670 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate " 671 "on cycle %d\n", tid, curTick + ticks(delay)); 672 scheduleActivateThreadEvent(tid, delay); 673 } else { 674 activateThread(tid); 675 } 676 677 if (lastActivatedCycle < curTick) { 678 scheduleTickEvent(delay); 679 680 // Be sure to signal that there's some activity so the CPU doesn't 681 // deschedule itself. 682 activityRec.activity(); 683 fetch.wakeFromQuiesce(); 684 685 lastActivatedCycle = curTick; 686 687 _status = Running; 688 } 689} 690 691template <class Impl> 692bool 693FullO3CPU<Impl>::deallocateContext(int tid, bool remove, int delay) 694{ 695 // Schedule removal of thread data from CPU 696 if (delay){ 697 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate " 698 "on cycle %d\n", tid, curTick + ticks(delay)); 699 scheduleDeallocateContextEvent(tid, remove, delay); 700 return false; 701 } else { 702 deactivateThread(tid); 703 if (remove) 704 removeThread(tid); 705 return true; 706 } 707} 708 709template <class Impl> 710void 711FullO3CPU<Impl>::suspendContext(int tid) 712{ 713 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid); 714 bool deallocated = deallocateContext(tid, false, 1); 715 // If this was the last thread then unschedule the tick event. 716 if ((activeThreads.size() == 1 && !deallocated) || 717 activeThreads.size() == 0) 718 unscheduleTickEvent(); 719 _status = Idle; 720} 721 722template <class Impl> 723void 724FullO3CPU<Impl>::haltContext(int tid) 725{ 726 //For now, this is the same as deallocate 727 DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid); 728 deallocateContext(tid, true, 1); 729} 730 731template <class Impl> 732void 733FullO3CPU<Impl>::insertThread(unsigned tid) 734{ 735 DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); 736 // Will change now that the PC and thread state is internal to the CPU 737 // and not in the ThreadContext. 738#if FULL_SYSTEM 739 ThreadContext *src_tc = system->threadContexts[tid]; 740#else 741 ThreadContext *src_tc = tcBase(tid); 742#endif 743 744 //Bind Int Regs to Rename Map 745 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 746 PhysRegIndex phys_reg = freeList.getIntReg(); 747 748 renameMap[tid].setEntry(ireg,phys_reg); 749 scoreboard.setReg(phys_reg); 750 } 751 752 //Bind Float Regs to Rename Map 753 for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 754 PhysRegIndex phys_reg = freeList.getFloatReg(); 755 756 renameMap[tid].setEntry(freg,phys_reg); 757 scoreboard.setReg(phys_reg); 758 } 759 760 //Copy Thread Data Into RegFile 761 //this->copyFromTC(tid); 762 763 //Set PC/NPC/NNPC 764 setPC(src_tc->readPC(), tid); 765 setNextPC(src_tc->readNextPC(), tid); 766 setNextNPC(src_tc->readNextNPC(), tid); 767 768 src_tc->setStatus(ThreadContext::Active); 769 770 activateContext(tid,1); 771 772 //Reset ROB/IQ/LSQ Entries 773 commit.rob->resetEntries(); 774 iew.resetEntries(); 775} 776 777template <class Impl> 778void 779FullO3CPU<Impl>::removeThread(unsigned tid) 780{ 781 DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid); 782 783 // Copy Thread Data From RegFile 784 // If thread is suspended, it might be re-allocated 785 // this->copyToTC(tid); 786 787 788 // @todo: 2-27-2008: Fix how we free up rename mappings 789 // here to alleviate the case for double-freeing registers 790 // in SMT workloads. 791 792 // Unbind Int Regs from Rename Map 793 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 794 PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 795 796 scoreboard.unsetReg(phys_reg); 797 freeList.addReg(phys_reg); 798 } 799 800 // Unbind Float Regs from Rename Map 801 for (int freg = TheISA::NumIntRegs; freg < TheISA::NumFloatRegs; freg++) { 802 PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 803 804 scoreboard.unsetReg(phys_reg); 805 freeList.addReg(phys_reg); 806 } 807 808 // Squash Throughout Pipeline 809 InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum; 810 fetch.squash(0, sizeof(TheISA::MachInst), 0, squash_seq_num, tid); 811 decode.squash(tid); 812 rename.squash(squash_seq_num, tid); 813 iew.squash(tid); 814 iew.ldstQueue.squash(squash_seq_num, tid); 815 commit.rob->squash(squash_seq_num, tid); 816 817 818 assert(iew.instQueue.getCount(tid) == 0); 819 assert(iew.ldstQueue.getCount(tid) == 0); 820 821 // Reset ROB/IQ/LSQ Entries 822 823 // Commented out for now. This should be possible to do by 824 // telling all the pipeline stages to drain first, and then 825 // checking until the drain completes. Once the pipeline is 826 // drained, call resetEntries(). - 10-09-06 ktlim 827/* 828 if (activeThreads.size() >= 1) { 829 commit.rob->resetEntries(); 830 iew.resetEntries(); 831 } 832*/ 833} 834 835 836template <class Impl> 837void 838FullO3CPU<Impl>::activateWhenReady(int tid) 839{ 840 DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming" 841 "(e.g. PhysRegs/ROB/IQ/LSQ) \n", 842 tid); 843 844 bool ready = true; 845 846 if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) { 847 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 848 "Phys. Int. Regs.\n", 849 tid); 850 ready = false; 851 } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) { 852 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 853 "Phys. Float. Regs.\n", 854 tid); 855 ready = false; 856 } else if (commit.rob->numFreeEntries() >= 857 commit.rob->entryAmount(activeThreads.size() + 1)) { 858 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 859 "ROB entries.\n", 860 tid); 861 ready = false; 862 } else if (iew.instQueue.numFreeEntries() >= 863 iew.instQueue.entryAmount(activeThreads.size() + 1)) { 864 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 865 "IQ entries.\n", 866 tid); 867 ready = false; 868 } else if (iew.ldstQueue.numFreeEntries() >= 869 iew.ldstQueue.entryAmount(activeThreads.size() + 1)) { 870 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 871 "LSQ entries.\n", 872 tid); 873 ready = false; 874 } 875 876 if (ready) { 877 insertThread(tid); 878 879 contextSwitch = false; 880 881 cpuWaitList.remove(tid); 882 } else { 883 suspendContext(tid); 884 885 //blocks fetch 886 contextSwitch = true; 887 888 //@todo: dont always add to waitlist 889 //do waitlist 890 cpuWaitList.push_back(tid); 891 } 892} 893 894#if FULL_SYSTEM 895template <class Impl> 896void 897FullO3CPU<Impl>::postInterrupt(int int_num, int index) 898{ 899 BaseCPU::postInterrupt(int_num, index); 900 901 if (this->thread[0]->status() == ThreadContext::Suspended) { 902 DPRINTF(IPI,"Suspended Processor awoke\n"); 903 this->threadContexts[0]->activate(); 904 } 905} 906 907template <class Impl> 908Fault 909FullO3CPU<Impl>::hwrei(unsigned tid) 910{ 911#if THE_ISA == ALPHA_ISA 912 // Need to clear the lock flag upon returning from an interrupt. 913 this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid); 914 915 this->thread[tid]->kernelStats->hwrei(); 916 917 // FIXME: XXX check for interrupts? XXX 918#endif 919 return NoFault; 920} 921 922template <class Impl> 923bool 924FullO3CPU<Impl>::simPalCheck(int palFunc, unsigned tid) 925{ 926#if THE_ISA == ALPHA_ISA 927 if (this->thread[tid]->kernelStats) 928 this->thread[tid]->kernelStats->callpal(palFunc, 929 this->threadContexts[tid]); 930 931 switch (palFunc) { 932 case PAL::halt: 933 halt(); 934 if (--System::numSystemsRunning == 0) 935 exitSimLoop("all cpus halted"); 936 break; 937 938 case PAL::bpt: 939 case PAL::bugchk: 940 if (this->system->breakpoint()) 941 return false; 942 break; 943 } 944#endif 945 return true; 946} 947 948template <class Impl> 949Fault 950FullO3CPU<Impl>::getInterrupts() 951{ 952 // Check if there are any outstanding interrupts 953 return this->interrupts->getInterrupt(this->threadContexts[0]); 954} 955 956template <class Impl> 957void 958FullO3CPU<Impl>::processInterrupts(Fault interrupt) 959{ 960 // Check for interrupts here. For now can copy the code that 961 // exists within isa_fullsys_traits.hh. Also assume that thread 0 962 // is the one that handles the interrupts. 963 // @todo: Possibly consolidate the interrupt checking code. 964 // @todo: Allow other threads to handle interrupts. 965 966 assert(interrupt != NoFault); 967 this->interrupts->updateIntrInfo(this->threadContexts[0]); 968 969 DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name()); 970 this->trap(interrupt, 0); 971} 972 973template <class Impl> 974void 975FullO3CPU<Impl>::updateMemPorts() 976{ 977 // Update all ThreadContext's memory ports (Functional/Virtual 978 // Ports) 979 for (int i = 0; i < thread.size(); ++i) 980 thread[i]->connectMemPorts(thread[i]->getTC()); 981} 982#endif 983 984template <class Impl> 985void 986FullO3CPU<Impl>::trap(Fault fault, unsigned tid) 987{ 988 // Pass the thread's TC into the invoke method. 989 fault->invoke(this->threadContexts[tid]); 990} 991 992#if !FULL_SYSTEM 993 994template <class Impl> 995void 996FullO3CPU<Impl>::syscall(int64_t callnum, int tid) 997{ 998 DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid); 999 1000 DPRINTF(Activity,"Activity: syscall() called.\n"); 1001 1002 // Temporarily increase this by one to account for the syscall 1003 // instruction. 1004 ++(this->thread[tid]->funcExeInst); 1005 1006 // Execute the actual syscall. 1007 this->thread[tid]->syscall(callnum); 1008 1009 // Decrease funcExeInst by one as the normal commit will handle 1010 // incrementing it. 1011 --(this->thread[tid]->funcExeInst); 1012} 1013 1014template <class Impl> 1015void 1016FullO3CPU<Impl>::setSyscallReturn(SyscallReturn return_value, int tid) 1017{ 1018 TheISA::setSyscallReturn(return_value, this->tcBase(tid)); 1019} 1020 1021#endif 1022 1023template <class Impl> 1024void 1025FullO3CPU<Impl>::serialize(std::ostream &os) 1026{ 1027 SimObject::State so_state = SimObject::getState(); 1028 SERIALIZE_ENUM(so_state); 1029 BaseCPU::serialize(os); 1030 nameOut(os, csprintf("%s.tickEvent", name())); 1031 tickEvent.serialize(os); 1032 1033 // Use SimpleThread's ability to checkpoint to make it easier to 1034 // write out the registers. Also make this static so it doesn't 1035 // get instantiated multiple times (causes a panic in statistics). 1036 static SimpleThread temp; 1037 1038 for (int i = 0; i < thread.size(); i++) { 1039 nameOut(os, csprintf("%s.xc.%i", name(), i)); 1040 temp.copyTC(thread[i]->getTC()); 1041 temp.serialize(os); 1042 } 1043} 1044 1045template <class Impl> 1046void 1047FullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion) 1048{ 1049 SimObject::State so_state; 1050 UNSERIALIZE_ENUM(so_state); 1051 BaseCPU::unserialize(cp, section); 1052 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 1053 1054 // Use SimpleThread's ability to checkpoint to make it easier to 1055 // read in the registers. Also make this static so it doesn't 1056 // get instantiated multiple times (causes a panic in statistics). 1057 static SimpleThread temp; 1058 1059 for (int i = 0; i < thread.size(); i++) { 1060 temp.copyTC(thread[i]->getTC()); 1061 temp.unserialize(cp, csprintf("%s.xc.%i", section, i)); 1062 thread[i]->getTC()->copyArchRegs(temp.getTC()); 1063 } 1064} 1065 1066template <class Impl> 1067unsigned int 1068FullO3CPU<Impl>::drain(Event *drain_event) 1069{ 1070 DPRINTF(O3CPU, "Switching out\n"); 1071 1072 // If the CPU isn't doing anything, then return immediately. 1073 if (_status == Idle || _status == SwitchedOut) { 1074 return 0; 1075 } 1076 1077 drainCount = 0; 1078 fetch.drain(); 1079 decode.drain(); 1080 rename.drain(); 1081 iew.drain(); 1082 commit.drain(); 1083 1084 // Wake the CPU and record activity so everything can drain out if 1085 // the CPU was not able to immediately drain. 1086 if (getState() != SimObject::Drained) { 1087 // A bit of a hack...set the drainEvent after all the drain() 1088 // calls have been made, that way if all of the stages drain 1089 // immediately, the signalDrained() function knows not to call 1090 // process on the drain event. 1091 drainEvent = drain_event; 1092 1093 wakeCPU(); 1094 activityRec.activity(); 1095 1096 return 1; 1097 } else { 1098 return 0; 1099 } 1100} 1101 1102template <class Impl> 1103void 1104FullO3CPU<Impl>::resume() 1105{ 1106 fetch.resume(); 1107 decode.resume(); 1108 rename.resume(); 1109 iew.resume(); 1110 commit.resume(); 1111 1112 changeState(SimObject::Running); 1113 1114 if (_status == SwitchedOut || _status == Idle) 1115 return; 1116 1117#if FULL_SYSTEM 1118 assert(system->getMemoryMode() == Enums::timing); 1119#endif 1120 1121 if (!tickEvent.scheduled()) 1122 schedule(tickEvent, nextCycle()); 1123 _status = Running; 1124} 1125 1126template <class Impl> 1127void 1128FullO3CPU<Impl>::signalDrained() 1129{ 1130 if (++drainCount == NumStages) { 1131 if (tickEvent.scheduled()) 1132 tickEvent.squash(); 1133 1134 changeState(SimObject::Drained); 1135 1136 BaseCPU::switchOut(); 1137 1138 if (drainEvent) { 1139 drainEvent->process(); 1140 drainEvent = NULL; 1141 } 1142 } 1143 assert(drainCount <= 5); 1144} 1145 1146template <class Impl> 1147void 1148FullO3CPU<Impl>::switchOut() 1149{ 1150 fetch.switchOut(); 1151 rename.switchOut(); 1152 iew.switchOut(); 1153 commit.switchOut(); 1154 instList.clear(); 1155 while (!removeList.empty()) { 1156 removeList.pop(); 1157 } 1158 1159 _status = SwitchedOut; 1160#if USE_CHECKER 1161 if (checker) 1162 checker->switchOut(); 1163#endif 1164 if (tickEvent.scheduled()) 1165 tickEvent.squash(); 1166} 1167 1168template <class Impl> 1169void 1170FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 1171{ 1172 // Flush out any old data from the time buffers. 1173 for (int i = 0; i < timeBuffer.getSize(); ++i) { 1174 timeBuffer.advance(); 1175 fetchQueue.advance(); 1176 decodeQueue.advance(); 1177 renameQueue.advance(); 1178 iewQueue.advance(); 1179 } 1180 1181 activityRec.reset(); 1182 1183 BaseCPU::takeOverFrom(oldCPU, fetch.getIcachePort(), iew.getDcachePort()); 1184 1185 fetch.takeOverFrom(); 1186 decode.takeOverFrom(); 1187 rename.takeOverFrom(); 1188 iew.takeOverFrom(); 1189 commit.takeOverFrom(); 1190 1191 assert(!tickEvent.scheduled()); 1192 1193 // @todo: Figure out how to properly select the tid to put onto 1194 // the active threads list. 1195 int tid = 0; 1196 1197 std::list<unsigned>::iterator isActive = 1198 std::find(activeThreads.begin(), activeThreads.end(), tid); 1199 1200 if (isActive == activeThreads.end()) { 1201 //May Need to Re-code this if the delay variable is the delay 1202 //needed for thread to activate 1203 DPRINTF(O3CPU, "Adding Thread %i to active threads list\n", 1204 tid); 1205 1206 activeThreads.push_back(tid); 1207 } 1208 1209 // Set all statuses to active, schedule the CPU's tick event. 1210 // @todo: Fix up statuses so this is handled properly 1211 for (int i = 0; i < threadContexts.size(); ++i) { 1212 ThreadContext *tc = threadContexts[i]; 1213 if (tc->status() == ThreadContext::Active && _status != Running) { 1214 _status = Running; 1215 schedule(tickEvent, nextCycle()); 1216 } 1217 } 1218 if (!tickEvent.scheduled()) 1219 schedule(tickEvent, nextCycle()); 1220} 1221 1222template <class Impl> 1223TheISA::MiscReg 1224FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, unsigned tid) 1225{ 1226 return this->regFile.readMiscRegNoEffect(misc_reg, tid); 1227} 1228 1229template <class Impl> 1230TheISA::MiscReg 1231FullO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid) 1232{ 1233 return this->regFile.readMiscReg(misc_reg, tid); 1234} 1235 1236template <class Impl> 1237void 1238FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, 1239 const TheISA::MiscReg &val, unsigned tid) 1240{ 1241 this->regFile.setMiscRegNoEffect(misc_reg, val, tid); 1242} 1243 1244template <class Impl> 1245void 1246FullO3CPU<Impl>::setMiscReg(int misc_reg, 1247 const TheISA::MiscReg &val, unsigned tid) 1248{ 1249 this->regFile.setMiscReg(misc_reg, val, tid); 1250} 1251 1252template <class Impl> 1253uint64_t 1254FullO3CPU<Impl>::readIntReg(int reg_idx) 1255{ 1256 return regFile.readIntReg(reg_idx); 1257} 1258 1259template <class Impl> 1260FloatReg 1261FullO3CPU<Impl>::readFloatReg(int reg_idx, int width) 1262{ 1263 return regFile.readFloatReg(reg_idx, width); 1264} 1265 1266template <class Impl> 1267FloatReg 1268FullO3CPU<Impl>::readFloatReg(int reg_idx) 1269{ 1270 return regFile.readFloatReg(reg_idx); 1271} 1272 1273template <class Impl> 1274FloatRegBits 1275FullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width) 1276{ 1277 return regFile.readFloatRegBits(reg_idx, width); 1278} 1279 1280template <class Impl> 1281FloatRegBits 1282FullO3CPU<Impl>::readFloatRegBits(int reg_idx) 1283{ 1284 return regFile.readFloatRegBits(reg_idx); 1285} 1286 1287template <class Impl> 1288void 1289FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 1290{ 1291 regFile.setIntReg(reg_idx, val); 1292} 1293 1294template <class Impl> 1295void 1296FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width) 1297{ 1298 regFile.setFloatReg(reg_idx, val, width); 1299} 1300 1301template <class Impl> 1302void 1303FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 1304{ 1305 regFile.setFloatReg(reg_idx, val); 1306} 1307 1308template <class Impl> 1309void 1310FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width) 1311{ 1312 regFile.setFloatRegBits(reg_idx, val, width); 1313} 1314 1315template <class Impl> 1316void 1317FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 1318{ 1319 regFile.setFloatRegBits(reg_idx, val); 1320} 1321 1322template <class Impl> 1323uint64_t 1324FullO3CPU<Impl>::readArchIntReg(int reg_idx, unsigned tid) 1325{ 1326 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 1327 1328 return regFile.readIntReg(phys_reg); 1329} 1330 1331template <class Impl> 1332float 1333FullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, unsigned tid) 1334{ 1335 int idx = reg_idx + TheISA::FP_Base_DepTag; 1336 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 1337 1338 return regFile.readFloatReg(phys_reg); 1339} 1340 1341template <class Impl> 1342double 1343FullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, unsigned tid) 1344{ 1345 int idx = reg_idx + TheISA::FP_Base_DepTag; 1346 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 1347 1348 return regFile.readFloatReg(phys_reg, 64); 1349} 1350 1351template <class Impl> 1352uint64_t 1353FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, unsigned tid) 1354{ 1355 int idx = reg_idx + TheISA::FP_Base_DepTag; 1356 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 1357 1358 return regFile.readFloatRegBits(phys_reg); 1359} 1360 1361template <class Impl> 1362void 1363FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, unsigned tid) 1364{ 1365 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 1366 1367 regFile.setIntReg(phys_reg, val); 1368} 1369 1370template <class Impl> 1371void 1372FullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, unsigned tid) 1373{ 1374 int idx = reg_idx + TheISA::FP_Base_DepTag; 1375 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 1376 1377 regFile.setFloatReg(phys_reg, val); 1378} 1379 1380template <class Impl> 1381void 1382FullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, unsigned tid) 1383{ 1384 int idx = reg_idx + TheISA::FP_Base_DepTag; 1385 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 1386 1387 regFile.setFloatReg(phys_reg, val, 64); 1388} 1389 1390template <class Impl> 1391void 1392FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid) 1393{ 1394 int idx = reg_idx + TheISA::FP_Base_DepTag; 1395 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 1396 1397 regFile.setFloatRegBits(phys_reg, val); 1398} 1399 1400template <class Impl> 1401uint64_t 1402FullO3CPU<Impl>::readPC(unsigned tid) 1403{ 1404 return commit.readPC(tid); 1405} 1406 1407template <class Impl> 1408void 1409FullO3CPU<Impl>::setPC(Addr new_PC,unsigned tid) 1410{ 1411 commit.setPC(new_PC, tid); 1412} 1413 1414template <class Impl> 1415uint64_t 1416FullO3CPU<Impl>::readMicroPC(unsigned tid) 1417{ 1418 return commit.readMicroPC(tid); 1419} 1420 1421template <class Impl> 1422void 1423FullO3CPU<Impl>::setMicroPC(Addr new_PC,unsigned tid) 1424{ 1425 commit.setMicroPC(new_PC, tid); 1426} 1427 1428template <class Impl> 1429uint64_t 1430FullO3CPU<Impl>::readNextPC(unsigned tid) 1431{ 1432 return commit.readNextPC(tid); 1433} 1434 1435template <class Impl> 1436void 1437FullO3CPU<Impl>::setNextPC(uint64_t val,unsigned tid) 1438{ 1439 commit.setNextPC(val, tid); 1440} 1441 1442template <class Impl> 1443uint64_t 1444FullO3CPU<Impl>::readNextNPC(unsigned tid) 1445{ 1446 return commit.readNextNPC(tid); 1447} 1448 1449template <class Impl> 1450void 1451FullO3CPU<Impl>::setNextNPC(uint64_t val,unsigned tid) 1452{ 1453 commit.setNextNPC(val, tid); 1454} 1455 1456template <class Impl> 1457uint64_t 1458FullO3CPU<Impl>::readNextMicroPC(unsigned tid) 1459{ 1460 return commit.readNextMicroPC(tid); 1461} 1462 1463template <class Impl> 1464void 1465FullO3CPU<Impl>::setNextMicroPC(Addr new_PC,unsigned tid) 1466{ 1467 commit.setNextMicroPC(new_PC, tid); 1468} 1469 1470template <class Impl> 1471void 1472FullO3CPU<Impl>::squashFromTC(unsigned tid) 1473{ 1474 this->thread[tid]->inSyscall = true; 1475 this->commit.generateTCEvent(tid); 1476} 1477 1478template <class Impl> 1479typename FullO3CPU<Impl>::ListIt 1480FullO3CPU<Impl>::addInst(DynInstPtr &inst) 1481{ 1482 instList.push_back(inst); 1483 1484 return --(instList.end()); 1485} 1486 1487template <class Impl> 1488void 1489FullO3CPU<Impl>::instDone(unsigned tid) 1490{ 1491 // Keep an instruction count. 1492 thread[tid]->numInst++; 1493 thread[tid]->numInsts++; 1494 committedInsts[tid]++; 1495 totalCommittedInsts++; 1496 1497 // Check for instruction-count-based events. 1498 comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 1499} 1500 1501template <class Impl> 1502void 1503FullO3CPU<Impl>::addToRemoveList(DynInstPtr &inst) 1504{ 1505 removeInstsThisCycle = true; 1506 1507 removeList.push(inst->getInstListIt()); 1508} 1509 1510template <class Impl> 1511void 1512FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 1513{ 1514 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %#x " 1515 "[sn:%lli]\n", 1516 inst->threadNumber, inst->readPC(), inst->seqNum); 1517 1518 removeInstsThisCycle = true; 1519 1520 // Remove the front instruction. 1521 removeList.push(inst->getInstListIt()); 1522} 1523 1524template <class Impl> 1525void 1526FullO3CPU<Impl>::removeInstsNotInROB(unsigned tid) 1527{ 1528 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 1529 " list.\n", tid); 1530 1531 ListIt end_it; 1532 1533 bool rob_empty = false; 1534 1535 if (instList.empty()) { 1536 return; 1537 } else if (rob.isEmpty(/*tid*/)) { 1538 DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 1539 end_it = instList.begin(); 1540 rob_empty = true; 1541 } else { 1542 end_it = (rob.readTailInst(tid))->getInstListIt(); 1543 DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 1544 } 1545 1546 removeInstsThisCycle = true; 1547 1548 ListIt inst_it = instList.end(); 1549 1550 inst_it--; 1551 1552 // Walk through the instruction list, removing any instructions 1553 // that were inserted after the given instruction iterator, end_it. 1554 while (inst_it != end_it) { 1555 assert(!instList.empty()); 1556 1557 squashInstIt(inst_it, tid); 1558 1559 inst_it--; 1560 } 1561 1562 // If the ROB was empty, then we actually need to remove the first 1563 // instruction as well. 1564 if (rob_empty) { 1565 squashInstIt(inst_it, tid); 1566 } 1567} 1568 1569template <class Impl> 1570void 1571FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, 1572 unsigned tid) 1573{ 1574 assert(!instList.empty()); 1575 1576 removeInstsThisCycle = true; 1577 1578 ListIt inst_iter = instList.end(); 1579 1580 inst_iter--; 1581 1582 DPRINTF(O3CPU, "Deleting instructions from instruction " 1583 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 1584 tid, seq_num, (*inst_iter)->seqNum); 1585 1586 while ((*inst_iter)->seqNum > seq_num) { 1587 1588 bool break_loop = (inst_iter == instList.begin()); 1589 1590 squashInstIt(inst_iter, tid); 1591 1592 inst_iter--; 1593 1594 if (break_loop) 1595 break; 1596 } 1597} 1598 1599template <class Impl> 1600inline void 1601FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, const unsigned &tid) 1602{ 1603 if ((*instIt)->threadNumber == tid) { 1604 DPRINTF(O3CPU, "Squashing instruction, " 1605 "[tid:%i] [sn:%lli] PC %#x\n", 1606 (*instIt)->threadNumber, 1607 (*instIt)->seqNum, 1608 (*instIt)->readPC()); 1609 1610 // Mark it as squashed. 1611 (*instIt)->setSquashed(); 1612 1613 // @todo: Formulate a consistent method for deleting 1614 // instructions from the instruction list 1615 // Remove the instruction from the list. 1616 removeList.push(instIt); 1617 } 1618} 1619 1620template <class Impl> 1621void 1622FullO3CPU<Impl>::cleanUpRemovedInsts() 1623{ 1624 while (!removeList.empty()) { 1625 DPRINTF(O3CPU, "Removing instruction, " 1626 "[tid:%i] [sn:%lli] PC %#x\n", 1627 (*removeList.front())->threadNumber, 1628 (*removeList.front())->seqNum, 1629 (*removeList.front())->readPC()); 1630 1631 instList.erase(removeList.front()); 1632 1633 removeList.pop(); 1634 } 1635 1636 removeInstsThisCycle = false; 1637} 1638/* 1639template <class Impl> 1640void 1641FullO3CPU<Impl>::removeAllInsts() 1642{ 1643 instList.clear(); 1644} 1645*/ 1646template <class Impl> 1647void 1648FullO3CPU<Impl>::dumpInsts() 1649{ 1650 int num = 0; 1651 1652 ListIt inst_list_it = instList.begin(); 1653 1654 cprintf("Dumping Instruction List\n"); 1655 1656 while (inst_list_it != instList.end()) { 1657 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 1658 "Squashed:%i\n\n", 1659 num, (*inst_list_it)->readPC(), (*inst_list_it)->threadNumber, 1660 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 1661 (*inst_list_it)->isSquashed()); 1662 inst_list_it++; 1663 ++num; 1664 } 1665} 1666/* 1667template <class Impl> 1668void 1669FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 1670{ 1671 iew.wakeDependents(inst); 1672} 1673*/ 1674template <class Impl> 1675void 1676FullO3CPU<Impl>::wakeCPU() 1677{ 1678 if (activityRec.active() || tickEvent.scheduled()) { 1679 DPRINTF(Activity, "CPU already running.\n"); 1680 return; 1681 } 1682 1683 DPRINTF(Activity, "Waking up CPU\n"); 1684 1685 idleCycles += tickToCycles((curTick - 1) - lastRunningCycle); 1686 numCycles += tickToCycles((curTick - 1) - lastRunningCycle); 1687 1688 schedule(tickEvent, nextCycle()); 1689} 1690 1691template <class Impl> 1692int 1693FullO3CPU<Impl>::getFreeTid() 1694{ 1695 for (int i=0; i < numThreads; i++) { 1696 if (!tids[i]) { 1697 tids[i] = true; 1698 return i; 1699 } 1700 } 1701 1702 return -1; 1703} 1704 1705template <class Impl> 1706void 1707FullO3CPU<Impl>::doContextSwitch() 1708{ 1709 if (contextSwitch) { 1710 1711 //ADD CODE TO DEACTIVE THREAD HERE (???) 1712 1713 for (int tid=0; tid < cpuWaitList.size(); tid++) { 1714 activateWhenReady(tid); 1715 } 1716 1717 if (cpuWaitList.size() == 0) 1718 contextSwitch = true; 1719 } 1720} 1721 1722template <class Impl> 1723void 1724FullO3CPU<Impl>::updateThreadPriority() 1725{ 1726 if (activeThreads.size() > 1) 1727 { 1728 //DEFAULT TO ROUND ROBIN SCHEME 1729 //e.g. Move highest priority to end of thread list 1730 std::list<unsigned>::iterator list_begin = activeThreads.begin(); 1731 std::list<unsigned>::iterator list_end = activeThreads.end(); 1732 1733 unsigned high_thread = *list_begin; 1734 1735 activeThreads.erase(list_begin); 1736 1737 activeThreads.push_back(high_thread); 1738 } 1739} 1740 1741// Forward declaration of FullO3CPU. 1742template class FullO3CPU<O3CPUImpl>;
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