1/*
2 * Copyright (c) 2011-2012, 2014 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * Copyright (c) 2011 Regents of the University of California
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Kevin Lim
43 * Korey Sewell
44 * Rick Strong
45 */
46
47#include "arch/kernel_stats.hh"
48#include "config/the_isa.hh"
49#include "cpu/checker/cpu.hh"
50#include "cpu/checker/thread_context.hh"
51#include "cpu/o3/cpu.hh"
52#include "cpu/o3/isa_specific.hh"
53#include "cpu/o3/thread_context.hh"
54#include "cpu/activity.hh"
55#include "cpu/quiesce_event.hh"
56#include "cpu/simple_thread.hh"
57#include "cpu/thread_context.hh"
58#include "debug/Activity.hh"
59#include "debug/Drain.hh"
60#include "debug/O3CPU.hh"
61#include "debug/Quiesce.hh"
62#include "enums/MemoryMode.hh"
63#include "sim/core.hh"
64#include "sim/full_system.hh"
65#include "sim/process.hh"
66#include "sim/stat_control.hh"
67#include "sim/system.hh"
68
69#if THE_ISA == ALPHA_ISA
70#include "arch/alpha/osfpal.hh"
71#include "debug/Activity.hh"
72#endif
73
74struct BaseCPUParams;
75
76using namespace TheISA;
77using namespace std;
78
79BaseO3CPU::BaseO3CPU(BaseCPUParams *params)
80 : BaseCPU(params)
81{
82}
83
84void
85BaseO3CPU::regStats()
86{
87 BaseCPU::regStats();
88}
89
90template<class Impl>
91bool
92FullO3CPU<Impl>::IcachePort::recvTimingResp(PacketPtr pkt)
93{
94 DPRINTF(O3CPU, "Fetch unit received timing\n");
95 // We shouldn't ever get a cacheable block in ownership state
96 assert(pkt->req->isUncacheable() ||
97 !(pkt->memInhibitAsserted() && !pkt->sharedAsserted()));
98 fetch->processCacheCompletion(pkt);
99
100 return true;
101}
102
103template<class Impl>
104void
105FullO3CPU<Impl>::IcachePort::recvReqRetry()
106{
107 fetch->recvReqRetry();
108}
109
110template <class Impl>
111bool
112FullO3CPU<Impl>::DcachePort::recvTimingResp(PacketPtr pkt)
113{
114 return lsq->recvTimingResp(pkt);
115}
116
117template <class Impl>
118void
119FullO3CPU<Impl>::DcachePort::recvTimingSnoopReq(PacketPtr pkt)
120{
121 // X86 ISA: Snooping an invalidation for monitor/mwait
122 if(cpu->getCpuAddrMonitor()->doMonitor(pkt)) {
123 cpu->wakeup();
124 }
125 lsq->recvTimingSnoopReq(pkt);
126}
127
128template <class Impl>
129void
130FullO3CPU<Impl>::DcachePort::recvReqRetry()
131{
132 lsq->recvReqRetry();
133}
134
135template <class Impl>
136FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
137 : Event(CPU_Tick_Pri), cpu(c)
138{
139}
140
141template <class Impl>
142void
143FullO3CPU<Impl>::TickEvent::process()
144{
145 cpu->tick();
146}
147
148template <class Impl>
149const char *
150FullO3CPU<Impl>::TickEvent::description() const
151{
152 return "FullO3CPU tick";
153}
154
155template <class Impl>
156FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
157 : BaseO3CPU(params),
158 itb(params->itb),
159 dtb(params->dtb),
160 tickEvent(this),
161#ifndef NDEBUG
162 instcount(0),
163#endif
164 removeInstsThisCycle(false),
165 fetch(this, params),
166 decode(this, params),
167 rename(this, params),
168 iew(this, params),
169 commit(this, params),
170
171 regFile(params->numPhysIntRegs,
172 params->numPhysFloatRegs,
|
173 params->numPhysCCRegs,
174 params->numPhysVectorRegs),
|
| 173 params->numPhysCCRegs), |
174
175 freeList(name() + ".freelist", ®File),
176
177 rob(this, params),
178
179 scoreboard(name() + ".scoreboard",
180 regFile.totalNumPhysRegs(), TheISA::NumMiscRegs,
181 TheISA::ZeroReg, TheISA::ZeroReg),
182
183 isa(numThreads, NULL),
184
185 icachePort(&fetch, this),
186 dcachePort(&iew.ldstQueue, this),
187
188 timeBuffer(params->backComSize, params->forwardComSize),
189 fetchQueue(params->backComSize, params->forwardComSize),
190 decodeQueue(params->backComSize, params->forwardComSize),
191 renameQueue(params->backComSize, params->forwardComSize),
192 iewQueue(params->backComSize, params->forwardComSize),
193 activityRec(name(), NumStages,
194 params->backComSize + params->forwardComSize,
195 params->activity),
196
197 globalSeqNum(1),
198 system(params->system),
199 lastRunningCycle(curCycle())
200{
201 if (!params->switched_out) {
202 _status = Running;
203 } else {
204 _status = SwitchedOut;
205 }
206
207 if (params->checker) {
208 BaseCPU *temp_checker = params->checker;
209 checker = dynamic_cast<Checker<Impl> *>(temp_checker);
210 checker->setIcachePort(&icachePort);
211 checker->setSystem(params->system);
212 } else {
213 checker = NULL;
214 }
215
216 if (!FullSystem) {
217 thread.resize(numThreads);
218 tids.resize(numThreads);
219 }
220
221 // The stages also need their CPU pointer setup. However this
222 // must be done at the upper level CPU because they have pointers
223 // to the upper level CPU, and not this FullO3CPU.
224
225 // Set up Pointers to the activeThreads list for each stage
226 fetch.setActiveThreads(&activeThreads);
227 decode.setActiveThreads(&activeThreads);
228 rename.setActiveThreads(&activeThreads);
229 iew.setActiveThreads(&activeThreads);
230 commit.setActiveThreads(&activeThreads);
231
232 // Give each of the stages the time buffer they will use.
233 fetch.setTimeBuffer(&timeBuffer);
234 decode.setTimeBuffer(&timeBuffer);
235 rename.setTimeBuffer(&timeBuffer);
236 iew.setTimeBuffer(&timeBuffer);
237 commit.setTimeBuffer(&timeBuffer);
238
239 // Also setup each of the stages' queues.
240 fetch.setFetchQueue(&fetchQueue);
241 decode.setFetchQueue(&fetchQueue);
242 commit.setFetchQueue(&fetchQueue);
243 decode.setDecodeQueue(&decodeQueue);
244 rename.setDecodeQueue(&decodeQueue);
245 rename.setRenameQueue(&renameQueue);
246 iew.setRenameQueue(&renameQueue);
247 iew.setIEWQueue(&iewQueue);
248 commit.setIEWQueue(&iewQueue);
249 commit.setRenameQueue(&renameQueue);
250
251 commit.setIEWStage(&iew);
252 rename.setIEWStage(&iew);
253 rename.setCommitStage(&commit);
254
255 ThreadID active_threads;
256 if (FullSystem) {
257 active_threads = 1;
258 } else {
259 active_threads = params->workload.size();
260
261 if (active_threads > Impl::MaxThreads) {
262 panic("Workload Size too large. Increase the 'MaxThreads' "
263 "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) "
264 "or edit your workload size.");
265 }
266 }
267
268 //Make Sure That this a Valid Architeture
269 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs);
270 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
271 assert(params->numPhysCCRegs >= numThreads * TheISA::NumCCRegs);
|
273 assert(params->numPhysVectorRegs >= numThreads * TheISA::NumVectorRegs);
|
272
273 rename.setScoreboard(&scoreboard);
274 iew.setScoreboard(&scoreboard);
275
276 // Setup the rename map for whichever stages need it.
277 for (ThreadID tid = 0; tid < numThreads; tid++) {
278 isa[tid] = params->isa[tid];
279
280 // Only Alpha has an FP zero register, so for other ISAs we
281 // use an invalid FP register index to avoid special treatment
282 // of any valid FP reg.
283 RegIndex invalidFPReg = TheISA::NumFloatRegs + 1;
284 RegIndex fpZeroReg =
285 (THE_ISA == ALPHA_ISA) ? TheISA::ZeroReg : invalidFPReg;
286
287 commitRenameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg,
288 &freeList);
289
290 renameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg,
291 &freeList);
292 }
293
294 // Initialize rename map to assign physical registers to the
295 // architectural registers for active threads only.
296 for (ThreadID tid = 0; tid < active_threads; tid++) {
297 for (RegIndex ridx = 0; ridx < TheISA::NumIntRegs; ++ridx) {
298 // Note that we can't use the rename() method because we don't
299 // want special treatment for the zero register at this point
300 PhysRegIndex phys_reg = freeList.getIntReg();
301 renameMap[tid].setIntEntry(ridx, phys_reg);
302 commitRenameMap[tid].setIntEntry(ridx, phys_reg);
303 }
304
305 for (RegIndex ridx = 0; ridx < TheISA::NumFloatRegs; ++ridx) {
306 PhysRegIndex phys_reg = freeList.getFloatReg();
307 renameMap[tid].setFloatEntry(ridx, phys_reg);
308 commitRenameMap[tid].setFloatEntry(ridx, phys_reg);
309 }
310
311 for (RegIndex ridx = 0; ridx < TheISA::NumCCRegs; ++ridx) {
312 PhysRegIndex phys_reg = freeList.getCCReg();
313 renameMap[tid].setCCEntry(ridx, phys_reg);
314 commitRenameMap[tid].setCCEntry(ridx, phys_reg);
315 }
|
318
319 for (RegIndex ridx = 0; ridx < TheISA::NumVectorRegs; ++ridx) {
320 PhysRegIndex phys_reg = freeList.getVectorReg();
321 renameMap[tid].setVectorEntry(ridx, phys_reg);
322 commitRenameMap[tid].setVectorEntry(ridx, phys_reg);
323 }
|
316 }
317
318 rename.setRenameMap(renameMap);
319 commit.setRenameMap(commitRenameMap);
320 rename.setFreeList(&freeList);
321
322 // Setup the ROB for whichever stages need it.
323 commit.setROB(&rob);
324
325 lastActivatedCycle = 0;
326#if 0
327 // Give renameMap & rename stage access to the freeList;
328 for (ThreadID tid = 0; tid < numThreads; tid++)
329 globalSeqNum[tid] = 1;
330#endif
331
332 DPRINTF(O3CPU, "Creating O3CPU object.\n");
333
334 // Setup any thread state.
335 this->thread.resize(this->numThreads);
336
337 for (ThreadID tid = 0; tid < this->numThreads; ++tid) {
338 if (FullSystem) {
339 // SMT is not supported in FS mode yet.
340 assert(this->numThreads == 1);
341 this->thread[tid] = new Thread(this, 0, NULL);
342 } else {
343 if (tid < params->workload.size()) {
344 DPRINTF(O3CPU, "Workload[%i] process is %#x",
345 tid, this->thread[tid]);
346 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
347 (typename Impl::O3CPU *)(this),
348 tid, params->workload[tid]);
349
350 //usedTids[tid] = true;
351 //threadMap[tid] = tid;
352 } else {
353 //Allocate Empty thread so M5 can use later
354 //when scheduling threads to CPU
355 Process* dummy_proc = NULL;
356
357 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
358 (typename Impl::O3CPU *)(this),
359 tid, dummy_proc);
360 //usedTids[tid] = false;
361 }
362 }
363
364 ThreadContext *tc;
365
366 // Setup the TC that will serve as the interface to the threads/CPU.
367 O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>;
368
369 tc = o3_tc;
370
371 // If we're using a checker, then the TC should be the
372 // CheckerThreadContext.
373 if (params->checker) {
374 tc = new CheckerThreadContext<O3ThreadContext<Impl> >(
375 o3_tc, this->checker);
376 }
377
378 o3_tc->cpu = (typename Impl::O3CPU *)(this);
379 assert(o3_tc->cpu);
380 o3_tc->thread = this->thread[tid];
381
382 if (FullSystem) {
383 // Setup quiesce event.
384 this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
385 }
386 // Give the thread the TC.
387 this->thread[tid]->tc = tc;
388
389 // Add the TC to the CPU's list of TC's.
390 this->threadContexts.push_back(tc);
391 }
392
393 // FullO3CPU always requires an interrupt controller.
394 if (!params->switched_out && !interrupts) {
395 fatal("FullO3CPU %s has no interrupt controller.\n"
396 "Ensure createInterruptController() is called.\n", name());
397 }
398
399 for (ThreadID tid = 0; tid < this->numThreads; tid++)
400 this->thread[tid]->setFuncExeInst(0);
401}
402
403template <class Impl>
404FullO3CPU<Impl>::~FullO3CPU()
405{
406}
407
408template <class Impl>
409void
410FullO3CPU<Impl>::regProbePoints()
411{
412 BaseCPU::regProbePoints();
413
414 ppInstAccessComplete = new ProbePointArg<PacketPtr>(getProbeManager(), "InstAccessComplete");
415 ppDataAccessComplete = new ProbePointArg<std::pair<DynInstPtr, PacketPtr> >(getProbeManager(), "DataAccessComplete");
416
417 fetch.regProbePoints();
418 iew.regProbePoints();
419 commit.regProbePoints();
420}
421
422template <class Impl>
423void
424FullO3CPU<Impl>::regStats()
425{
426 BaseO3CPU::regStats();
427
428 // Register any of the O3CPU's stats here.
429 timesIdled
430 .name(name() + ".timesIdled")
431 .desc("Number of times that the entire CPU went into an idle state and"
432 " unscheduled itself")
433 .prereq(timesIdled);
434
435 idleCycles
436 .name(name() + ".idleCycles")
437 .desc("Total number of cycles that the CPU has spent unscheduled due "
438 "to idling")
439 .prereq(idleCycles);
440
441 quiesceCycles
442 .name(name() + ".quiesceCycles")
443 .desc("Total number of cycles that CPU has spent quiesced or waiting "
444 "for an interrupt")
445 .prereq(quiesceCycles);
446
447 // Number of Instructions simulated
448 // --------------------------------
449 // Should probably be in Base CPU but need templated
450 // MaxThreads so put in here instead
451 committedInsts
452 .init(numThreads)
453 .name(name() + ".committedInsts")
454 .desc("Number of Instructions Simulated")
455 .flags(Stats::total);
456
457 committedOps
458 .init(numThreads)
459 .name(name() + ".committedOps")
460 .desc("Number of Ops (including micro ops) Simulated")
461 .flags(Stats::total);
462
463 cpi
464 .name(name() + ".cpi")
465 .desc("CPI: Cycles Per Instruction")
466 .precision(6);
467 cpi = numCycles / committedInsts;
468
469 totalCpi
470 .name(name() + ".cpi_total")
471 .desc("CPI: Total CPI of All Threads")
472 .precision(6);
473 totalCpi = numCycles / sum(committedInsts);
474
475 ipc
476 .name(name() + ".ipc")
477 .desc("IPC: Instructions Per Cycle")
478 .precision(6);
479 ipc = committedInsts / numCycles;
480
481 totalIpc
482 .name(name() + ".ipc_total")
483 .desc("IPC: Total IPC of All Threads")
484 .precision(6);
485 totalIpc = sum(committedInsts) / numCycles;
486
487 this->fetch.regStats();
488 this->decode.regStats();
489 this->rename.regStats();
490 this->iew.regStats();
491 this->commit.regStats();
492 this->rob.regStats();
493
494 intRegfileReads
495 .name(name() + ".int_regfile_reads")
496 .desc("number of integer regfile reads")
497 .prereq(intRegfileReads);
498
499 intRegfileWrites
500 .name(name() + ".int_regfile_writes")
501 .desc("number of integer regfile writes")
502 .prereq(intRegfileWrites);
503
504 fpRegfileReads
505 .name(name() + ".fp_regfile_reads")
506 .desc("number of floating regfile reads")
507 .prereq(fpRegfileReads);
508
509 fpRegfileWrites
510 .name(name() + ".fp_regfile_writes")
511 .desc("number of floating regfile writes")
512 .prereq(fpRegfileWrites);
513
514 ccRegfileReads
515 .name(name() + ".cc_regfile_reads")
516 .desc("number of cc regfile reads")
517 .prereq(ccRegfileReads);
518
519 ccRegfileWrites
520 .name(name() + ".cc_regfile_writes")
521 .desc("number of cc regfile writes")
522 .prereq(ccRegfileWrites);
523
|
532 vectorRegfileReads
533 .name(name() + ".vector_regfile_reads")
534 .desc("number of vector regfile reads")
535 .prereq(vectorRegfileReads);
536
537 vectorRegfileWrites
538 .name(name() + ".vector_regfile_writes")
539 .desc("number of vector regfile writes")
540 .prereq(vectorRegfileWrites);
541
|
524 miscRegfileReads
525 .name(name() + ".misc_regfile_reads")
526 .desc("number of misc regfile reads")
527 .prereq(miscRegfileReads);
528
529 miscRegfileWrites
530 .name(name() + ".misc_regfile_writes")
531 .desc("number of misc regfile writes")
532 .prereq(miscRegfileWrites);
533}
534
535template <class Impl>
536void
537FullO3CPU<Impl>::tick()
538{
539 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
540 assert(!switchedOut());
541 assert(drainState() != DrainState::Drained);
542
543 ++numCycles;
544 ppCycles->notify(1);
545
546// activity = false;
547
548 //Tick each of the stages
549 fetch.tick();
550
551 decode.tick();
552
553 rename.tick();
554
555 iew.tick();
556
557 commit.tick();
558
559 // Now advance the time buffers
560 timeBuffer.advance();
561
562 fetchQueue.advance();
563 decodeQueue.advance();
564 renameQueue.advance();
565 iewQueue.advance();
566
567 activityRec.advance();
568
569 if (removeInstsThisCycle) {
570 cleanUpRemovedInsts();
571 }
572
573 if (!tickEvent.scheduled()) {
574 if (_status == SwitchedOut) {
575 DPRINTF(O3CPU, "Switched out!\n");
576 // increment stat
577 lastRunningCycle = curCycle();
578 } else if (!activityRec.active() || _status == Idle) {
579 DPRINTF(O3CPU, "Idle!\n");
580 lastRunningCycle = curCycle();
581 timesIdled++;
582 } else {
583 schedule(tickEvent, clockEdge(Cycles(1)));
584 DPRINTF(O3CPU, "Scheduling next tick!\n");
585 }
586 }
587
588 if (!FullSystem)
589 updateThreadPriority();
590
591 tryDrain();
592}
593
594template <class Impl>
595void
596FullO3CPU<Impl>::init()
597{
598 BaseCPU::init();
599
600 for (ThreadID tid = 0; tid < numThreads; ++tid) {
601 // Set noSquashFromTC so that the CPU doesn't squash when initially
602 // setting up registers.
603 thread[tid]->noSquashFromTC = true;
604 // Initialise the ThreadContext's memory proxies
605 thread[tid]->initMemProxies(thread[tid]->getTC());
606 }
607
608 if (FullSystem && !params()->switched_out) {
609 for (ThreadID tid = 0; tid < numThreads; tid++) {
610 ThreadContext *src_tc = threadContexts[tid];
611 TheISA::initCPU(src_tc, src_tc->contextId());
612 }
613 }
614
615 // Clear noSquashFromTC.
616 for (int tid = 0; tid < numThreads; ++tid)
617 thread[tid]->noSquashFromTC = false;
618
619 commit.setThreads(thread);
620}
621
622template <class Impl>
623void
624FullO3CPU<Impl>::startup()
625{
626 BaseCPU::startup();
627 for (int tid = 0; tid < numThreads; ++tid)
628 isa[tid]->startup(threadContexts[tid]);
629
630 fetch.startupStage();
631 decode.startupStage();
632 iew.startupStage();
633 rename.startupStage();
634 commit.startupStage();
635}
636
637template <class Impl>
638void
639FullO3CPU<Impl>::activateThread(ThreadID tid)
640{
641 list<ThreadID>::iterator isActive =
642 std::find(activeThreads.begin(), activeThreads.end(), tid);
643
644 DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid);
645 assert(!switchedOut());
646
647 if (isActive == activeThreads.end()) {
648 DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n",
649 tid);
650
651 activeThreads.push_back(tid);
652 }
653}
654
655template <class Impl>
656void
657FullO3CPU<Impl>::deactivateThread(ThreadID tid)
658{
659 //Remove From Active List, if Active
660 list<ThreadID>::iterator thread_it =
661 std::find(activeThreads.begin(), activeThreads.end(), tid);
662
663 DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid);
664 assert(!switchedOut());
665
666 if (thread_it != activeThreads.end()) {
667 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
668 tid);
669 activeThreads.erase(thread_it);
670 }
671
672 fetch.deactivateThread(tid);
673 commit.deactivateThread(tid);
674}
675
676template <class Impl>
677Counter
678FullO3CPU<Impl>::totalInsts() const
679{
680 Counter total(0);
681
682 ThreadID size = thread.size();
683 for (ThreadID i = 0; i < size; i++)
684 total += thread[i]->numInst;
685
686 return total;
687}
688
689template <class Impl>
690Counter
691FullO3CPU<Impl>::totalOps() const
692{
693 Counter total(0);
694
695 ThreadID size = thread.size();
696 for (ThreadID i = 0; i < size; i++)
697 total += thread[i]->numOp;
698
699 return total;
700}
701
702template <class Impl>
703void
704FullO3CPU<Impl>::activateContext(ThreadID tid)
705{
706 assert(!switchedOut());
707
708 // Needs to set each stage to running as well.
709 activateThread(tid);
710
711 // We don't want to wake the CPU if it is drained. In that case,
712 // we just want to flag the thread as active and schedule the tick
713 // event from drainResume() instead.
714 if (drainState() == DrainState::Drained)
715 return;
716
717 // If we are time 0 or if the last activation time is in the past,
718 // schedule the next tick and wake up the fetch unit
719 if (lastActivatedCycle == 0 || lastActivatedCycle < curTick()) {
720 scheduleTickEvent(Cycles(0));
721
722 // Be sure to signal that there's some activity so the CPU doesn't
723 // deschedule itself.
724 activityRec.activity();
725 fetch.wakeFromQuiesce();
726
727 Cycles cycles(curCycle() - lastRunningCycle);
728 // @todo: This is an oddity that is only here to match the stats
729 if (cycles != 0)
730 --cycles;
731 quiesceCycles += cycles;
732
733 lastActivatedCycle = curTick();
734
735 _status = Running;
736 }
737}
738
739template <class Impl>
740void
741FullO3CPU<Impl>::suspendContext(ThreadID tid)
742{
743 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
744 assert(!switchedOut());
745
746 deactivateThread(tid);
747
748 // If this was the last thread then unschedule the tick event.
749 if (activeThreads.size() == 0) {
750 unscheduleTickEvent();
751 lastRunningCycle = curCycle();
752 _status = Idle;
753 }
754
755 DPRINTF(Quiesce, "Suspending Context\n");
756}
757
758template <class Impl>
759void
760FullO3CPU<Impl>::haltContext(ThreadID tid)
761{
762 //For now, this is the same as deallocate
763 DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
764 assert(!switchedOut());
765
766 deactivateThread(tid);
767 removeThread(tid);
768}
769
770template <class Impl>
771void
772FullO3CPU<Impl>::insertThread(ThreadID tid)
773{
774 DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
775 // Will change now that the PC and thread state is internal to the CPU
776 // and not in the ThreadContext.
777 ThreadContext *src_tc;
778 if (FullSystem)
779 src_tc = system->threadContexts[tid];
780 else
781 src_tc = tcBase(tid);
782
783 //Bind Int Regs to Rename Map
784 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
785 PhysRegIndex phys_reg = freeList.getIntReg();
786
787 renameMap[tid].setEntry(ireg,phys_reg);
788 scoreboard.setReg(phys_reg);
789 }
790
791 //Bind Float Regs to Rename Map
792 int max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs;
793 for (int freg = TheISA::NumIntRegs; freg < max_reg; freg++) {
794 PhysRegIndex phys_reg = freeList.getFloatReg();
795
796 renameMap[tid].setEntry(freg,phys_reg);
797 scoreboard.setReg(phys_reg);
798 }
799
800 //Bind condition-code Regs to Rename Map
801 max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs + TheISA::NumCCRegs;
802 for (int creg = TheISA::NumIntRegs + TheISA::NumFloatRegs;
803 creg < max_reg; creg++) {
804 PhysRegIndex phys_reg = freeList.getCCReg();
805
806 renameMap[tid].setEntry(creg,phys_reg);
807 scoreboard.setReg(phys_reg);
808 }
809
|
828 //Bind vector Regs to Rename Map
829 max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs + TheISA::NumCCRegs +
830 TheISA::NumVectorRegs;
831 for (int vreg = TheISA::NumIntRegs + TheISA::NumFloatRegs +
832 TheISA::NumCCRegs;
833 vreg < max_reg; vreg++) {
834 PhysRegIndex phys_reg = freeList.getVectorReg();
835
836 renameMap[tid].setEntry(vreg, phys_reg);
837 scoreboard.setReg(phys_reg);
838 }
839
|
810 //Copy Thread Data Into RegFile
811 //this->copyFromTC(tid);
812
813 //Set PC/NPC/NNPC
814 pcState(src_tc->pcState(), tid);
815
816 src_tc->setStatus(ThreadContext::Active);
817
818 activateContext(tid);
819
820 //Reset ROB/IQ/LSQ Entries
821 commit.rob->resetEntries();
822 iew.resetEntries();
823}
824
825template <class Impl>
826void
827FullO3CPU<Impl>::removeThread(ThreadID tid)
828{
829 DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
830
831 // Copy Thread Data From RegFile
832 // If thread is suspended, it might be re-allocated
833 // this->copyToTC(tid);
834
835
836 // @todo: 2-27-2008: Fix how we free up rename mappings
837 // here to alleviate the case for double-freeing registers
838 // in SMT workloads.
839
840 // Unbind Int Regs from Rename Map
841 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
842 PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
843 scoreboard.unsetReg(phys_reg);
844 freeList.addReg(phys_reg);
845 }
846
847 // Unbind Float Regs from Rename Map
848 int max_reg = TheISA::FP_Reg_Base + TheISA::NumFloatRegs;
849 for (int freg = TheISA::FP_Reg_Base; freg < max_reg; freg++) {
850 PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
851 scoreboard.unsetReg(phys_reg);
852 freeList.addReg(phys_reg);
853 }
854
855 // Unbind condition-code Regs from Rename Map
856 max_reg = TheISA::CC_Reg_Base + TheISA::NumCCRegs;
857 for (int creg = TheISA::CC_Reg_Base; creg < max_reg; creg++) {
858 PhysRegIndex phys_reg = renameMap[tid].lookup(creg);
859 scoreboard.unsetReg(phys_reg);
860 freeList.addReg(phys_reg);
861 }
862
|
893 // Unbind condition-code Regs from Rename Map
894 max_reg = TheISA::Vector_Reg_Base + TheISA::NumVectorRegs;
895 for (int vreg = TheISA::Vector_Reg_Base; vreg < max_reg; vreg++) {
896 PhysRegIndex phys_reg = renameMap[tid].lookup(vreg);
897 scoreboard.unsetReg(phys_reg);
898 freeList.addReg(phys_reg);
899 }
900
|
863 // Squash Throughout Pipeline
864 DynInstPtr inst = commit.rob->readHeadInst(tid);
865 InstSeqNum squash_seq_num = inst->seqNum;
866 fetch.squash(0, squash_seq_num, inst, tid);
867 decode.squash(tid);
868 rename.squash(squash_seq_num, tid);
869 iew.squash(tid);
870 iew.ldstQueue.squash(squash_seq_num, tid);
871 commit.rob->squash(squash_seq_num, tid);
872
873
874 assert(iew.instQueue.getCount(tid) == 0);
875 assert(iew.ldstQueue.getCount(tid) == 0);
876
877 // Reset ROB/IQ/LSQ Entries
878
879 // Commented out for now. This should be possible to do by
880 // telling all the pipeline stages to drain first, and then
881 // checking until the drain completes. Once the pipeline is
882 // drained, call resetEntries(). - 10-09-06 ktlim
883/*
884 if (activeThreads.size() >= 1) {
885 commit.rob->resetEntries();
886 iew.resetEntries();
887 }
888*/
889}
890
891template <class Impl>
892Fault
893FullO3CPU<Impl>::hwrei(ThreadID tid)
894{
895#if THE_ISA == ALPHA_ISA
896 // Need to clear the lock flag upon returning from an interrupt.
897 this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
898
899 this->thread[tid]->kernelStats->hwrei();
900
901 // FIXME: XXX check for interrupts? XXX
902#endif
903 return NoFault;
904}
905
906template <class Impl>
907bool
908FullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid)
909{
910#if THE_ISA == ALPHA_ISA
911 if (this->thread[tid]->kernelStats)
912 this->thread[tid]->kernelStats->callpal(palFunc,
913 this->threadContexts[tid]);
914
915 switch (palFunc) {
916 case PAL::halt:
917 halt();
918 if (--System::numSystemsRunning == 0)
919 exitSimLoop("all cpus halted");
920 break;
921
922 case PAL::bpt:
923 case PAL::bugchk:
924 if (this->system->breakpoint())
925 return false;
926 break;
927 }
928#endif
929 return true;
930}
931
932template <class Impl>
933Fault
934FullO3CPU<Impl>::getInterrupts()
935{
936 // Check if there are any outstanding interrupts
937 return this->interrupts->getInterrupt(this->threadContexts[0]);
938}
939
940template <class Impl>
941void
942FullO3CPU<Impl>::processInterrupts(const Fault &interrupt)
943{
944 // Check for interrupts here. For now can copy the code that
945 // exists within isa_fullsys_traits.hh. Also assume that thread 0
946 // is the one that handles the interrupts.
947 // @todo: Possibly consolidate the interrupt checking code.
948 // @todo: Allow other threads to handle interrupts.
949
950 assert(interrupt != NoFault);
951 this->interrupts->updateIntrInfo(this->threadContexts[0]);
952
953 DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
954 this->trap(interrupt, 0, nullptr);
955}
956
957template <class Impl>
958void
959FullO3CPU<Impl>::trap(const Fault &fault, ThreadID tid,
960 const StaticInstPtr &inst)
961{
962 // Pass the thread's TC into the invoke method.
963 fault->invoke(this->threadContexts[tid], inst);
964}
965
966template <class Impl>
967void
968FullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid)
969{
970 DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid);
971
972 DPRINTF(Activity,"Activity: syscall() called.\n");
973
974 // Temporarily increase this by one to account for the syscall
975 // instruction.
976 ++(this->thread[tid]->funcExeInst);
977
978 // Execute the actual syscall.
979 this->thread[tid]->syscall(callnum);
980
981 // Decrease funcExeInst by one as the normal commit will handle
982 // incrementing it.
983 --(this->thread[tid]->funcExeInst);
984}
985
986template <class Impl>
987void
988FullO3CPU<Impl>::serializeThread(CheckpointOut &cp, ThreadID tid) const
989{
990 thread[tid]->serialize(cp);
991}
992
993template <class Impl>
994void
995FullO3CPU<Impl>::unserializeThread(CheckpointIn &cp, ThreadID tid)
996{
997 thread[tid]->unserialize(cp);
998}
999
1000template <class Impl>
1001DrainState
1002FullO3CPU<Impl>::drain()
1003{
1004 // If the CPU isn't doing anything, then return immediately.
1005 if (switchedOut())
1006 return DrainState::Drained;
1007
1008 DPRINTF(Drain, "Draining...\n");
1009
1010 // We only need to signal a drain to the commit stage as this
1011 // initiates squashing controls the draining. Once the commit
1012 // stage commits an instruction where it is safe to stop, it'll
1013 // squash the rest of the instructions in the pipeline and force
1014 // the fetch stage to stall. The pipeline will be drained once all
1015 // in-flight instructions have retired.
1016 commit.drain();
1017
1018 // Wake the CPU and record activity so everything can drain out if
1019 // the CPU was not able to immediately drain.
1020 if (!isDrained()) {
1021 wakeCPU();
1022 activityRec.activity();
1023
1024 DPRINTF(Drain, "CPU not drained\n");
1025
1026 return DrainState::Draining;
1027 } else {
1028 DPRINTF(Drain, "CPU is already drained\n");
1029 if (tickEvent.scheduled())
1030 deschedule(tickEvent);
1031
1032 // Flush out any old data from the time buffers. In
1033 // particular, there might be some data in flight from the
1034 // fetch stage that isn't visible in any of the CPU buffers we
1035 // test in isDrained().
1036 for (int i = 0; i < timeBuffer.getSize(); ++i) {
1037 timeBuffer.advance();
1038 fetchQueue.advance();
1039 decodeQueue.advance();
1040 renameQueue.advance();
1041 iewQueue.advance();
1042 }
1043
1044 drainSanityCheck();
1045 return DrainState::Drained;
1046 }
1047}
1048
1049template <class Impl>
1050bool
1051FullO3CPU<Impl>::tryDrain()
1052{
1053 if (drainState() != DrainState::Draining || !isDrained())
1054 return false;
1055
1056 if (tickEvent.scheduled())
1057 deschedule(tickEvent);
1058
1059 DPRINTF(Drain, "CPU done draining, processing drain event\n");
1060 signalDrainDone();
1061
1062 return true;
1063}
1064
1065template <class Impl>
1066void
1067FullO3CPU<Impl>::drainSanityCheck() const
1068{
1069 assert(isDrained());
1070 fetch.drainSanityCheck();
1071 decode.drainSanityCheck();
1072 rename.drainSanityCheck();
1073 iew.drainSanityCheck();
1074 commit.drainSanityCheck();
1075}
1076
1077template <class Impl>
1078bool
1079FullO3CPU<Impl>::isDrained() const
1080{
1081 bool drained(true);
1082
1083 if (!instList.empty() || !removeList.empty()) {
1084 DPRINTF(Drain, "Main CPU structures not drained.\n");
1085 drained = false;
1086 }
1087
1088 if (!fetch.isDrained()) {
1089 DPRINTF(Drain, "Fetch not drained.\n");
1090 drained = false;
1091 }
1092
1093 if (!decode.isDrained()) {
1094 DPRINTF(Drain, "Decode not drained.\n");
1095 drained = false;
1096 }
1097
1098 if (!rename.isDrained()) {
1099 DPRINTF(Drain, "Rename not drained.\n");
1100 drained = false;
1101 }
1102
1103 if (!iew.isDrained()) {
1104 DPRINTF(Drain, "IEW not drained.\n");
1105 drained = false;
1106 }
1107
1108 if (!commit.isDrained()) {
1109 DPRINTF(Drain, "Commit not drained.\n");
1110 drained = false;
1111 }
1112
1113 return drained;
1114}
1115
1116template <class Impl>
1117void
1118FullO3CPU<Impl>::commitDrained(ThreadID tid)
1119{
1120 fetch.drainStall(tid);
1121}
1122
1123template <class Impl>
1124void
1125FullO3CPU<Impl>::drainResume()
1126{
1127 if (switchedOut())
1128 return;
1129
1130 DPRINTF(Drain, "Resuming...\n");
1131 verifyMemoryMode();
1132
1133 fetch.drainResume();
1134 commit.drainResume();
1135
1136 _status = Idle;
1137 for (ThreadID i = 0; i < thread.size(); i++) {
1138 if (thread[i]->status() == ThreadContext::Active) {
1139 DPRINTF(Drain, "Activating thread: %i\n", i);
1140 activateThread(i);
1141 _status = Running;
1142 }
1143 }
1144
1145 assert(!tickEvent.scheduled());
1146 if (_status == Running)
1147 schedule(tickEvent, nextCycle());
1148}
1149
1150template <class Impl>
1151void
1152FullO3CPU<Impl>::switchOut()
1153{
1154 DPRINTF(O3CPU, "Switching out\n");
1155 BaseCPU::switchOut();
1156
1157 activityRec.reset();
1158
1159 _status = SwitchedOut;
1160
1161 if (checker)
1162 checker->switchOut();
1163}
1164
1165template <class Impl>
1166void
1167FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
1168{
1169 BaseCPU::takeOverFrom(oldCPU);
1170
1171 fetch.takeOverFrom();
1172 decode.takeOverFrom();
1173 rename.takeOverFrom();
1174 iew.takeOverFrom();
1175 commit.takeOverFrom();
1176
1177 assert(!tickEvent.scheduled());
1178
1179 FullO3CPU<Impl> *oldO3CPU = dynamic_cast<FullO3CPU<Impl>*>(oldCPU);
1180 if (oldO3CPU)
1181 globalSeqNum = oldO3CPU->globalSeqNum;
1182
1183 lastRunningCycle = curCycle();
1184 _status = Idle;
1185}
1186
1187template <class Impl>
1188void
1189FullO3CPU<Impl>::verifyMemoryMode() const
1190{
1191 if (!system->isTimingMode()) {
1192 fatal("The O3 CPU requires the memory system to be in "
1193 "'timing' mode.\n");
1194 }
1195}
1196
1197template <class Impl>
1198TheISA::MiscReg
1199FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
1200{
1201 return this->isa[tid]->readMiscRegNoEffect(misc_reg);
1202}
1203
1204template <class Impl>
1205TheISA::MiscReg
1206FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
1207{
1208 miscRegfileReads++;
1209 return this->isa[tid]->readMiscReg(misc_reg, tcBase(tid));
1210}
1211
1212template <class Impl>
1213void
1214FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
1215 const TheISA::MiscReg &val, ThreadID tid)
1216{
1217 this->isa[tid]->setMiscRegNoEffect(misc_reg, val);
1218}
1219
1220template <class Impl>
1221void
1222FullO3CPU<Impl>::setMiscReg(int misc_reg,
1223 const TheISA::MiscReg &val, ThreadID tid)
1224{
1225 miscRegfileWrites++;
1226 this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid));
1227}
1228
1229template <class Impl>
1230uint64_t
1231FullO3CPU<Impl>::readIntReg(int reg_idx)
1232{
1233 intRegfileReads++;
1234 return regFile.readIntReg(reg_idx);
1235}
1236
1237template <class Impl>
1238FloatReg
1239FullO3CPU<Impl>::readFloatReg(int reg_idx)
1240{
1241 fpRegfileReads++;
1242 return regFile.readFloatReg(reg_idx);
1243}
1244
1245template <class Impl>
1246FloatRegBits
1247FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
1248{
1249 fpRegfileReads++;
1250 return regFile.readFloatRegBits(reg_idx);
1251}
1252
1253template <class Impl>
1254CCReg
1255FullO3CPU<Impl>::readCCReg(int reg_idx)
1256{
1257 ccRegfileReads++;
1258 return regFile.readCCReg(reg_idx);
1259}
1260
1261template <class Impl>
|
1300const VectorReg &
1301FullO3CPU<Impl>::readVectorReg(int reg_idx)
1302{
1303 vectorRegfileReads++;
1304 return regFile.readVectorReg(reg_idx);
1305}
1306
1307template <class Impl>
|
1262void
1263FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
1264{
1265 intRegfileWrites++;
1266 regFile.setIntReg(reg_idx, val);
1267}
1268
1269template <class Impl>
1270void
1271FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
1272{
1273 fpRegfileWrites++;
1274 regFile.setFloatReg(reg_idx, val);
1275}
1276
1277template <class Impl>
1278void
1279FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
1280{
1281 fpRegfileWrites++;
1282 regFile.setFloatRegBits(reg_idx, val);
1283}
1284
1285template <class Impl>
1286void
1287FullO3CPU<Impl>::setCCReg(int reg_idx, CCReg val)
1288{
1289 ccRegfileWrites++;
1290 regFile.setCCReg(reg_idx, val);
1291}
1292
1293template <class Impl>
|
1340void
1341FullO3CPU<Impl>::setVectorReg(int reg_idx, const VectorReg &val)
1342{
1343 vectorRegfileWrites++;
1344 regFile.setVectorReg(reg_idx, val);
1345}
1346
1347template <class Impl>
|
1294uint64_t
1295FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1296{
1297 intRegfileReads++;
1298 PhysRegIndex phys_reg = commitRenameMap[tid].lookupInt(reg_idx);
1299
1300 return regFile.readIntReg(phys_reg);
1301}
1302
1303template <class Impl>
1304float
1305FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
1306{
1307 fpRegfileReads++;
1308 PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1309
1310 return regFile.readFloatReg(phys_reg);
1311}
1312
1313template <class Impl>
1314uint64_t
1315FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid)
1316{
1317 fpRegfileReads++;
1318 PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1319
1320 return regFile.readFloatRegBits(phys_reg);
1321}
1322
1323template <class Impl>
1324CCReg
1325FullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid)
1326{
1327 ccRegfileReads++;
1328 PhysRegIndex phys_reg = commitRenameMap[tid].lookupCC(reg_idx);
1329
1330 return regFile.readCCReg(phys_reg);
1331}
1332
1333template <class Impl>
|
1388const VectorReg&
1389FullO3CPU<Impl>::readArchVectorReg(int reg_idx, ThreadID tid)
1390{
1391 vectorRegfileReads++;
1392 PhysRegIndex phys_reg = commitRenameMap[tid].lookupVector(reg_idx);
1393
1394 return regFile.readVectorReg(phys_reg);
1395}
1396
1397template <class Impl>
|
1334void
1335FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
1336{
1337 intRegfileWrites++;
1338 PhysRegIndex phys_reg = commitRenameMap[tid].lookupInt(reg_idx);
1339
1340 regFile.setIntReg(phys_reg, val);
1341}
1342
1343template <class Impl>
1344void
1345FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid)
1346{
1347 fpRegfileWrites++;
1348 PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1349
1350 regFile.setFloatReg(phys_reg, val);
1351}
1352
1353template <class Impl>
1354void
1355FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid)
1356{
1357 fpRegfileWrites++;
1358 PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1359
1360 regFile.setFloatRegBits(phys_reg, val);
1361}
1362
1363template <class Impl>
1364void
1365FullO3CPU<Impl>::setArchCCReg(int reg_idx, CCReg val, ThreadID tid)
1366{
1367 ccRegfileWrites++;
1368 PhysRegIndex phys_reg = commitRenameMap[tid].lookupCC(reg_idx);
1369
1370 regFile.setCCReg(phys_reg, val);
1371}
1372
1373template <class Impl>
|
1438void
1439FullO3CPU<Impl>::setArchVectorReg(int reg_idx, const VectorReg &val,
1440 ThreadID tid)
1441{
1442 vectorRegfileWrites++;
1443 PhysRegIndex phys_reg = commitRenameMap[tid].lookupVector(reg_idx);
1444 regFile.setVectorReg(phys_reg, val);
1445}
1446
1447template <class Impl>
|
1374TheISA::PCState
1375FullO3CPU<Impl>::pcState(ThreadID tid)
1376{
1377 return commit.pcState(tid);
1378}
1379
1380template <class Impl>
1381void
1382FullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid)
1383{
1384 commit.pcState(val, tid);
1385}
1386
1387template <class Impl>
1388Addr
1389FullO3CPU<Impl>::instAddr(ThreadID tid)
1390{
1391 return commit.instAddr(tid);
1392}
1393
1394template <class Impl>
1395Addr
1396FullO3CPU<Impl>::nextInstAddr(ThreadID tid)
1397{
1398 return commit.nextInstAddr(tid);
1399}
1400
1401template <class Impl>
1402MicroPC
1403FullO3CPU<Impl>::microPC(ThreadID tid)
1404{
1405 return commit.microPC(tid);
1406}
1407
1408template <class Impl>
1409void
1410FullO3CPU<Impl>::squashFromTC(ThreadID tid)
1411{
1412 this->thread[tid]->noSquashFromTC = true;
1413 this->commit.generateTCEvent(tid);
1414}
1415
1416template <class Impl>
1417typename FullO3CPU<Impl>::ListIt
1418FullO3CPU<Impl>::addInst(DynInstPtr &inst)
1419{
1420 instList.push_back(inst);
1421
1422 return --(instList.end());
1423}
1424
1425template <class Impl>
1426void
1427FullO3CPU<Impl>::instDone(ThreadID tid, DynInstPtr &inst)
1428{
1429 // Keep an instruction count.
1430 if (!inst->isMicroop() || inst->isLastMicroop()) {
1431 thread[tid]->numInst++;
1432 thread[tid]->numInsts++;
1433 committedInsts[tid]++;
1434 system->totalNumInsts++;
1435
1436 // Check for instruction-count-based events.
1437 comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1438 system->instEventQueue.serviceEvents(system->totalNumInsts);
1439 }
1440 thread[tid]->numOp++;
1441 thread[tid]->numOps++;
1442 committedOps[tid]++;
1443
1444 probeInstCommit(inst->staticInst);
1445}
1446
1447template <class Impl>
1448void
1449FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
1450{
1451 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s "
1452 "[sn:%lli]\n",
1453 inst->threadNumber, inst->pcState(), inst->seqNum);
1454
1455 removeInstsThisCycle = true;
1456
1457 // Remove the front instruction.
1458 removeList.push(inst->getInstListIt());
1459}
1460
1461template <class Impl>
1462void
1463FullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid)
1464{
1465 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1466 " list.\n", tid);
1467
1468 ListIt end_it;
1469
1470 bool rob_empty = false;
1471
1472 if (instList.empty()) {
1473 return;
1474 } else if (rob.isEmpty(tid)) {
1475 DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1476 end_it = instList.begin();
1477 rob_empty = true;
1478 } else {
1479 end_it = (rob.readTailInst(tid))->getInstListIt();
1480 DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1481 }
1482
1483 removeInstsThisCycle = true;
1484
1485 ListIt inst_it = instList.end();
1486
1487 inst_it--;
1488
1489 // Walk through the instruction list, removing any instructions
1490 // that were inserted after the given instruction iterator, end_it.
1491 while (inst_it != end_it) {
1492 assert(!instList.empty());
1493
1494 squashInstIt(inst_it, tid);
1495
1496 inst_it--;
1497 }
1498
1499 // If the ROB was empty, then we actually need to remove the first
1500 // instruction as well.
1501 if (rob_empty) {
1502 squashInstIt(inst_it, tid);
1503 }
1504}
1505
1506template <class Impl>
1507void
1508FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1509{
1510 assert(!instList.empty());
1511
1512 removeInstsThisCycle = true;
1513
1514 ListIt inst_iter = instList.end();
1515
1516 inst_iter--;
1517
1518 DPRINTF(O3CPU, "Deleting instructions from instruction "
1519 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1520 tid, seq_num, (*inst_iter)->seqNum);
1521
1522 while ((*inst_iter)->seqNum > seq_num) {
1523
1524 bool break_loop = (inst_iter == instList.begin());
1525
1526 squashInstIt(inst_iter, tid);
1527
1528 inst_iter--;
1529
1530 if (break_loop)
1531 break;
1532 }
1533}
1534
1535template <class Impl>
1536inline void
1537FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid)
1538{
1539 if ((*instIt)->threadNumber == tid) {
1540 DPRINTF(O3CPU, "Squashing instruction, "
1541 "[tid:%i] [sn:%lli] PC %s\n",
1542 (*instIt)->threadNumber,
1543 (*instIt)->seqNum,
1544 (*instIt)->pcState());
1545
1546 // Mark it as squashed.
1547 (*instIt)->setSquashed();
1548
1549 // @todo: Formulate a consistent method for deleting
1550 // instructions from the instruction list
1551 // Remove the instruction from the list.
1552 removeList.push(instIt);
1553 }
1554}
1555
1556template <class Impl>
1557void
1558FullO3CPU<Impl>::cleanUpRemovedInsts()
1559{
1560 while (!removeList.empty()) {
1561 DPRINTF(O3CPU, "Removing instruction, "
1562 "[tid:%i] [sn:%lli] PC %s\n",
1563 (*removeList.front())->threadNumber,
1564 (*removeList.front())->seqNum,
1565 (*removeList.front())->pcState());
1566
1567 instList.erase(removeList.front());
1568
1569 removeList.pop();
1570 }
1571
1572 removeInstsThisCycle = false;
1573}
1574/*
1575template <class Impl>
1576void
1577FullO3CPU<Impl>::removeAllInsts()
1578{
1579 instList.clear();
1580}
1581*/
1582template <class Impl>
1583void
1584FullO3CPU<Impl>::dumpInsts()
1585{
1586 int num = 0;
1587
1588 ListIt inst_list_it = instList.begin();
1589
1590 cprintf("Dumping Instruction List\n");
1591
1592 while (inst_list_it != instList.end()) {
1593 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1594 "Squashed:%i\n\n",
1595 num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber,
1596 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1597 (*inst_list_it)->isSquashed());
1598 inst_list_it++;
1599 ++num;
1600 }
1601}
1602/*
1603template <class Impl>
1604void
1605FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
1606{
1607 iew.wakeDependents(inst);
1608}
1609*/
1610template <class Impl>
1611void
1612FullO3CPU<Impl>::wakeCPU()
1613{
1614 if (activityRec.active() || tickEvent.scheduled()) {
1615 DPRINTF(Activity, "CPU already running.\n");
1616 return;
1617 }
1618
1619 DPRINTF(Activity, "Waking up CPU\n");
1620
1621 Cycles cycles(curCycle() - lastRunningCycle);
1622 // @todo: This is an oddity that is only here to match the stats
1623 if (cycles > 1) {
1624 --cycles;
1625 idleCycles += cycles;
1626 numCycles += cycles;
1627 ppCycles->notify(cycles);
1628 }
1629
1630 schedule(tickEvent, clockEdge());
1631}
1632
1633template <class Impl>
1634void
1635FullO3CPU<Impl>::wakeup()
1636{
1637 if (this->thread[0]->status() != ThreadContext::Suspended)
1638 return;
1639
1640 this->wakeCPU();
1641
1642 DPRINTF(Quiesce, "Suspended Processor woken\n");
1643 this->threadContexts[0]->activate();
1644}
1645
1646template <class Impl>
1647ThreadID
1648FullO3CPU<Impl>::getFreeTid()
1649{
1650 for (ThreadID tid = 0; tid < numThreads; tid++) {
1651 if (!tids[tid]) {
1652 tids[tid] = true;
1653 return tid;
1654 }
1655 }
1656
1657 return InvalidThreadID;
1658}
1659
1660template <class Impl>
1661void
1662FullO3CPU<Impl>::updateThreadPriority()
1663{
1664 if (activeThreads.size() > 1) {
1665 //DEFAULT TO ROUND ROBIN SCHEME
1666 //e.g. Move highest priority to end of thread list
1667 list<ThreadID>::iterator list_begin = activeThreads.begin();
1668
1669 unsigned high_thread = *list_begin;
1670
1671 activeThreads.erase(list_begin);
1672
1673 activeThreads.push_back(high_thread);
1674 }
1675}
1676
1677// Forward declaration of FullO3CPU.
1678template class FullO3CPU<O3CPUImpl>;
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