1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 625 unchanged lines hidden (view full) --- 634} 635 636template <class Impl> 637void 638FullO3CPU<Impl>::init() 639{ 640 BaseCPU::init(); 641 |
642 for (ThreadID tid = 0; tid < numThreads; ++tid) { 643 // Set inSyscall so that the CPU doesn't squash when initially 644 // setting up registers. |
645 thread[tid]->inSyscall = true; |
646 // Initialise the ThreadContext's memory proxies 647 thread[tid]->initMemProxies(thread[tid]->getTC()); 648 } |
649 650 // this CPU could still be unconnected if we are restoring from a 651 // checkpoint and this CPU is to be switched in, thus we can only 652 // do this here if the instruction port is actually connected, if 653 // not we have to do it as part of takeOverFrom 654 if (icachePort.isConnected()) 655 fetch.setIcache(); 656 657 if (FullSystem && !params()->defer_registration) { 658 for (ThreadID tid = 0; tid < numThreads; tid++) { 659 ThreadContext *src_tc = threadContexts[tid]; 660 TheISA::initCPU(src_tc, src_tc->contextId()); |
661 } 662 } 663 664 // Clear inSyscall. 665 for (int tid = 0; tid < numThreads; ++tid) 666 thread[tid]->inSyscall = false; 667 668 // Initialize stages. --- 1060 unchanged lines hidden --- |