1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 31 unchanged lines hidden (view full) --- 40 * 41 * Authors: Kevin Lim 42 * Korey Sewell 43 * Rick Strong 44 */ 45 46#include "arch/kernel_stats.hh" 47#include "config/the_isa.hh" |
48#include "cpu/checker/cpu.hh" 49#include "cpu/checker/thread_context.hh" |
50#include "cpu/o3/cpu.hh" 51#include "cpu/o3/isa_specific.hh" 52#include "cpu/o3/thread_context.hh" 53#include "cpu/activity.hh" 54#include "cpu/quiesce_event.hh" 55#include "cpu/simple_thread.hh" 56#include "cpu/thread_context.hh" 57#include "debug/Activity.hh" 58#include "debug/O3CPU.hh" 59#include "debug/Quiesce.hh" 60#include "enums/MemoryMode.hh" 61#include "sim/core.hh" 62#include "sim/full_system.hh" 63#include "sim/process.hh" 64#include "sim/stat_control.hh" 65#include "sim/system.hh" 66 |
67#if THE_ISA == ALPHA_ISA 68#include "arch/alpha/osfpal.hh" 69#include "debug/Activity.hh" 70#endif 71 72struct BaseCPUParams; 73 74using namespace TheISA; --- 179 unchanged lines hidden (view full) --- 254 deferRegistration(params->defer_registration) 255{ 256 if (!deferRegistration) { 257 _status = Running; 258 } else { 259 _status = Idle; 260 } 261 |
262 if (params->checker) { 263 BaseCPU *temp_checker = params->checker; 264 checker = dynamic_cast<Checker<Impl> *>(temp_checker); 265 checker->setIcachePort(&icachePort); 266 checker->setSystem(params->system); 267 } else { 268 checker = NULL; 269 } |
270 271 if (!FullSystem) { 272 thread.resize(numThreads); 273 tids.resize(numThreads); 274 } 275 276 // The stages also need their CPU pointer setup. However this 277 // must be done at the upper level CPU because they have pointers --- 149 unchanged lines hidden (view full) --- 427 428 // Setup the TC that will serve as the interface to the threads/CPU. 429 O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>; 430 431 tc = o3_tc; 432 433 // If we're using a checker, then the TC should be the 434 // CheckerThreadContext. |
435 if (params->checker) { 436 tc = new CheckerThreadContext<O3ThreadContext<Impl> >( 437 o3_tc, this->checker); 438 } |
439 440 o3_tc->cpu = (typename Impl::O3CPU *)(this); 441 assert(o3_tc->cpu); 442 o3_tc->thread = this->thread[tid]; 443 444 if (FullSystem) { 445 // Setup quiesce event. 446 this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc); --- 747 unchanged lines hidden (view full) --- 1194 iew.switchOut(); 1195 commit.switchOut(); 1196 instList.clear(); 1197 while (!removeList.empty()) { 1198 removeList.pop(); 1199 } 1200 1201 _status = SwitchedOut; |
1202 |
1203 if (checker) 1204 checker->switchOut(); |
1205 |
1206 if (tickEvent.scheduled()) 1207 tickEvent.squash(); 1208} 1209 1210template <class Impl> 1211void 1212FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 1213{ --- 514 unchanged lines hidden --- |