1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 48 unchanged lines hidden (view full) --- 57#include "arch/alpha/osfpal.hh" 58#endif 59 60class BaseCPUParams; 61 62using namespace TheISA; 63 64BaseO3CPU::BaseO3CPU(BaseCPUParams *params) |
65 : BaseCPU(params) |
66{ 67} 68 69void 70BaseO3CPU::regStats() 71{ 72 BaseCPU::regStats(); 73} --- 325 unchanged lines hidden (view full) --- 399 o3_tc->thread = this->thread[i]; 400 401#if FULL_SYSTEM 402 // Setup quiesce event. 403 this->thread[i]->quiesceEvent = new EndQuiesceEvent(tc); 404#endif 405 // Give the thread the TC. 406 this->thread[i]->tc = tc; |
407 408 // Add the TC to the CPU's list of TC's. 409 this->threadContexts.push_back(tc); 410 } 411 412 for (int i=0; i < this->numThreads; i++) { 413 this->thread[i]->setFuncExeInst(0); 414 } --- 190 unchanged lines hidden (view full) --- 605 ThreadContext *src_tc = thread[tid]->getTC(); 606#endif 607 // Threads start in the Suspended State 608 if (src_tc->status() != ThreadContext::Suspended) { 609 continue; 610 } 611 612#if FULL_SYSTEM |
613 TheISA::initCPU(src_tc, src_tc->cpuId()); |
614#endif 615 } 616 617 // Clear inSyscall. 618 for (int i = 0; i < number_of_threads; ++i) 619 thread[i]->inSyscall = false; 620 621 // Initialize stages. --- 1121 unchanged lines hidden --- |