1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 190 unchanged lines hidden (view full) --- 199 numThreads(number_of_threads) 200{ 201 if (!deferRegistration) { 202 _status = Running; 203 } else { 204 _status = Idle; 205 } 206 |
207 checker = NULL; 208 |
209 if (params->checker) { |
210#if USE_CHECKER |
211 BaseCPU *temp_checker = params->checker; 212 checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker); 213#if FULL_SYSTEM 214 checker->setSystem(params->system); 215#endif |
216#else 217 panic("Checker enabled but not compiled in!"); |
218#endif // USE_CHECKER |
219 } |
220 221#if !FULL_SYSTEM 222 thread.resize(number_of_threads); 223 tids.resize(number_of_threads); 224#endif 225 226 // The stages also need their CPU pointer setup. However this 227 // must be done at the upper level CPU because they have pointers --- 151 unchanged lines hidden (view full) --- 379 totalCommittedInsts 380 .name(name() + ".committedInsts_total") 381 .desc("Number of Instructions Simulated"); 382 383 cpi 384 .name(name() + ".cpi") 385 .desc("CPI: Cycles Per Instruction") 386 .precision(6); |
387 cpi = simTicks / committedInsts; |
388 389 totalCpi 390 .name(name() + ".cpi_total") 391 .desc("CPI: Total CPI of All Threads") 392 .precision(6); |
393 totalCpi = simTicks / totalCommittedInsts; |
394 395 ipc 396 .name(name() + ".ipc") 397 .desc("IPC: Instructions Per Cycle") 398 .precision(6); |
399 ipc = committedInsts / simTicks; |
400 401 totalIpc 402 .name(name() + ".ipc_total") 403 .desc("IPC: Total IPC of All Threads") 404 .precision(6); |
405 totalIpc = totalCommittedInsts / simTicks; |
406 407} 408 409template <class Impl> 410Port * 411FullO3CPU<Impl>::getPort(const std::string &if_name, int idx) 412{ 413 if (if_name == "dcache_port") --- 277 unchanged lines hidden (view full) --- 691 PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 692 693 scoreboard.unsetReg(phys_reg); 694 freeList.addReg(phys_reg); 695 } 696 697 // Squash Throughout Pipeline 698 InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum; |
699 fetch.squash(0, sizeof(TheISA::MachInst), squash_seq_num, tid); |
700 decode.squash(tid); 701 rename.squash(squash_seq_num, tid); 702 iew.squash(tid); 703 commit.rob->squash(squash_seq_num, tid); 704 705 assert(iew.ldstQueue.getCount(tid) == 0); 706 707 // Reset ROB/IQ/LSQ Entries --- 513 unchanged lines hidden (view full) --- 1221 removeInstsThisCycle = true; 1222 1223 // Remove the front instruction. 1224 removeList.push(inst->getInstListIt()); 1225} 1226 1227template <class Impl> 1228void |
1229FullO3CPU<Impl>::removeInstsNotInROB(unsigned tid) |
1230{ 1231 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 1232 " list.\n", tid); 1233 1234 ListIt end_it; 1235 1236 bool rob_empty = false; 1237 --- 14 unchanged lines hidden (view full) --- 1252 1253 inst_it--; 1254 1255 // Walk through the instruction list, removing any instructions 1256 // that were inserted after the given instruction iterator, end_it. 1257 while (inst_it != end_it) { 1258 assert(!instList.empty()); 1259 |
1260 squashInstIt(inst_it, tid); 1261 1262 inst_it--; 1263 } 1264 1265 // If the ROB was empty, then we actually need to remove the first 1266 // instruction as well. 1267 if (rob_empty) { --- 177 unchanged lines hidden --- |