1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 103 unchanged lines hidden (view full) --- 112const char * 113FullO3CPU<Impl>::ActivateThreadEvent::description() 114{ 115 return "FullO3CPU \"Activate Thread\" event"; 116} 117 118template <class Impl> 119FullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent() |
120 : Event(&mainEventQueue, CPU_Tick_Pri) |
121{ 122} 123 124template <class Impl> 125void 126FullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num, |
127 FullO3CPU |
128{ 129 tid = thread_num; 130 cpu = thread_cpu; |
131} 132 133template <class Impl> 134void 135FullO3CPU<Impl>::DeallocateContextEvent::process() 136{ 137 cpu->deactivateThread(tid); 138 if (remove) --- 5 unchanged lines hidden (view full) --- 144FullO3CPU<Impl>::DeallocateContextEvent::description() 145{ 146 return "FullO3CPU \"Deallocate Context\" event"; 147} 148 149template <class Impl> 150FullO3CPU<Impl>::FullO3CPU(Params *params) 151 : BaseO3CPU(params), |
152#if FULL_SYSTEM 153 itb(params->itb), 154 dtb(params->dtb), 155#endif |
156 tickEvent(this), 157 removeInstsThisCycle(false), 158 fetch(params), 159 decode(params), 160 rename(params), 161 iew(params), 162 commit(params), 163 --- 441 unchanged lines hidden (view full) --- 605 606template <class Impl> 607void 608FullO3CPU<Impl>::suspendContext(int tid) 609{ 610 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid); 611 bool deallocated = deallocateContext(tid, false, 1); 612 // If this was the last thread then unschedule the tick event. |
613 if ((activeThreads.size() == 1 && !deallocated) || activeThreads.size() == 0) |
614 unscheduleTickEvent(); 615 _status = Idle; 616} 617 618template <class Impl> 619void 620FullO3CPU<Impl>::haltContext(int tid) 621{ --- 32 unchanged lines hidden (view full) --- 654 } 655 656 //Copy Thread Data Into RegFile 657 //this->copyFromTC(tid); 658 659 //Set PC/NPC/NNPC 660 setPC(src_tc->readPC(), tid); 661 setNextPC(src_tc->readNextPC(), tid); |
662 setNextNPC(src_tc->readNextNPC(), tid); |
663 664 src_tc->setStatus(ThreadContext::Active); 665 666 activateContext(tid,1); 667 668 //Reset ROB/IQ/LSQ Entries 669 commit.rob->resetEntries(); 670 iew.resetEntries(); --- 22 unchanged lines hidden (view full) --- 693 PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 694 695 scoreboard.unsetReg(phys_reg); 696 freeList.addReg(phys_reg); 697 } 698 699 // Squash Throughout Pipeline 700 InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum; |
701 fetch.squash(0, sizeof(TheISA::MachInst), squash_seq_num, true, tid); |
702 decode.squash(tid); 703 rename.squash(squash_seq_num, tid); 704 iew.squash(tid); 705 commit.rob->squash(squash_seq_num, tid); 706 707 assert(iew.ldstQueue.getCount(tid) == 0); 708 709 // Reset ROB/IQ/LSQ Entries --- 752 unchanged lines hidden --- |