1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 386 unchanged lines hidden (view full) --- 395 396 activityRec.advance(); 397 398 if (removeInstsThisCycle) { 399 cleanUpRemovedInsts(); 400 } 401 402 if (!tickEvent.scheduled()) { |
403 if (_status == SwitchedOut || 404 getState() == SimObject::DrainedTiming) { |
405 // increment stat 406 lastRunningCycle = curTick; 407 } else if (!activityRec.active()) { 408 lastRunningCycle = curTick; 409 timesIdled++; 410 } else { 411 tickEvent.schedule(curTick + cycles(1)); 412 } --- 376 unchanged lines hidden (view full) --- 789 commit.resume(); 790 791 if (_status == SwitchedOut || _status == Idle) 792 return; 793 794 if (!tickEvent.scheduled()) 795 tickEvent.schedule(curTick); 796 _status = Running; |
797 changeState(SimObject::Timing); |
798} 799 800template <class Impl> 801void 802FullO3CPU<Impl>::signalDrained() 803{ 804 if (++drainCount == NumStages) { 805 if (tickEvent.scheduled()) --- 538 unchanged lines hidden --- |