1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 144 unchanged lines hidden (view full) --- 153 154 globalSeqNum(1), 155 156#if FULL_SYSTEM 157 system(params->system), 158 physmem(system->physmem), 159#endif // FULL_SYSTEM 160 mem(params->mem), |
161 switchCount(0), |
162 deferRegistration(params->deferRegistration), 163 numThreads(number_of_threads) 164{ 165 _status = Idle; 166 167 checker = NULL; 168 169 if (params->checker) { --- 288 unchanged lines hidden (view full) --- 458 459 commit.setThreads(thread); 460} 461 462template <class Impl> 463void 464FullO3CPU<Impl>::insertThread(unsigned tid) 465{ |
466 DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); |
467 // Will change now that the PC and thread state is internal to the CPU 468 // and not in the ThreadContext. |
469#if FULL_SYSTEM 470 ThreadContext *src_tc = system->threadContexts[tid]; 471#else |
472 ThreadContext *src_tc = tcBase(tid); |
473#endif 474 475 //Bind Int Regs to Rename Map 476 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 477 PhysRegIndex phys_reg = freeList.getIntReg(); 478 479 renameMap[tid].setEntry(ireg,phys_reg); 480 scoreboard.setReg(phys_reg); 481 } 482 483 //Bind Float Regs to Rename Map 484 for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 485 PhysRegIndex phys_reg = freeList.getFloatReg(); 486 487 renameMap[tid].setEntry(freg,phys_reg); 488 scoreboard.setReg(phys_reg); 489 } 490 491 //Copy Thread Data Into RegFile |
492 //this->copyFromTC(tid); |
493 |
494 //Set PC/NPC/NNPC 495 setPC(src_tc->readPC(), tid); 496 setNextPC(src_tc->readNextPC(), tid); 497#if THE_ISA != ALPHA_ISA 498 setNextNPC(src_tc->readNextNPC(), tid); 499#endif |
500 501 src_tc->setStatus(ThreadContext::Active); 502 503 activateContext(tid,1); 504 505 //Reset ROB/IQ/LSQ Entries 506 commit.rob->resetEntries(); 507 iew.resetEntries(); |
508} 509 510template <class Impl> 511void 512FullO3CPU<Impl>::removeThread(unsigned tid) 513{ |
514 DPRINTF(O3CPU,"[tid:%i] Removing thread from CPU."); 515 516 // Copy Thread Data From RegFile 517 // If thread is suspended, it might be re-allocated 518 //this->copyToTC(tid); 519 520 // Unbind Int Regs from Rename Map |
521 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 522 PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 523 524 scoreboard.unsetReg(phys_reg); 525 freeList.addReg(phys_reg); 526 } 527 |
528 // Unbind Float Regs from Rename Map |
529 for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 530 PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 531 532 scoreboard.unsetReg(phys_reg); 533 freeList.addReg(phys_reg); 534 } 535 |
536 // Squash Throughout Pipeline |
537 fetch.squash(0,tid); 538 decode.squash(tid); 539 rename.squash(tid); 540 541 assert(iew.ldstQueue.getCount(tid) == 0); 542 |
543 // Reset ROB/IQ/LSQ Entries |
544 if (activeThreads.size() >= 1) { 545 commit.rob->resetEntries(); 546 iew.resetEntries(); 547 } |
548} 549 550 551template <class Impl> 552void 553FullO3CPU<Impl>::activateWhenReady(int tid) 554{ 555 DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming" --- 91 unchanged lines hidden (view full) --- 647 _status = Running; 648 } 649} 650 651template <class Impl> 652void 653FullO3CPU<Impl>::suspendContext(int tid) 654{ |
655 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid); |
656 unscheduleTickEvent(); 657 _status = Idle; 658/* 659 //Remove From Active List, if Active 660 list<unsigned>::iterator isActive = find( 661 activeThreads.begin(), activeThreads.end(), tid); 662 663 if (isActive != activeThreads.end()) { 664 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 665 tid); 666 activeThreads.erase(isActive); 667 } 668*/ 669} 670 671template <class Impl> 672void 673FullO3CPU<Impl>::deallocateContext(int tid) 674{ |
675 DPRINTF(O3CPU,"[tid:%i]: Deallocating Thread Context", tid); 676 |
677 //Remove From Active List, if Active |
678 list<unsigned>::iterator thread_it = 679 find(activeThreads.begin(), activeThreads.end(), tid); |
680 |
681 if (thread_it != activeThreads.end()) { |
682 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 683 tid); |
684 activeThreads.erase(thread_it); |
685 686 removeThread(tid); 687 } |
688} 689 690template <class Impl> 691void 692FullO3CPU<Impl>::haltContext(int tid) 693{ |
694 DPRINTF(O3CPU,"[tid:%i]: Halting Thread Context", tid); |
695/* 696 //Remove From Active List, if Active 697 list<unsigned>::iterator isActive = find( 698 activeThreads.begin(), activeThreads.end(), tid); 699 700 if (isActive != activeThreads.end()) { 701 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 702 tid); 703 activeThreads.erase(isActive); 704 705 removeThread(tid); 706 } 707*/ 708} 709 710template <class Impl> |
711void 712FullO3CPU<Impl>::switchOut(Sampler *_sampler) |
713{ |
714 sampler = _sampler; 715 switchCount = 0; 716 fetch.switchOut(); 717 decode.switchOut(); 718 rename.switchOut(); 719 iew.switchOut(); 720 commit.switchOut(); |
721 722 // Wake the CPU and record activity so everything can drain out if 723 // the CPU is currently idle. 724 wakeCPU(); 725 activityRec.activity(); |
726} 727 728template <class Impl> 729void |
730FullO3CPU<Impl>::signalSwitched() |
731{ |
732 if (++switchCount == NumStages) { 733 fetch.doSwitchOut(); 734 rename.doSwitchOut(); 735 commit.doSwitchOut(); 736 instList.clear(); 737 while (!removeList.empty()) { 738 removeList.pop(); 739 } |
740 |
741#if USE_CHECKER 742 if (checker) 743 checker->switchOut(sampler); 744#endif |
745 |
746 if (tickEvent.scheduled()) 747 tickEvent.squash(); |
748 sampler->signalSwitched(); 749 _status = SwitchedOut; |
750 } |
751 assert(switchCount <= 5); |
752} 753 754template <class Impl> 755void |
756FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 757{ 758 // Flush out any old data from the time buffers. 759 for (int i = 0; i < 10; ++i) { 760 timeBuffer.advance(); 761 fetchQueue.advance(); 762 decodeQueue.advance(); 763 renameQueue.advance(); --- 497 unchanged lines hidden --- |