1/* 2 * Copyright (c) 2011-2012, 2014, 2016, 2017, 2019 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 911 unchanged lines hidden (view full) --- 920template <class Impl> 921Fault 922FullO3CPU<Impl>::hwrei(ThreadID tid) 923{ 924#if THE_ISA == ALPHA_ISA 925 // Need to clear the lock flag upon returning from an interrupt. 926 this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid); 927 |
928 auto *stats = dynamic_cast<AlphaISA::Kernel::Statistics *>( 929 this->thread[tid]->kernelStats); 930 assert(stats); 931 stats->hwrei(); |
932 933 // FIXME: XXX check for interrupts? XXX 934#endif 935 return NoFault; 936} 937 938template <class Impl> 939bool 940FullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid) 941{ 942#if THE_ISA == ALPHA_ISA |
943 auto *stats = dynamic_cast<AlphaISA::Kernel::Statistics *>( 944 this->thread[tid]->kernelStats); 945 if (stats) 946 stats->callpal(palFunc, this->threadContexts[tid]); |
947 948 switch (palFunc) { 949 case PAL::halt: 950 halt(); 951 if (--System::numSystemsRunning == 0) 952 exitSimLoop("all cpus halted"); 953 break; 954 --- 981 unchanged lines hidden --- |