228c228,229
< params->numPhysFloatRegs),
---
> params->numPhysFloatRegs,
> params->numPhysCCRegs),
329a331
> assert(params->numPhysCCRegs >= numThreads * TheISA::NumCCRegs);
370a373,378
>
> for (RegIndex ridx = 0; ridx < TheISA::NumCCRegs; ++ridx) {
> PhysRegIndex phys_reg = freeList.getCCReg();
> renameMap[tid].setCCEntry(ridx, phys_reg);
> commitRenameMap[tid].setCCEntry(ridx, phys_reg);
> }
557a566,575
> ccRegfileReads
> .name(name() + ".cc_regfile_reads")
> .desc("number of cc regfile reads")
> .prereq(ccRegfileReads);
>
> ccRegfileWrites
> .name(name() + ".cc_regfile_writes")
> .desc("number of cc regfile writes")
> .prereq(ccRegfileWrites);
>
845c863,864
< for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
---
> int max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs;
> for (int freg = TheISA::NumIntRegs; freg < max_reg; freg++) {
851a871,880
> //Bind condition-code Regs to Rename Map
> max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs + TheISA::NumCCRegs;
> for (int creg = TheISA::NumIntRegs + TheISA::NumFloatRegs;
> creg < max_reg; creg++) {
> PhysRegIndex phys_reg = freeList.getCCReg();
>
> renameMap[tid].setEntry(creg,phys_reg);
> scoreboard.setReg(phys_reg);
> }
>
891c920,921
< for (int freg = TheISA::NumIntRegs; freg < TheISA::NumFloatRegs; freg++) {
---
> int max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs;
> for (int freg = TheISA::NumIntRegs; freg < max_reg; freg++) {
897a928,937
> // Unbind condition-code Regs from Rename Map
> max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs + TheISA::NumCCRegs;
> for (int creg = TheISA::NumIntRegs + TheISA::NumFloatRegs;
> creg < max_reg; creg++) {
> PhysRegIndex phys_reg = renameMap[tid].lookup(creg);
>
> scoreboard.unsetReg(phys_reg);
> freeList.addReg(phys_reg);
> }
>
936a977
> // Should these all be '<' not '>='? This seems backwards...
946a988,992
> } else if (freeList.numFreeCCRegs() >= TheISA::NumCCRegs) {
> DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
> "Phys. CC. Regs.\n",
> tid);
> ready = false;
1368a1415,1422
> CCReg
> FullO3CPU<Impl>::readCCReg(int reg_idx)
> {
> ccRegfileReads++;
> return regFile.readCCReg(reg_idx);
> }
>
> template <class Impl>
1392a1447,1454
> void
> FullO3CPU<Impl>::setCCReg(int reg_idx, CCReg val)
> {
> ccRegfileWrites++;
> regFile.setCCReg(reg_idx, val);
> }
>
> template <class Impl>
1422a1485,1494
> CCReg
> FullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid)
> {
> ccRegfileReads++;
> PhysRegIndex phys_reg = commitRenameMap[tid].lookupCC(reg_idx);
>
> return regFile.readCCReg(phys_reg);
> }
>
> template <class Impl>
1452a1525,1534
> void
> FullO3CPU<Impl>::setArchCCReg(int reg_idx, CCReg val, ThreadID tid)
> {
> ccRegfileWrites++;
> PhysRegIndex phys_reg = commitRenameMap[tid].lookupCC(reg_idx);
>
> regFile.setCCReg(phys_reg, val);
> }
>
> template <class Impl>