2c2
< * Copyright (c) 2011 ARM Limited
---
> * Copyright (c) 2011-2012 ARM Limited
91a92
> assert(pkt->isResponse());
93,95c94,96
< if (pkt->isResponse()) {
< // We shouldn't ever get a block in ownership state
< assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted()));
---
> // We shouldn't ever get a block in ownership state
> assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted()));
> fetch->processCacheCompletion(pkt);
97,99d97
< fetch->processCacheCompletion(pkt);
< }
< //else Snooped a coherence request, just return
113a112
> assert(pkt->isResponse());
117a117,124
> bool
> FullO3CPU<Impl>::DcachePort::recvTimingSnoop(PacketPtr pkt)
> {
> assert(pkt->isRequest());
> return lsq->recvTimingSnoop(pkt);
> }
>
> template <class Impl>