2,13d1
< * Copyright (c) 2011 ARM Limited
< * All rights reserved
< *
< * The license below extends only to copyright in the software and shall
< * not be construed as granting a license to any other intellectual
< * property including but not limited to intellectual property relating
< * to a hardware implementation of the functionality of the software
< * licensed hereunder. You may use the software subject to the license
< * terms below provided that you ensure that this notice is replicated
< * unmodified and in its entirety in all distributions of the software,
< * modified or unmodified, in source code or in binary form.
< *
71d58
< #include "cpu/checker/thread_context.hh"
79c66
< struct BaseCPUParams;
---
> class BaseCPUParams;
95,116d81
< template<class Impl>
< bool
< FullO3CPU<Impl>::IcachePort::recvTiming(PacketPtr pkt)
< {
< DPRINTF(O3CPU, "Fetch unit received timing\n");
< if (pkt->isResponse()) {
< // We shouldn't ever get a block in ownership state
< assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted()));
<
< fetch->processCacheCompletion(pkt);
< }
< //else Snooped a coherence request, just return
< return true;
< }
<
< template<class Impl>
< void
< FullO3CPU<Impl>::IcachePort::recvRetry()
< {
< fetch->recvRetry();
< }
<
118,131d82
< bool
< FullO3CPU<Impl>::DcachePort::recvTiming(PacketPtr pkt)
< {
< return lsq->recvTiming(pkt);
< }
<
< template <class Impl>
< void
< FullO3CPU<Impl>::DcachePort::recvRetry()
< {
< lsq->recvRetry();
< }
<
< template <class Impl>
246,248d196
< icachePort(&fetch, this),
< dcachePort(&iew.ldstQueue, this),
<
272,273c220
< checker = dynamic_cast<Checker<Impl> *>(temp_checker);
< checker->setIcachePort(&icachePort);
---
> checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
413c360
< this->thread[tid] = new Thread(this, 0);
---
> this->thread[tid] = new Thread(this, 0, NULL);
498,503d444
< quiesceCycles
< .name(name() + ".quiesceCycles")
< .desc("Total number of cycles that CPU has spent quiesced or waiting "
< "for an interrupt")
< .prereq(quiesceCycles);
<
584c525
< return &dcachePort;
---
> return iew.getDcachePort();
586c527
< return &icachePort;
---
> return fetch.getIcachePort();
662,668d602
< // this CPU could still be unconnected if we are restoring from a
< // checkpoint and this CPU is to be switched in, thus we can only
< // do this here if the instruction port is actually connected, if
< // not we have to do it as part of takeOverFrom
< if (icachePort.isConnected())
< fetch.setIcache();
<
673,674d606
< // Initialise the ThreadContext's memory proxies
< thread[tid]->initMemProxies(thread[tid]->getTC());
759,760d690
< quiesceCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
<
769,770c699
< FullO3CPU<Impl>::scheduleDeallocateContext(ThreadID tid, bool remove,
< int delay)
---
> FullO3CPU<Impl>::deallocateContext(ThreadID tid, bool remove, int delay)
791c720
< bool deallocated = scheduleDeallocateContext(tid, false, 1);
---
> bool deallocated = deallocateContext(tid, false, 1);
796,798d724
<
< DPRINTF(Quiesce, "Suspending Context\n");
< lastRunningCycle = curTick();
808c734
< scheduleDeallocateContext(tid, true, 1);
---
> deallocateContext(tid, true, 1);
1039a966,975
> template <class Impl>
> void
> FullO3CPU<Impl>::updateMemPorts()
> {
> // Update all ThreadContext's memory ports (Functional/Virtual
> // Ports)
> ThreadID size = thread.size();
> for (ThreadID i = 0; i < size; ++i)
> thread[i]->connectMemPorts(thread[i]->getTC());
> }
1234c1170
< BaseCPU::takeOverFrom(oldCPU);
---
> BaseCPU::takeOverFrom(oldCPU, fetch.getIcachePort(), iew.getDcachePort());
1272,1273d1207
<
< lastRunningCycle = curTick();
1721a1656
> list<ThreadID>::iterator list_end = activeThreads.end();