161a162
> params->numPhysVecPredRegs,
260a262
> assert(params->numPhysVecPredRegs >= numThreads * TheISA::NumVecPredRegs);
327a330,336
> for (RegIndex ridx = 0; ridx < TheISA::NumVecPredRegs; ++ridx) {
> PhysRegIdPtr phys_reg = freeList.getVecPredReg();
> renameMap[tid].setEntry(RegId(VecPredRegClass, ridx), phys_reg);
> commitRenameMap[tid].setEntry(
> RegId(VecPredRegClass, ridx), phys_reg);
> }
>
540a550,559
> vecPredRegfileReads
> .name(name() + ".pred_regfile_reads")
> .desc("number of predicate regfile reads")
> .prereq(vecPredRegfileReads);
>
> vecPredRegfileWrites
> .name(name() + ".pred_regfile_writes")
> .desc("number of predicate regfile writes")
> .prereq(vecPredRegfileWrites);
>
885a905,912
> // Unbind Float Regs from Rename Map
> for (unsigned preg = 0; preg < TheISA::NumVecPredRegs; preg++) {
> PhysRegIdPtr phys_reg = renameMap[tid].lookup(
> RegId(VecPredRegClass, preg));
> scoreboard.unsetReg(phys_reg);
> freeList.addReg(phys_reg);
> }
>
1336a1364,1381
> auto
> FullO3CPU<Impl>::readVecPredReg(PhysRegIdPtr phys_reg) const
> -> const VecPredRegContainer&
> {
> vecPredRegfileReads++;
> return regFile.readVecPredReg(phys_reg);
> }
>
> template <class Impl>
> auto
> FullO3CPU<Impl>::getWritableVecPredReg(PhysRegIdPtr phys_reg)
> -> VecPredRegContainer&
> {
> vecPredRegfileWrites++;
> return regFile.getWritableVecPredReg(phys_reg);
> }
>
> template <class Impl>
1377a1423,1431
> FullO3CPU<Impl>::setVecPredReg(PhysRegIdPtr phys_reg,
> const VecPredRegContainer& val)
> {
> vecPredRegfileWrites++;
> regFile.setVecPredReg(phys_reg, val);
> }
>
> template <class Impl>
> void
1436a1491,1510
> auto
> FullO3CPU<Impl>::readArchVecPredReg(int reg_idx, ThreadID tid) const
> -> const VecPredRegContainer&
> {
> PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
> RegId(VecPredRegClass, reg_idx));
> return readVecPredReg(phys_reg);
> }
>
> template <class Impl>
> auto
> FullO3CPU<Impl>::getWritableArchVecPredReg(int reg_idx, ThreadID tid)
> -> VecPredRegContainer&
> {
> PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
> RegId(VecPredRegClass, reg_idx));
> return getWritableVecPredReg(phys_reg);
> }
>
> template <class Impl>
1490a1565,1574
> FullO3CPU<Impl>::setArchVecPredReg(int reg_idx, const VecPredRegContainer& val,
> ThreadID tid)
> {
> PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
> RegId(VecPredRegClass, reg_idx));
> setVecPredReg(phys_reg, val);
> }
>
> template <class Impl>
> void