1247c1247
< TheISA::MiscReg
---
> RegVal
1254c1254
< TheISA::MiscReg
---
> RegVal
1264c1264
< const TheISA::MiscReg &val, ThreadID tid)
---
> const RegVal &val, ThreadID tid)
1272c1272
< const TheISA::MiscReg &val, ThreadID tid)
---
> const RegVal &val, ThreadID tid)
1279c1279
< uint64_t
---
> RegVal
1287c1287
< FloatRegBits
---
> RegVal
1330c1330
< FullO3CPU<Impl>::setIntReg(PhysRegIdPtr phys_reg, uint64_t val)
---
> FullO3CPU<Impl>::setIntReg(PhysRegIdPtr phys_reg, RegVal val)
1338c1338
< FullO3CPU<Impl>::setFloatRegBits(PhysRegIdPtr phys_reg, FloatRegBits val)
---
> FullO3CPU<Impl>::setFloatRegBits(PhysRegIdPtr phys_reg, RegVal val)
1369c1369
< uint64_t
---
> RegVal
1380c1380
< uint64_t
---
> RegVal
1433c1433
< FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
---
> FullO3CPU<Impl>::setArchIntReg(int reg_idx, RegVal val, ThreadID tid)
1444c1444
< FullO3CPU<Impl>::setArchFloatRegBits(int reg_idx, uint64_t val, ThreadID tid)
---
> FullO3CPU<Impl>::setArchFloatRegBits(int reg_idx, RegVal val, ThreadID tid)