122}
123
124template <class Impl>
125void
126FullO3CPU<Impl>::DcachePort::recvRetry()
127{
128 lsq->recvRetry();
129}
130
131template <class Impl>
132FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
133 : Event(CPU_Tick_Pri), cpu(c)
134{
135}
136
137template <class Impl>
138void
139FullO3CPU<Impl>::TickEvent::process()
140{
141 cpu->tick();
142}
143
144template <class Impl>
145const char *
146FullO3CPU<Impl>::TickEvent::description() const
147{
148 return "FullO3CPU tick";
149}
150
151template <class Impl>
152FullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent()
153 : Event(CPU_Switch_Pri)
154{
155}
156
157template <class Impl>
158void
159FullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num,
160 FullO3CPU<Impl> *thread_cpu)
161{
162 tid = thread_num;
163 cpu = thread_cpu;
164}
165
166template <class Impl>
167void
168FullO3CPU<Impl>::ActivateThreadEvent::process()
169{
170 cpu->activateThread(tid);
171}
172
173template <class Impl>
174const char *
175FullO3CPU<Impl>::ActivateThreadEvent::description() const
176{
177 return "FullO3CPU \"Activate Thread\"";
178}
179
180template <class Impl>
181FullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent()
182 : Event(CPU_Tick_Pri), tid(0), remove(false), cpu(NULL)
183{
184}
185
186template <class Impl>
187void
188FullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num,
189 FullO3CPU<Impl> *thread_cpu)
190{
191 tid = thread_num;
192 cpu = thread_cpu;
193 remove = false;
194}
195
196template <class Impl>
197void
198FullO3CPU<Impl>::DeallocateContextEvent::process()
199{
200 cpu->deactivateThread(tid);
201 if (remove)
202 cpu->removeThread(tid);
203}
204
205template <class Impl>
206const char *
207FullO3CPU<Impl>::DeallocateContextEvent::description() const
208{
209 return "FullO3CPU \"Deallocate Context\"";
210}
211
212template <class Impl>
213FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
214 : BaseO3CPU(params),
215 itb(params->itb),
216 dtb(params->dtb),
217 tickEvent(this),
218#ifndef NDEBUG
219 instcount(0),
220#endif
221 removeInstsThisCycle(false),
222 fetch(this, params),
223 decode(this, params),
224 rename(this, params),
225 iew(this, params),
226 commit(this, params),
227
228 regFile(this, params->numPhysIntRegs,
229 params->numPhysFloatRegs),
230
231 freeList(params->numThreads,
232 TheISA::NumIntRegs, params->numPhysIntRegs,
233 TheISA::NumFloatRegs, params->numPhysFloatRegs),
234
235 rob(this,
236 params->numROBEntries, params->squashWidth,
237 params->smtROBPolicy, params->smtROBThreshold,
238 params->numThreads),
239
240 scoreboard(params->numThreads,
241 TheISA::NumIntRegs, params->numPhysIntRegs,
242 TheISA::NumFloatRegs, params->numPhysFloatRegs,
243 TheISA::NumMiscRegs * numThreads,
244 TheISA::ZeroReg),
245
246 icachePort(&fetch, this),
247 dcachePort(&iew.ldstQueue, this),
248
249 timeBuffer(params->backComSize, params->forwardComSize),
250 fetchQueue(params->backComSize, params->forwardComSize),
251 decodeQueue(params->backComSize, params->forwardComSize),
252 renameQueue(params->backComSize, params->forwardComSize),
253 iewQueue(params->backComSize, params->forwardComSize),
254 activityRec(name(), NumStages,
255 params->backComSize + params->forwardComSize,
256 params->activity),
257
258 globalSeqNum(1),
259 system(params->system),
260 drainCount(0),
261 deferRegistration(params->defer_registration)
262{
263 if (!deferRegistration) {
264 _status = Running;
265 } else {
266 _status = Idle;
267 }
268
269 if (params->checker) {
270 BaseCPU *temp_checker = params->checker;
271 checker = dynamic_cast<Checker<Impl> *>(temp_checker);
272 checker->setIcachePort(&icachePort);
273 checker->setSystem(params->system);
274 } else {
275 checker = NULL;
276 }
277
278 if (!FullSystem) {
279 thread.resize(numThreads);
280 tids.resize(numThreads);
281 }
282
283 // The stages also need their CPU pointer setup. However this
284 // must be done at the upper level CPU because they have pointers
285 // to the upper level CPU, and not this FullO3CPU.
286
287 // Set up Pointers to the activeThreads list for each stage
288 fetch.setActiveThreads(&activeThreads);
289 decode.setActiveThreads(&activeThreads);
290 rename.setActiveThreads(&activeThreads);
291 iew.setActiveThreads(&activeThreads);
292 commit.setActiveThreads(&activeThreads);
293
294 // Give each of the stages the time buffer they will use.
295 fetch.setTimeBuffer(&timeBuffer);
296 decode.setTimeBuffer(&timeBuffer);
297 rename.setTimeBuffer(&timeBuffer);
298 iew.setTimeBuffer(&timeBuffer);
299 commit.setTimeBuffer(&timeBuffer);
300
301 // Also setup each of the stages' queues.
302 fetch.setFetchQueue(&fetchQueue);
303 decode.setFetchQueue(&fetchQueue);
304 commit.setFetchQueue(&fetchQueue);
305 decode.setDecodeQueue(&decodeQueue);
306 rename.setDecodeQueue(&decodeQueue);
307 rename.setRenameQueue(&renameQueue);
308 iew.setRenameQueue(&renameQueue);
309 iew.setIEWQueue(&iewQueue);
310 commit.setIEWQueue(&iewQueue);
311 commit.setRenameQueue(&renameQueue);
312
313 commit.setIEWStage(&iew);
314 rename.setIEWStage(&iew);
315 rename.setCommitStage(&commit);
316
317 ThreadID active_threads;
318 if (FullSystem) {
319 active_threads = 1;
320 } else {
321 active_threads = params->workload.size();
322
323 if (active_threads > Impl::MaxThreads) {
324 panic("Workload Size too large. Increase the 'MaxThreads' "
325 "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) "
326 "or edit your workload size.");
327 }
328 }
329
330 //Make Sure That this a Valid Architeture
331 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs);
332 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
333
334 rename.setScoreboard(&scoreboard);
335 iew.setScoreboard(&scoreboard);
336
337 // Setup the rename map for whichever stages need it.
338 PhysRegIndex lreg_idx = 0;
339 PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs
340
341 for (ThreadID tid = 0; tid < numThreads; tid++) {
342 bool bindRegs = (tid <= active_threads - 1);
343
344 commitRenameMap[tid].init(TheISA::NumIntRegs,
345 params->numPhysIntRegs,
346 lreg_idx, //Index for Logical. Regs
347
348 TheISA::NumFloatRegs,
349 params->numPhysFloatRegs,
350 freg_idx, //Index for Float Regs
351
352 TheISA::NumMiscRegs,
353
354 TheISA::ZeroReg,
355 TheISA::ZeroReg,
356
357 tid,
358 false);
359
360 renameMap[tid].init(TheISA::NumIntRegs,
361 params->numPhysIntRegs,
362 lreg_idx, //Index for Logical. Regs
363
364 TheISA::NumFloatRegs,
365 params->numPhysFloatRegs,
366 freg_idx, //Index for Float Regs
367
368 TheISA::NumMiscRegs,
369
370 TheISA::ZeroReg,
371 TheISA::ZeroReg,
372
373 tid,
374 bindRegs);
375
376 activateThreadEvent[tid].init(tid, this);
377 deallocateContextEvent[tid].init(tid, this);
378 }
379
380 rename.setRenameMap(renameMap);
381 commit.setRenameMap(commitRenameMap);
382
383 // Give renameMap & rename stage access to the freeList;
384 for (ThreadID tid = 0; tid < numThreads; tid++)
385 renameMap[tid].setFreeList(&freeList);
386 rename.setFreeList(&freeList);
387
388 // Setup the ROB for whichever stages need it.
389 commit.setROB(&rob);
390
391 lastRunningCycle = curTick();
392
393 lastActivatedCycle = -1;
394#if 0
395 // Give renameMap & rename stage access to the freeList;
396 for (ThreadID tid = 0; tid < numThreads; tid++)
397 globalSeqNum[tid] = 1;
398#endif
399
400 contextSwitch = false;
401 DPRINTF(O3CPU, "Creating O3CPU object.\n");
402
403 // Setup any thread state.
404 this->thread.resize(this->numThreads);
405
406 for (ThreadID tid = 0; tid < this->numThreads; ++tid) {
407 if (FullSystem) {
408 // SMT is not supported in FS mode yet.
409 assert(this->numThreads == 1);
410 this->thread[tid] = new Thread(this, 0, NULL);
411 } else {
412 if (tid < params->workload.size()) {
413 DPRINTF(O3CPU, "Workload[%i] process is %#x",
414 tid, this->thread[tid]);
415 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
416 (typename Impl::O3CPU *)(this),
417 tid, params->workload[tid]);
418
419 //usedTids[tid] = true;
420 //threadMap[tid] = tid;
421 } else {
422 //Allocate Empty thread so M5 can use later
423 //when scheduling threads to CPU
424 Process* dummy_proc = NULL;
425
426 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
427 (typename Impl::O3CPU *)(this),
428 tid, dummy_proc);
429 //usedTids[tid] = false;
430 }
431 }
432
433 ThreadContext *tc;
434
435 // Setup the TC that will serve as the interface to the threads/CPU.
436 O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>;
437
438 tc = o3_tc;
439
440 // If we're using a checker, then the TC should be the
441 // CheckerThreadContext.
442 if (params->checker) {
443 tc = new CheckerThreadContext<O3ThreadContext<Impl> >(
444 o3_tc, this->checker);
445 }
446
447 o3_tc->cpu = (typename Impl::O3CPU *)(this);
448 assert(o3_tc->cpu);
449 o3_tc->thread = this->thread[tid];
450
451 if (FullSystem) {
452 // Setup quiesce event.
453 this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
454 }
455 // Give the thread the TC.
456 this->thread[tid]->tc = tc;
457
458 // Add the TC to the CPU's list of TC's.
459 this->threadContexts.push_back(tc);
460 }
461
462 // FullO3CPU always requires an interrupt controller.
463 if (!params->defer_registration && !interrupts) {
464 fatal("FullO3CPU %s has no interrupt controller.\n"
465 "Ensure createInterruptController() is called.\n", name());
466 }
467
468 for (ThreadID tid = 0; tid < this->numThreads; tid++)
469 this->thread[tid]->setFuncExeInst(0);
470
471 lockAddr = 0;
472 lockFlag = false;
473}
474
475template <class Impl>
476FullO3CPU<Impl>::~FullO3CPU()
477{
478}
479
480template <class Impl>
481void
482FullO3CPU<Impl>::regStats()
483{
484 BaseO3CPU::regStats();
485
486 // Register any of the O3CPU's stats here.
487 timesIdled
488 .name(name() + ".timesIdled")
489 .desc("Number of times that the entire CPU went into an idle state and"
490 " unscheduled itself")
491 .prereq(timesIdled);
492
493 idleCycles
494 .name(name() + ".idleCycles")
495 .desc("Total number of cycles that the CPU has spent unscheduled due "
496 "to idling")
497 .prereq(idleCycles);
498
499 quiesceCycles
500 .name(name() + ".quiesceCycles")
501 .desc("Total number of cycles that CPU has spent quiesced or waiting "
502 "for an interrupt")
503 .prereq(quiesceCycles);
504
505 // Number of Instructions simulated
506 // --------------------------------
507 // Should probably be in Base CPU but need templated
508 // MaxThreads so put in here instead
509 committedInsts
510 .init(numThreads)
511 .name(name() + ".committedInsts")
512 .desc("Number of Instructions Simulated");
513
514 committedOps
515 .init(numThreads)
516 .name(name() + ".committedOps")
517 .desc("Number of Ops (including micro ops) Simulated");
518
519 totalCommittedInsts
520 .name(name() + ".committedInsts_total")
521 .desc("Number of Instructions Simulated");
522
523 cpi
524 .name(name() + ".cpi")
525 .desc("CPI: Cycles Per Instruction")
526 .precision(6);
527 cpi = numCycles / committedInsts;
528
529 totalCpi
530 .name(name() + ".cpi_total")
531 .desc("CPI: Total CPI of All Threads")
532 .precision(6);
533 totalCpi = numCycles / totalCommittedInsts;
534
535 ipc
536 .name(name() + ".ipc")
537 .desc("IPC: Instructions Per Cycle")
538 .precision(6);
539 ipc = committedInsts / numCycles;
540
541 totalIpc
542 .name(name() + ".ipc_total")
543 .desc("IPC: Total IPC of All Threads")
544 .precision(6);
545 totalIpc = totalCommittedInsts / numCycles;
546
547 this->fetch.regStats();
548 this->decode.regStats();
549 this->rename.regStats();
550 this->iew.regStats();
551 this->commit.regStats();
552 this->rob.regStats();
553
554 intRegfileReads
555 .name(name() + ".int_regfile_reads")
556 .desc("number of integer regfile reads")
557 .prereq(intRegfileReads);
558
559 intRegfileWrites
560 .name(name() + ".int_regfile_writes")
561 .desc("number of integer regfile writes")
562 .prereq(intRegfileWrites);
563
564 fpRegfileReads
565 .name(name() + ".fp_regfile_reads")
566 .desc("number of floating regfile reads")
567 .prereq(fpRegfileReads);
568
569 fpRegfileWrites
570 .name(name() + ".fp_regfile_writes")
571 .desc("number of floating regfile writes")
572 .prereq(fpRegfileWrites);
573
574 miscRegfileReads
575 .name(name() + ".misc_regfile_reads")
576 .desc("number of misc regfile reads")
577 .prereq(miscRegfileReads);
578
579 miscRegfileWrites
580 .name(name() + ".misc_regfile_writes")
581 .desc("number of misc regfile writes")
582 .prereq(miscRegfileWrites);
583}
584
585template <class Impl>
586void
587FullO3CPU<Impl>::tick()
588{
589 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
590
591 ++numCycles;
592
593// activity = false;
594
595 //Tick each of the stages
596 fetch.tick();
597
598 decode.tick();
599
600 rename.tick();
601
602 iew.tick();
603
604 commit.tick();
605
606 if (!FullSystem)
607 doContextSwitch();
608
609 // Now advance the time buffers
610 timeBuffer.advance();
611
612 fetchQueue.advance();
613 decodeQueue.advance();
614 renameQueue.advance();
615 iewQueue.advance();
616
617 activityRec.advance();
618
619 if (removeInstsThisCycle) {
620 cleanUpRemovedInsts();
621 }
622
623 if (!tickEvent.scheduled()) {
624 if (_status == SwitchedOut ||
625 getState() == SimObject::Drained) {
626 DPRINTF(O3CPU, "Switched out!\n");
627 // increment stat
628 lastRunningCycle = curTick();
629 } else if (!activityRec.active() || _status == Idle) {
630 DPRINTF(O3CPU, "Idle!\n");
631 lastRunningCycle = curTick();
632 timesIdled++;
633 } else {
634 schedule(tickEvent, nextCycle(curTick() + ticks(1)));
635 DPRINTF(O3CPU, "Scheduling next tick!\n");
636 }
637 }
638
639 if (!FullSystem)
640 updateThreadPriority();
641}
642
643template <class Impl>
644void
645FullO3CPU<Impl>::init()
646{
647 BaseCPU::init();
648
649 for (ThreadID tid = 0; tid < numThreads; ++tid) {
650 // Set inSyscall so that the CPU doesn't squash when initially
651 // setting up registers.
652 thread[tid]->inSyscall = true;
653 // Initialise the ThreadContext's memory proxies
654 thread[tid]->initMemProxies(thread[tid]->getTC());
655 }
656
657 // this CPU could still be unconnected if we are restoring from a
658 // checkpoint and this CPU is to be switched in, thus we can only
659 // do this here if the instruction port is actually connected, if
660 // not we have to do it as part of takeOverFrom
661 if (icachePort.isConnected())
662 fetch.setIcache();
663
664 if (FullSystem && !params()->defer_registration) {
665 for (ThreadID tid = 0; tid < numThreads; tid++) {
666 ThreadContext *src_tc = threadContexts[tid];
667 TheISA::initCPU(src_tc, src_tc->contextId());
668 }
669 }
670
671 // Clear inSyscall.
672 for (int tid = 0; tid < numThreads; ++tid)
673 thread[tid]->inSyscall = false;
674
675 // Initialize stages.
676 fetch.initStage();
677 iew.initStage();
678 rename.initStage();
679 commit.initStage();
680
681 commit.setThreads(thread);
682}
683
684template <class Impl>
685void
686FullO3CPU<Impl>::activateThread(ThreadID tid)
687{
688 list<ThreadID>::iterator isActive =
689 std::find(activeThreads.begin(), activeThreads.end(), tid);
690
691 DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid);
692
693 if (isActive == activeThreads.end()) {
694 DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n",
695 tid);
696
697 activeThreads.push_back(tid);
698 }
699}
700
701template <class Impl>
702void
703FullO3CPU<Impl>::deactivateThread(ThreadID tid)
704{
705 //Remove From Active List, if Active
706 list<ThreadID>::iterator thread_it =
707 std::find(activeThreads.begin(), activeThreads.end(), tid);
708
709 DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid);
710
711 if (thread_it != activeThreads.end()) {
712 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
713 tid);
714 activeThreads.erase(thread_it);
715 }
716}
717
718template <class Impl>
719Counter
720FullO3CPU<Impl>::totalInsts() const
721{
722 Counter total(0);
723
724 ThreadID size = thread.size();
725 for (ThreadID i = 0; i < size; i++)
726 total += thread[i]->numInst;
727
728 return total;
729}
730
731template <class Impl>
732Counter
733FullO3CPU<Impl>::totalOps() const
734{
735 Counter total(0);
736
737 ThreadID size = thread.size();
738 for (ThreadID i = 0; i < size; i++)
739 total += thread[i]->numOp;
740
741 return total;
742}
743
744template <class Impl>
745void
746FullO3CPU<Impl>::activateContext(ThreadID tid, int delay)
747{
748 // Needs to set each stage to running as well.
749 if (delay){
750 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate "
751 "on cycle %d\n", tid, curTick() + ticks(delay));
752 scheduleActivateThreadEvent(tid, delay);
753 } else {
754 activateThread(tid);
755 }
756
757 if (lastActivatedCycle < curTick()) {
758 scheduleTickEvent(delay);
759
760 // Be sure to signal that there's some activity so the CPU doesn't
761 // deschedule itself.
762 activityRec.activity();
763 fetch.wakeFromQuiesce();
764
765 quiesceCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
766
767 lastActivatedCycle = curTick();
768
769 _status = Running;
770 }
771}
772
773template <class Impl>
774bool
775FullO3CPU<Impl>::scheduleDeallocateContext(ThreadID tid, bool remove,
776 int delay)
777{
778 // Schedule removal of thread data from CPU
779 if (delay){
780 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate "
781 "on cycle %d\n", tid, curTick() + ticks(delay));
782 scheduleDeallocateContextEvent(tid, remove, delay);
783 return false;
784 } else {
785 deactivateThread(tid);
786 if (remove)
787 removeThread(tid);
788 return true;
789 }
790}
791
792template <class Impl>
793void
794FullO3CPU<Impl>::suspendContext(ThreadID tid)
795{
796 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
797 bool deallocated = scheduleDeallocateContext(tid, false, 1);
798 // If this was the last thread then unschedule the tick event.
799 if ((activeThreads.size() == 1 && !deallocated) ||
800 activeThreads.size() == 0)
801 unscheduleTickEvent();
802
803 DPRINTF(Quiesce, "Suspending Context\n");
804 lastRunningCycle = curTick();
805 _status = Idle;
806}
807
808template <class Impl>
809void
810FullO3CPU<Impl>::haltContext(ThreadID tid)
811{
812 //For now, this is the same as deallocate
813 DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
814 scheduleDeallocateContext(tid, true, 1);
815}
816
817template <class Impl>
818void
819FullO3CPU<Impl>::insertThread(ThreadID tid)
820{
821 DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
822 // Will change now that the PC and thread state is internal to the CPU
823 // and not in the ThreadContext.
824 ThreadContext *src_tc;
825 if (FullSystem)
826 src_tc = system->threadContexts[tid];
827 else
828 src_tc = tcBase(tid);
829
830 //Bind Int Regs to Rename Map
831 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
832 PhysRegIndex phys_reg = freeList.getIntReg();
833
834 renameMap[tid].setEntry(ireg,phys_reg);
835 scoreboard.setReg(phys_reg);
836 }
837
838 //Bind Float Regs to Rename Map
839 for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
840 PhysRegIndex phys_reg = freeList.getFloatReg();
841
842 renameMap[tid].setEntry(freg,phys_reg);
843 scoreboard.setReg(phys_reg);
844 }
845
846 //Copy Thread Data Into RegFile
847 //this->copyFromTC(tid);
848
849 //Set PC/NPC/NNPC
850 pcState(src_tc->pcState(), tid);
851
852 src_tc->setStatus(ThreadContext::Active);
853
854 activateContext(tid,1);
855
856 //Reset ROB/IQ/LSQ Entries
857 commit.rob->resetEntries();
858 iew.resetEntries();
859}
860
861template <class Impl>
862void
863FullO3CPU<Impl>::removeThread(ThreadID tid)
864{
865 DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
866
867 // Copy Thread Data From RegFile
868 // If thread is suspended, it might be re-allocated
869 // this->copyToTC(tid);
870
871
872 // @todo: 2-27-2008: Fix how we free up rename mappings
873 // here to alleviate the case for double-freeing registers
874 // in SMT workloads.
875
876 // Unbind Int Regs from Rename Map
877 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
878 PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
879
880 scoreboard.unsetReg(phys_reg);
881 freeList.addReg(phys_reg);
882 }
883
884 // Unbind Float Regs from Rename Map
885 for (int freg = TheISA::NumIntRegs; freg < TheISA::NumFloatRegs; freg++) {
886 PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
887
888 scoreboard.unsetReg(phys_reg);
889 freeList.addReg(phys_reg);
890 }
891
892 // Squash Throughout Pipeline
893 DynInstPtr inst = commit.rob->readHeadInst(tid);
894 InstSeqNum squash_seq_num = inst->seqNum;
895 fetch.squash(0, squash_seq_num, inst, tid);
896 decode.squash(tid);
897 rename.squash(squash_seq_num, tid);
898 iew.squash(tid);
899 iew.ldstQueue.squash(squash_seq_num, tid);
900 commit.rob->squash(squash_seq_num, tid);
901
902
903 assert(iew.instQueue.getCount(tid) == 0);
904 assert(iew.ldstQueue.getCount(tid) == 0);
905
906 // Reset ROB/IQ/LSQ Entries
907
908 // Commented out for now. This should be possible to do by
909 // telling all the pipeline stages to drain first, and then
910 // checking until the drain completes. Once the pipeline is
911 // drained, call resetEntries(). - 10-09-06 ktlim
912/*
913 if (activeThreads.size() >= 1) {
914 commit.rob->resetEntries();
915 iew.resetEntries();
916 }
917*/
918}
919
920
921template <class Impl>
922void
923FullO3CPU<Impl>::activateWhenReady(ThreadID tid)
924{
925 DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming"
926 "(e.g. PhysRegs/ROB/IQ/LSQ) \n",
927 tid);
928
929 bool ready = true;
930
931 if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) {
932 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
933 "Phys. Int. Regs.\n",
934 tid);
935 ready = false;
936 } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) {
937 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
938 "Phys. Float. Regs.\n",
939 tid);
940 ready = false;
941 } else if (commit.rob->numFreeEntries() >=
942 commit.rob->entryAmount(activeThreads.size() + 1)) {
943 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
944 "ROB entries.\n",
945 tid);
946 ready = false;
947 } else if (iew.instQueue.numFreeEntries() >=
948 iew.instQueue.entryAmount(activeThreads.size() + 1)) {
949 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
950 "IQ entries.\n",
951 tid);
952 ready = false;
953 } else if (iew.ldstQueue.numFreeEntries() >=
954 iew.ldstQueue.entryAmount(activeThreads.size() + 1)) {
955 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
956 "LSQ entries.\n",
957 tid);
958 ready = false;
959 }
960
961 if (ready) {
962 insertThread(tid);
963
964 contextSwitch = false;
965
966 cpuWaitList.remove(tid);
967 } else {
968 suspendContext(tid);
969
970 //blocks fetch
971 contextSwitch = true;
972
973 //@todo: dont always add to waitlist
974 //do waitlist
975 cpuWaitList.push_back(tid);
976 }
977}
978
979template <class Impl>
980Fault
981FullO3CPU<Impl>::hwrei(ThreadID tid)
982{
983#if THE_ISA == ALPHA_ISA
984 // Need to clear the lock flag upon returning from an interrupt.
985 this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
986
987 this->thread[tid]->kernelStats->hwrei();
988
989 // FIXME: XXX check for interrupts? XXX
990#endif
991 return NoFault;
992}
993
994template <class Impl>
995bool
996FullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid)
997{
998#if THE_ISA == ALPHA_ISA
999 if (this->thread[tid]->kernelStats)
1000 this->thread[tid]->kernelStats->callpal(palFunc,
1001 this->threadContexts[tid]);
1002
1003 switch (palFunc) {
1004 case PAL::halt:
1005 halt();
1006 if (--System::numSystemsRunning == 0)
1007 exitSimLoop("all cpus halted");
1008 break;
1009
1010 case PAL::bpt:
1011 case PAL::bugchk:
1012 if (this->system->breakpoint())
1013 return false;
1014 break;
1015 }
1016#endif
1017 return true;
1018}
1019
1020template <class Impl>
1021Fault
1022FullO3CPU<Impl>::getInterrupts()
1023{
1024 // Check if there are any outstanding interrupts
1025 return this->interrupts->getInterrupt(this->threadContexts[0]);
1026}
1027
1028template <class Impl>
1029void
1030FullO3CPU<Impl>::processInterrupts(Fault interrupt)
1031{
1032 // Check for interrupts here. For now can copy the code that
1033 // exists within isa_fullsys_traits.hh. Also assume that thread 0
1034 // is the one that handles the interrupts.
1035 // @todo: Possibly consolidate the interrupt checking code.
1036 // @todo: Allow other threads to handle interrupts.
1037
1038 assert(interrupt != NoFault);
1039 this->interrupts->updateIntrInfo(this->threadContexts[0]);
1040
1041 DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
1042 this->trap(interrupt, 0, NULL);
1043}
1044
1045template <class Impl>
1046void
1047FullO3CPU<Impl>::trap(Fault fault, ThreadID tid, StaticInstPtr inst)
1048{
1049 // Pass the thread's TC into the invoke method.
1050 fault->invoke(this->threadContexts[tid], inst);
1051}
1052
1053template <class Impl>
1054void
1055FullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid)
1056{
1057 DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid);
1058
1059 DPRINTF(Activity,"Activity: syscall() called.\n");
1060
1061 // Temporarily increase this by one to account for the syscall
1062 // instruction.
1063 ++(this->thread[tid]->funcExeInst);
1064
1065 // Execute the actual syscall.
1066 this->thread[tid]->syscall(callnum);
1067
1068 // Decrease funcExeInst by one as the normal commit will handle
1069 // incrementing it.
1070 --(this->thread[tid]->funcExeInst);
1071}
1072
1073template <class Impl>
1074void
1075FullO3CPU<Impl>::serialize(std::ostream &os)
1076{
1077 SimObject::State so_state = SimObject::getState();
1078 SERIALIZE_ENUM(so_state);
1079 BaseCPU::serialize(os);
1080 nameOut(os, csprintf("%s.tickEvent", name()));
1081 tickEvent.serialize(os);
1082
1083 // Use SimpleThread's ability to checkpoint to make it easier to
1084 // write out the registers. Also make this static so it doesn't
1085 // get instantiated multiple times (causes a panic in statistics).
1086 static SimpleThread temp;
1087
1088 ThreadID size = thread.size();
1089 for (ThreadID i = 0; i < size; i++) {
1090 nameOut(os, csprintf("%s.xc.%i", name(), i));
1091 temp.copyTC(thread[i]->getTC());
1092 temp.serialize(os);
1093 }
1094}
1095
1096template <class Impl>
1097void
1098FullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion)
1099{
1100 SimObject::State so_state;
1101 UNSERIALIZE_ENUM(so_state);
1102 BaseCPU::unserialize(cp, section);
1103 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
1104
1105 // Use SimpleThread's ability to checkpoint to make it easier to
1106 // read in the registers. Also make this static so it doesn't
1107 // get instantiated multiple times (causes a panic in statistics).
1108 static SimpleThread temp;
1109
1110 ThreadID size = thread.size();
1111 for (ThreadID i = 0; i < size; i++) {
1112 temp.copyTC(thread[i]->getTC());
1113 temp.unserialize(cp, csprintf("%s.xc.%i", section, i));
1114 thread[i]->getTC()->copyArchRegs(temp.getTC());
1115 }
1116}
1117
1118template <class Impl>
1119unsigned int
1120FullO3CPU<Impl>::drain(Event *drain_event)
1121{
1122 DPRINTF(O3CPU, "Switching out\n");
1123
1124 // If the CPU isn't doing anything, then return immediately.
1125 if (_status == Idle || _status == SwitchedOut) {
1126 return 0;
1127 }
1128
1129 drainCount = 0;
1130 fetch.drain();
1131 decode.drain();
1132 rename.drain();
1133 iew.drain();
1134 commit.drain();
1135
1136 // Wake the CPU and record activity so everything can drain out if
1137 // the CPU was not able to immediately drain.
1138 if (getState() != SimObject::Drained) {
1139 // A bit of a hack...set the drainEvent after all the drain()
1140 // calls have been made, that way if all of the stages drain
1141 // immediately, the signalDrained() function knows not to call
1142 // process on the drain event.
1143 drainEvent = drain_event;
1144
1145 wakeCPU();
1146 activityRec.activity();
1147
1148 return 1;
1149 } else {
1150 return 0;
1151 }
1152}
1153
1154template <class Impl>
1155void
1156FullO3CPU<Impl>::resume()
1157{
1158 fetch.resume();
1159 decode.resume();
1160 rename.resume();
1161 iew.resume();
1162 commit.resume();
1163
1164 changeState(SimObject::Running);
1165
1166 if (_status == SwitchedOut || _status == Idle)
1167 return;
1168
1169 assert(system->getMemoryMode() == Enums::timing);
1170
1171 if (!tickEvent.scheduled())
1172 schedule(tickEvent, nextCycle());
1173 _status = Running;
1174}
1175
1176template <class Impl>
1177void
1178FullO3CPU<Impl>::signalDrained()
1179{
1180 if (++drainCount == NumStages) {
1181 if (tickEvent.scheduled())
1182 tickEvent.squash();
1183
1184 changeState(SimObject::Drained);
1185
1186 BaseCPU::switchOut();
1187
1188 if (drainEvent) {
1189 drainEvent->process();
1190 drainEvent = NULL;
1191 }
1192 }
1193 assert(drainCount <= 5);
1194}
1195
1196template <class Impl>
1197void
1198FullO3CPU<Impl>::switchOut()
1199{
1200 fetch.switchOut();
1201 rename.switchOut();
1202 iew.switchOut();
1203 commit.switchOut();
1204 instList.clear();
1205 while (!removeList.empty()) {
1206 removeList.pop();
1207 }
1208
1209 _status = SwitchedOut;
1210
1211 if (checker)
1212 checker->switchOut();
1213
1214 if (tickEvent.scheduled())
1215 tickEvent.squash();
1216}
1217
1218template <class Impl>
1219void
1220FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
1221{
1222 // Flush out any old data from the time buffers.
1223 for (int i = 0; i < timeBuffer.getSize(); ++i) {
1224 timeBuffer.advance();
1225 fetchQueue.advance();
1226 decodeQueue.advance();
1227 renameQueue.advance();
1228 iewQueue.advance();
1229 }
1230
1231 activityRec.reset();
1232
1233 BaseCPU::takeOverFrom(oldCPU);
1234
1235 fetch.takeOverFrom();
1236 decode.takeOverFrom();
1237 rename.takeOverFrom();
1238 iew.takeOverFrom();
1239 commit.takeOverFrom();
1240
1241 assert(!tickEvent.scheduled() || tickEvent.squashed());
1242
1243 // @todo: Figure out how to properly select the tid to put onto
1244 // the active threads list.
1245 ThreadID tid = 0;
1246
1247 list<ThreadID>::iterator isActive =
1248 std::find(activeThreads.begin(), activeThreads.end(), tid);
1249
1250 if (isActive == activeThreads.end()) {
1251 //May Need to Re-code this if the delay variable is the delay
1252 //needed for thread to activate
1253 DPRINTF(O3CPU, "Adding Thread %i to active threads list\n",
1254 tid);
1255
1256 activeThreads.push_back(tid);
1257 }
1258
1259 // Set all statuses to active, schedule the CPU's tick event.
1260 // @todo: Fix up statuses so this is handled properly
1261 ThreadID size = threadContexts.size();
1262 for (ThreadID i = 0; i < size; ++i) {
1263 ThreadContext *tc = threadContexts[i];
1264 if (tc->status() == ThreadContext::Active && _status != Running) {
1265 _status = Running;
1266 reschedule(tickEvent, nextCycle(), true);
1267 }
1268 }
1269 if (!tickEvent.scheduled())
1270 schedule(tickEvent, nextCycle());
1271
1272 lastRunningCycle = curTick();
1273}
1274
1275template <class Impl>
1276TheISA::MiscReg
1277FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid)
1278{
1279 return this->isa[tid].readMiscRegNoEffect(misc_reg);
1280}
1281
1282template <class Impl>
1283TheISA::MiscReg
1284FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
1285{
1286 miscRegfileReads++;
1287 return this->isa[tid].readMiscReg(misc_reg, tcBase(tid));
1288}
1289
1290template <class Impl>
1291void
1292FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
1293 const TheISA::MiscReg &val, ThreadID tid)
1294{
1295 this->isa[tid].setMiscRegNoEffect(misc_reg, val);
1296}
1297
1298template <class Impl>
1299void
1300FullO3CPU<Impl>::setMiscReg(int misc_reg,
1301 const TheISA::MiscReg &val, ThreadID tid)
1302{
1303 miscRegfileWrites++;
1304 this->isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
1305}
1306
1307template <class Impl>
1308uint64_t
1309FullO3CPU<Impl>::readIntReg(int reg_idx)
1310{
1311 intRegfileReads++;
1312 return regFile.readIntReg(reg_idx);
1313}
1314
1315template <class Impl>
1316FloatReg
1317FullO3CPU<Impl>::readFloatReg(int reg_idx)
1318{
1319 fpRegfileReads++;
1320 return regFile.readFloatReg(reg_idx);
1321}
1322
1323template <class Impl>
1324FloatRegBits
1325FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
1326{
1327 fpRegfileReads++;
1328 return regFile.readFloatRegBits(reg_idx);
1329}
1330
1331template <class Impl>
1332void
1333FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
1334{
1335 intRegfileWrites++;
1336 regFile.setIntReg(reg_idx, val);
1337}
1338
1339template <class Impl>
1340void
1341FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
1342{
1343 fpRegfileWrites++;
1344 regFile.setFloatReg(reg_idx, val);
1345}
1346
1347template <class Impl>
1348void
1349FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
1350{
1351 fpRegfileWrites++;
1352 regFile.setFloatRegBits(reg_idx, val);
1353}
1354
1355template <class Impl>
1356uint64_t
1357FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1358{
1359 intRegfileReads++;
1360 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1361
1362 return regFile.readIntReg(phys_reg);
1363}
1364
1365template <class Impl>
1366float
1367FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
1368{
1369 fpRegfileReads++;
1370 int idx = reg_idx + TheISA::NumIntRegs;
1371 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1372
1373 return regFile.readFloatReg(phys_reg);
1374}
1375
1376template <class Impl>
1377uint64_t
1378FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid)
1379{
1380 fpRegfileReads++;
1381 int idx = reg_idx + TheISA::NumIntRegs;
1382 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1383
1384 return regFile.readFloatRegBits(phys_reg);
1385}
1386
1387template <class Impl>
1388void
1389FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
1390{
1391 intRegfileWrites++;
1392 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1393
1394 regFile.setIntReg(phys_reg, val);
1395}
1396
1397template <class Impl>
1398void
1399FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid)
1400{
1401 fpRegfileWrites++;
1402 int idx = reg_idx + TheISA::NumIntRegs;
1403 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1404
1405 regFile.setFloatReg(phys_reg, val);
1406}
1407
1408template <class Impl>
1409void
1410FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid)
1411{
1412 fpRegfileWrites++;
1413 int idx = reg_idx + TheISA::NumIntRegs;
1414 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1415
1416 regFile.setFloatRegBits(phys_reg, val);
1417}
1418
1419template <class Impl>
1420TheISA::PCState
1421FullO3CPU<Impl>::pcState(ThreadID tid)
1422{
1423 return commit.pcState(tid);
1424}
1425
1426template <class Impl>
1427void
1428FullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid)
1429{
1430 commit.pcState(val, tid);
1431}
1432
1433template <class Impl>
1434Addr
1435FullO3CPU<Impl>::instAddr(ThreadID tid)
1436{
1437 return commit.instAddr(tid);
1438}
1439
1440template <class Impl>
1441Addr
1442FullO3CPU<Impl>::nextInstAddr(ThreadID tid)
1443{
1444 return commit.nextInstAddr(tid);
1445}
1446
1447template <class Impl>
1448MicroPC
1449FullO3CPU<Impl>::microPC(ThreadID tid)
1450{
1451 return commit.microPC(tid);
1452}
1453
1454template <class Impl>
1455void
1456FullO3CPU<Impl>::squashFromTC(ThreadID tid)
1457{
1458 this->thread[tid]->inSyscall = true;
1459 this->commit.generateTCEvent(tid);
1460}
1461
1462template <class Impl>
1463typename FullO3CPU<Impl>::ListIt
1464FullO3CPU<Impl>::addInst(DynInstPtr &inst)
1465{
1466 instList.push_back(inst);
1467
1468 return --(instList.end());
1469}
1470
1471template <class Impl>
1472void
1473FullO3CPU<Impl>::instDone(ThreadID tid, DynInstPtr &inst)
1474{
1475 // Keep an instruction count.
1476 if (!inst->isMicroop() || inst->isLastMicroop()) {
1477 thread[tid]->numInst++;
1478 thread[tid]->numInsts++;
1479 committedInsts[tid]++;
1480 totalCommittedInsts++;
1481 }
1482 thread[tid]->numOp++;
1483 thread[tid]->numOps++;
1484 committedOps[tid]++;
1485
1486 system->totalNumInsts++;
1487 // Check for instruction-count-based events.
1488 comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1489 system->instEventQueue.serviceEvents(system->totalNumInsts);
1490}
1491
1492template <class Impl>
1493void
1494FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
1495{
1496 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s "
1497 "[sn:%lli]\n",
1498 inst->threadNumber, inst->pcState(), inst->seqNum);
1499
1500 removeInstsThisCycle = true;
1501
1502 // Remove the front instruction.
1503 removeList.push(inst->getInstListIt());
1504}
1505
1506template <class Impl>
1507void
1508FullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid)
1509{
1510 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1511 " list.\n", tid);
1512
1513 ListIt end_it;
1514
1515 bool rob_empty = false;
1516
1517 if (instList.empty()) {
1518 return;
1519 } else if (rob.isEmpty(/*tid*/)) {
1520 DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1521 end_it = instList.begin();
1522 rob_empty = true;
1523 } else {
1524 end_it = (rob.readTailInst(tid))->getInstListIt();
1525 DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1526 }
1527
1528 removeInstsThisCycle = true;
1529
1530 ListIt inst_it = instList.end();
1531
1532 inst_it--;
1533
1534 // Walk through the instruction list, removing any instructions
1535 // that were inserted after the given instruction iterator, end_it.
1536 while (inst_it != end_it) {
1537 assert(!instList.empty());
1538
1539 squashInstIt(inst_it, tid);
1540
1541 inst_it--;
1542 }
1543
1544 // If the ROB was empty, then we actually need to remove the first
1545 // instruction as well.
1546 if (rob_empty) {
1547 squashInstIt(inst_it, tid);
1548 }
1549}
1550
1551template <class Impl>
1552void
1553FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1554{
1555 assert(!instList.empty());
1556
1557 removeInstsThisCycle = true;
1558
1559 ListIt inst_iter = instList.end();
1560
1561 inst_iter--;
1562
1563 DPRINTF(O3CPU, "Deleting instructions from instruction "
1564 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1565 tid, seq_num, (*inst_iter)->seqNum);
1566
1567 while ((*inst_iter)->seqNum > seq_num) {
1568
1569 bool break_loop = (inst_iter == instList.begin());
1570
1571 squashInstIt(inst_iter, tid);
1572
1573 inst_iter--;
1574
1575 if (break_loop)
1576 break;
1577 }
1578}
1579
1580template <class Impl>
1581inline void
1582FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid)
1583{
1584 if ((*instIt)->threadNumber == tid) {
1585 DPRINTF(O3CPU, "Squashing instruction, "
1586 "[tid:%i] [sn:%lli] PC %s\n",
1587 (*instIt)->threadNumber,
1588 (*instIt)->seqNum,
1589 (*instIt)->pcState());
1590
1591 // Mark it as squashed.
1592 (*instIt)->setSquashed();
1593
1594 // @todo: Formulate a consistent method for deleting
1595 // instructions from the instruction list
1596 // Remove the instruction from the list.
1597 removeList.push(instIt);
1598 }
1599}
1600
1601template <class Impl>
1602void
1603FullO3CPU<Impl>::cleanUpRemovedInsts()
1604{
1605 while (!removeList.empty()) {
1606 DPRINTF(O3CPU, "Removing instruction, "
1607 "[tid:%i] [sn:%lli] PC %s\n",
1608 (*removeList.front())->threadNumber,
1609 (*removeList.front())->seqNum,
1610 (*removeList.front())->pcState());
1611
1612 instList.erase(removeList.front());
1613
1614 removeList.pop();
1615 }
1616
1617 removeInstsThisCycle = false;
1618}
1619/*
1620template <class Impl>
1621void
1622FullO3CPU<Impl>::removeAllInsts()
1623{
1624 instList.clear();
1625}
1626*/
1627template <class Impl>
1628void
1629FullO3CPU<Impl>::dumpInsts()
1630{
1631 int num = 0;
1632
1633 ListIt inst_list_it = instList.begin();
1634
1635 cprintf("Dumping Instruction List\n");
1636
1637 while (inst_list_it != instList.end()) {
1638 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1639 "Squashed:%i\n\n",
1640 num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber,
1641 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1642 (*inst_list_it)->isSquashed());
1643 inst_list_it++;
1644 ++num;
1645 }
1646}
1647/*
1648template <class Impl>
1649void
1650FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
1651{
1652 iew.wakeDependents(inst);
1653}
1654*/
1655template <class Impl>
1656void
1657FullO3CPU<Impl>::wakeCPU()
1658{
1659 if (activityRec.active() || tickEvent.scheduled()) {
1660 DPRINTF(Activity, "CPU already running.\n");
1661 return;
1662 }
1663
1664 DPRINTF(Activity, "Waking up CPU\n");
1665
1666 idleCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
1667 numCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
1668
1669 schedule(tickEvent, nextCycle());
1670}
1671
1672template <class Impl>
1673void
1674FullO3CPU<Impl>::wakeup()
1675{
1676 if (this->thread[0]->status() != ThreadContext::Suspended)
1677 return;
1678
1679 this->wakeCPU();
1680
1681 DPRINTF(Quiesce, "Suspended Processor woken\n");
1682 this->threadContexts[0]->activate();
1683}
1684
1685template <class Impl>
1686ThreadID
1687FullO3CPU<Impl>::getFreeTid()
1688{
1689 for (ThreadID tid = 0; tid < numThreads; tid++) {
1690 if (!tids[tid]) {
1691 tids[tid] = true;
1692 return tid;
1693 }
1694 }
1695
1696 return InvalidThreadID;
1697}
1698
1699template <class Impl>
1700void
1701FullO3CPU<Impl>::doContextSwitch()
1702{
1703 if (contextSwitch) {
1704
1705 //ADD CODE TO DEACTIVE THREAD HERE (???)
1706
1707 ThreadID size = cpuWaitList.size();
1708 for (ThreadID tid = 0; tid < size; tid++) {
1709 activateWhenReady(tid);
1710 }
1711
1712 if (cpuWaitList.size() == 0)
1713 contextSwitch = true;
1714 }
1715}
1716
1717template <class Impl>
1718void
1719FullO3CPU<Impl>::updateThreadPriority()
1720{
1721 if (activeThreads.size() > 1) {
1722 //DEFAULT TO ROUND ROBIN SCHEME
1723 //e.g. Move highest priority to end of thread list
1724 list<ThreadID>::iterator list_begin = activeThreads.begin();
1725
1726 unsigned high_thread = *list_begin;
1727
1728 activeThreads.erase(list_begin);
1729
1730 activeThreads.push_back(high_thread);
1731 }
1732}
1733
1734// Forward declaration of FullO3CPU.
1735template class FullO3CPU<O3CPUImpl>;
| 119}
120
121template <class Impl>
122void
123FullO3CPU<Impl>::DcachePort::recvRetry()
124{
125 lsq->recvRetry();
126}
127
128template <class Impl>
129FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
130 : Event(CPU_Tick_Pri), cpu(c)
131{
132}
133
134template <class Impl>
135void
136FullO3CPU<Impl>::TickEvent::process()
137{
138 cpu->tick();
139}
140
141template <class Impl>
142const char *
143FullO3CPU<Impl>::TickEvent::description() const
144{
145 return "FullO3CPU tick";
146}
147
148template <class Impl>
149FullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent()
150 : Event(CPU_Switch_Pri)
151{
152}
153
154template <class Impl>
155void
156FullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num,
157 FullO3CPU<Impl> *thread_cpu)
158{
159 tid = thread_num;
160 cpu = thread_cpu;
161}
162
163template <class Impl>
164void
165FullO3CPU<Impl>::ActivateThreadEvent::process()
166{
167 cpu->activateThread(tid);
168}
169
170template <class Impl>
171const char *
172FullO3CPU<Impl>::ActivateThreadEvent::description() const
173{
174 return "FullO3CPU \"Activate Thread\"";
175}
176
177template <class Impl>
178FullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent()
179 : Event(CPU_Tick_Pri), tid(0), remove(false), cpu(NULL)
180{
181}
182
183template <class Impl>
184void
185FullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num,
186 FullO3CPU<Impl> *thread_cpu)
187{
188 tid = thread_num;
189 cpu = thread_cpu;
190 remove = false;
191}
192
193template <class Impl>
194void
195FullO3CPU<Impl>::DeallocateContextEvent::process()
196{
197 cpu->deactivateThread(tid);
198 if (remove)
199 cpu->removeThread(tid);
200}
201
202template <class Impl>
203const char *
204FullO3CPU<Impl>::DeallocateContextEvent::description() const
205{
206 return "FullO3CPU \"Deallocate Context\"";
207}
208
209template <class Impl>
210FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
211 : BaseO3CPU(params),
212 itb(params->itb),
213 dtb(params->dtb),
214 tickEvent(this),
215#ifndef NDEBUG
216 instcount(0),
217#endif
218 removeInstsThisCycle(false),
219 fetch(this, params),
220 decode(this, params),
221 rename(this, params),
222 iew(this, params),
223 commit(this, params),
224
225 regFile(this, params->numPhysIntRegs,
226 params->numPhysFloatRegs),
227
228 freeList(params->numThreads,
229 TheISA::NumIntRegs, params->numPhysIntRegs,
230 TheISA::NumFloatRegs, params->numPhysFloatRegs),
231
232 rob(this,
233 params->numROBEntries, params->squashWidth,
234 params->smtROBPolicy, params->smtROBThreshold,
235 params->numThreads),
236
237 scoreboard(params->numThreads,
238 TheISA::NumIntRegs, params->numPhysIntRegs,
239 TheISA::NumFloatRegs, params->numPhysFloatRegs,
240 TheISA::NumMiscRegs * numThreads,
241 TheISA::ZeroReg),
242
243 icachePort(&fetch, this),
244 dcachePort(&iew.ldstQueue, this),
245
246 timeBuffer(params->backComSize, params->forwardComSize),
247 fetchQueue(params->backComSize, params->forwardComSize),
248 decodeQueue(params->backComSize, params->forwardComSize),
249 renameQueue(params->backComSize, params->forwardComSize),
250 iewQueue(params->backComSize, params->forwardComSize),
251 activityRec(name(), NumStages,
252 params->backComSize + params->forwardComSize,
253 params->activity),
254
255 globalSeqNum(1),
256 system(params->system),
257 drainCount(0),
258 deferRegistration(params->defer_registration)
259{
260 if (!deferRegistration) {
261 _status = Running;
262 } else {
263 _status = Idle;
264 }
265
266 if (params->checker) {
267 BaseCPU *temp_checker = params->checker;
268 checker = dynamic_cast<Checker<Impl> *>(temp_checker);
269 checker->setIcachePort(&icachePort);
270 checker->setSystem(params->system);
271 } else {
272 checker = NULL;
273 }
274
275 if (!FullSystem) {
276 thread.resize(numThreads);
277 tids.resize(numThreads);
278 }
279
280 // The stages also need their CPU pointer setup. However this
281 // must be done at the upper level CPU because they have pointers
282 // to the upper level CPU, and not this FullO3CPU.
283
284 // Set up Pointers to the activeThreads list for each stage
285 fetch.setActiveThreads(&activeThreads);
286 decode.setActiveThreads(&activeThreads);
287 rename.setActiveThreads(&activeThreads);
288 iew.setActiveThreads(&activeThreads);
289 commit.setActiveThreads(&activeThreads);
290
291 // Give each of the stages the time buffer they will use.
292 fetch.setTimeBuffer(&timeBuffer);
293 decode.setTimeBuffer(&timeBuffer);
294 rename.setTimeBuffer(&timeBuffer);
295 iew.setTimeBuffer(&timeBuffer);
296 commit.setTimeBuffer(&timeBuffer);
297
298 // Also setup each of the stages' queues.
299 fetch.setFetchQueue(&fetchQueue);
300 decode.setFetchQueue(&fetchQueue);
301 commit.setFetchQueue(&fetchQueue);
302 decode.setDecodeQueue(&decodeQueue);
303 rename.setDecodeQueue(&decodeQueue);
304 rename.setRenameQueue(&renameQueue);
305 iew.setRenameQueue(&renameQueue);
306 iew.setIEWQueue(&iewQueue);
307 commit.setIEWQueue(&iewQueue);
308 commit.setRenameQueue(&renameQueue);
309
310 commit.setIEWStage(&iew);
311 rename.setIEWStage(&iew);
312 rename.setCommitStage(&commit);
313
314 ThreadID active_threads;
315 if (FullSystem) {
316 active_threads = 1;
317 } else {
318 active_threads = params->workload.size();
319
320 if (active_threads > Impl::MaxThreads) {
321 panic("Workload Size too large. Increase the 'MaxThreads' "
322 "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) "
323 "or edit your workload size.");
324 }
325 }
326
327 //Make Sure That this a Valid Architeture
328 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs);
329 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
330
331 rename.setScoreboard(&scoreboard);
332 iew.setScoreboard(&scoreboard);
333
334 // Setup the rename map for whichever stages need it.
335 PhysRegIndex lreg_idx = 0;
336 PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs
337
338 for (ThreadID tid = 0; tid < numThreads; tid++) {
339 bool bindRegs = (tid <= active_threads - 1);
340
341 commitRenameMap[tid].init(TheISA::NumIntRegs,
342 params->numPhysIntRegs,
343 lreg_idx, //Index for Logical. Regs
344
345 TheISA::NumFloatRegs,
346 params->numPhysFloatRegs,
347 freg_idx, //Index for Float Regs
348
349 TheISA::NumMiscRegs,
350
351 TheISA::ZeroReg,
352 TheISA::ZeroReg,
353
354 tid,
355 false);
356
357 renameMap[tid].init(TheISA::NumIntRegs,
358 params->numPhysIntRegs,
359 lreg_idx, //Index for Logical. Regs
360
361 TheISA::NumFloatRegs,
362 params->numPhysFloatRegs,
363 freg_idx, //Index for Float Regs
364
365 TheISA::NumMiscRegs,
366
367 TheISA::ZeroReg,
368 TheISA::ZeroReg,
369
370 tid,
371 bindRegs);
372
373 activateThreadEvent[tid].init(tid, this);
374 deallocateContextEvent[tid].init(tid, this);
375 }
376
377 rename.setRenameMap(renameMap);
378 commit.setRenameMap(commitRenameMap);
379
380 // Give renameMap & rename stage access to the freeList;
381 for (ThreadID tid = 0; tid < numThreads; tid++)
382 renameMap[tid].setFreeList(&freeList);
383 rename.setFreeList(&freeList);
384
385 // Setup the ROB for whichever stages need it.
386 commit.setROB(&rob);
387
388 lastRunningCycle = curTick();
389
390 lastActivatedCycle = -1;
391#if 0
392 // Give renameMap & rename stage access to the freeList;
393 for (ThreadID tid = 0; tid < numThreads; tid++)
394 globalSeqNum[tid] = 1;
395#endif
396
397 contextSwitch = false;
398 DPRINTF(O3CPU, "Creating O3CPU object.\n");
399
400 // Setup any thread state.
401 this->thread.resize(this->numThreads);
402
403 for (ThreadID tid = 0; tid < this->numThreads; ++tid) {
404 if (FullSystem) {
405 // SMT is not supported in FS mode yet.
406 assert(this->numThreads == 1);
407 this->thread[tid] = new Thread(this, 0, NULL);
408 } else {
409 if (tid < params->workload.size()) {
410 DPRINTF(O3CPU, "Workload[%i] process is %#x",
411 tid, this->thread[tid]);
412 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
413 (typename Impl::O3CPU *)(this),
414 tid, params->workload[tid]);
415
416 //usedTids[tid] = true;
417 //threadMap[tid] = tid;
418 } else {
419 //Allocate Empty thread so M5 can use later
420 //when scheduling threads to CPU
421 Process* dummy_proc = NULL;
422
423 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
424 (typename Impl::O3CPU *)(this),
425 tid, dummy_proc);
426 //usedTids[tid] = false;
427 }
428 }
429
430 ThreadContext *tc;
431
432 // Setup the TC that will serve as the interface to the threads/CPU.
433 O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>;
434
435 tc = o3_tc;
436
437 // If we're using a checker, then the TC should be the
438 // CheckerThreadContext.
439 if (params->checker) {
440 tc = new CheckerThreadContext<O3ThreadContext<Impl> >(
441 o3_tc, this->checker);
442 }
443
444 o3_tc->cpu = (typename Impl::O3CPU *)(this);
445 assert(o3_tc->cpu);
446 o3_tc->thread = this->thread[tid];
447
448 if (FullSystem) {
449 // Setup quiesce event.
450 this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
451 }
452 // Give the thread the TC.
453 this->thread[tid]->tc = tc;
454
455 // Add the TC to the CPU's list of TC's.
456 this->threadContexts.push_back(tc);
457 }
458
459 // FullO3CPU always requires an interrupt controller.
460 if (!params->defer_registration && !interrupts) {
461 fatal("FullO3CPU %s has no interrupt controller.\n"
462 "Ensure createInterruptController() is called.\n", name());
463 }
464
465 for (ThreadID tid = 0; tid < this->numThreads; tid++)
466 this->thread[tid]->setFuncExeInst(0);
467
468 lockAddr = 0;
469 lockFlag = false;
470}
471
472template <class Impl>
473FullO3CPU<Impl>::~FullO3CPU()
474{
475}
476
477template <class Impl>
478void
479FullO3CPU<Impl>::regStats()
480{
481 BaseO3CPU::regStats();
482
483 // Register any of the O3CPU's stats here.
484 timesIdled
485 .name(name() + ".timesIdled")
486 .desc("Number of times that the entire CPU went into an idle state and"
487 " unscheduled itself")
488 .prereq(timesIdled);
489
490 idleCycles
491 .name(name() + ".idleCycles")
492 .desc("Total number of cycles that the CPU has spent unscheduled due "
493 "to idling")
494 .prereq(idleCycles);
495
496 quiesceCycles
497 .name(name() + ".quiesceCycles")
498 .desc("Total number of cycles that CPU has spent quiesced or waiting "
499 "for an interrupt")
500 .prereq(quiesceCycles);
501
502 // Number of Instructions simulated
503 // --------------------------------
504 // Should probably be in Base CPU but need templated
505 // MaxThreads so put in here instead
506 committedInsts
507 .init(numThreads)
508 .name(name() + ".committedInsts")
509 .desc("Number of Instructions Simulated");
510
511 committedOps
512 .init(numThreads)
513 .name(name() + ".committedOps")
514 .desc("Number of Ops (including micro ops) Simulated");
515
516 totalCommittedInsts
517 .name(name() + ".committedInsts_total")
518 .desc("Number of Instructions Simulated");
519
520 cpi
521 .name(name() + ".cpi")
522 .desc("CPI: Cycles Per Instruction")
523 .precision(6);
524 cpi = numCycles / committedInsts;
525
526 totalCpi
527 .name(name() + ".cpi_total")
528 .desc("CPI: Total CPI of All Threads")
529 .precision(6);
530 totalCpi = numCycles / totalCommittedInsts;
531
532 ipc
533 .name(name() + ".ipc")
534 .desc("IPC: Instructions Per Cycle")
535 .precision(6);
536 ipc = committedInsts / numCycles;
537
538 totalIpc
539 .name(name() + ".ipc_total")
540 .desc("IPC: Total IPC of All Threads")
541 .precision(6);
542 totalIpc = totalCommittedInsts / numCycles;
543
544 this->fetch.regStats();
545 this->decode.regStats();
546 this->rename.regStats();
547 this->iew.regStats();
548 this->commit.regStats();
549 this->rob.regStats();
550
551 intRegfileReads
552 .name(name() + ".int_regfile_reads")
553 .desc("number of integer regfile reads")
554 .prereq(intRegfileReads);
555
556 intRegfileWrites
557 .name(name() + ".int_regfile_writes")
558 .desc("number of integer regfile writes")
559 .prereq(intRegfileWrites);
560
561 fpRegfileReads
562 .name(name() + ".fp_regfile_reads")
563 .desc("number of floating regfile reads")
564 .prereq(fpRegfileReads);
565
566 fpRegfileWrites
567 .name(name() + ".fp_regfile_writes")
568 .desc("number of floating regfile writes")
569 .prereq(fpRegfileWrites);
570
571 miscRegfileReads
572 .name(name() + ".misc_regfile_reads")
573 .desc("number of misc regfile reads")
574 .prereq(miscRegfileReads);
575
576 miscRegfileWrites
577 .name(name() + ".misc_regfile_writes")
578 .desc("number of misc regfile writes")
579 .prereq(miscRegfileWrites);
580}
581
582template <class Impl>
583void
584FullO3CPU<Impl>::tick()
585{
586 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
587
588 ++numCycles;
589
590// activity = false;
591
592 //Tick each of the stages
593 fetch.tick();
594
595 decode.tick();
596
597 rename.tick();
598
599 iew.tick();
600
601 commit.tick();
602
603 if (!FullSystem)
604 doContextSwitch();
605
606 // Now advance the time buffers
607 timeBuffer.advance();
608
609 fetchQueue.advance();
610 decodeQueue.advance();
611 renameQueue.advance();
612 iewQueue.advance();
613
614 activityRec.advance();
615
616 if (removeInstsThisCycle) {
617 cleanUpRemovedInsts();
618 }
619
620 if (!tickEvent.scheduled()) {
621 if (_status == SwitchedOut ||
622 getState() == SimObject::Drained) {
623 DPRINTF(O3CPU, "Switched out!\n");
624 // increment stat
625 lastRunningCycle = curTick();
626 } else if (!activityRec.active() || _status == Idle) {
627 DPRINTF(O3CPU, "Idle!\n");
628 lastRunningCycle = curTick();
629 timesIdled++;
630 } else {
631 schedule(tickEvent, nextCycle(curTick() + ticks(1)));
632 DPRINTF(O3CPU, "Scheduling next tick!\n");
633 }
634 }
635
636 if (!FullSystem)
637 updateThreadPriority();
638}
639
640template <class Impl>
641void
642FullO3CPU<Impl>::init()
643{
644 BaseCPU::init();
645
646 for (ThreadID tid = 0; tid < numThreads; ++tid) {
647 // Set inSyscall so that the CPU doesn't squash when initially
648 // setting up registers.
649 thread[tid]->inSyscall = true;
650 // Initialise the ThreadContext's memory proxies
651 thread[tid]->initMemProxies(thread[tid]->getTC());
652 }
653
654 // this CPU could still be unconnected if we are restoring from a
655 // checkpoint and this CPU is to be switched in, thus we can only
656 // do this here if the instruction port is actually connected, if
657 // not we have to do it as part of takeOverFrom
658 if (icachePort.isConnected())
659 fetch.setIcache();
660
661 if (FullSystem && !params()->defer_registration) {
662 for (ThreadID tid = 0; tid < numThreads; tid++) {
663 ThreadContext *src_tc = threadContexts[tid];
664 TheISA::initCPU(src_tc, src_tc->contextId());
665 }
666 }
667
668 // Clear inSyscall.
669 for (int tid = 0; tid < numThreads; ++tid)
670 thread[tid]->inSyscall = false;
671
672 // Initialize stages.
673 fetch.initStage();
674 iew.initStage();
675 rename.initStage();
676 commit.initStage();
677
678 commit.setThreads(thread);
679}
680
681template <class Impl>
682void
683FullO3CPU<Impl>::activateThread(ThreadID tid)
684{
685 list<ThreadID>::iterator isActive =
686 std::find(activeThreads.begin(), activeThreads.end(), tid);
687
688 DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid);
689
690 if (isActive == activeThreads.end()) {
691 DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n",
692 tid);
693
694 activeThreads.push_back(tid);
695 }
696}
697
698template <class Impl>
699void
700FullO3CPU<Impl>::deactivateThread(ThreadID tid)
701{
702 //Remove From Active List, if Active
703 list<ThreadID>::iterator thread_it =
704 std::find(activeThreads.begin(), activeThreads.end(), tid);
705
706 DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid);
707
708 if (thread_it != activeThreads.end()) {
709 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
710 tid);
711 activeThreads.erase(thread_it);
712 }
713}
714
715template <class Impl>
716Counter
717FullO3CPU<Impl>::totalInsts() const
718{
719 Counter total(0);
720
721 ThreadID size = thread.size();
722 for (ThreadID i = 0; i < size; i++)
723 total += thread[i]->numInst;
724
725 return total;
726}
727
728template <class Impl>
729Counter
730FullO3CPU<Impl>::totalOps() const
731{
732 Counter total(0);
733
734 ThreadID size = thread.size();
735 for (ThreadID i = 0; i < size; i++)
736 total += thread[i]->numOp;
737
738 return total;
739}
740
741template <class Impl>
742void
743FullO3CPU<Impl>::activateContext(ThreadID tid, int delay)
744{
745 // Needs to set each stage to running as well.
746 if (delay){
747 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate "
748 "on cycle %d\n", tid, curTick() + ticks(delay));
749 scheduleActivateThreadEvent(tid, delay);
750 } else {
751 activateThread(tid);
752 }
753
754 if (lastActivatedCycle < curTick()) {
755 scheduleTickEvent(delay);
756
757 // Be sure to signal that there's some activity so the CPU doesn't
758 // deschedule itself.
759 activityRec.activity();
760 fetch.wakeFromQuiesce();
761
762 quiesceCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
763
764 lastActivatedCycle = curTick();
765
766 _status = Running;
767 }
768}
769
770template <class Impl>
771bool
772FullO3CPU<Impl>::scheduleDeallocateContext(ThreadID tid, bool remove,
773 int delay)
774{
775 // Schedule removal of thread data from CPU
776 if (delay){
777 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate "
778 "on cycle %d\n", tid, curTick() + ticks(delay));
779 scheduleDeallocateContextEvent(tid, remove, delay);
780 return false;
781 } else {
782 deactivateThread(tid);
783 if (remove)
784 removeThread(tid);
785 return true;
786 }
787}
788
789template <class Impl>
790void
791FullO3CPU<Impl>::suspendContext(ThreadID tid)
792{
793 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
794 bool deallocated = scheduleDeallocateContext(tid, false, 1);
795 // If this was the last thread then unschedule the tick event.
796 if ((activeThreads.size() == 1 && !deallocated) ||
797 activeThreads.size() == 0)
798 unscheduleTickEvent();
799
800 DPRINTF(Quiesce, "Suspending Context\n");
801 lastRunningCycle = curTick();
802 _status = Idle;
803}
804
805template <class Impl>
806void
807FullO3CPU<Impl>::haltContext(ThreadID tid)
808{
809 //For now, this is the same as deallocate
810 DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
811 scheduleDeallocateContext(tid, true, 1);
812}
813
814template <class Impl>
815void
816FullO3CPU<Impl>::insertThread(ThreadID tid)
817{
818 DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
819 // Will change now that the PC and thread state is internal to the CPU
820 // and not in the ThreadContext.
821 ThreadContext *src_tc;
822 if (FullSystem)
823 src_tc = system->threadContexts[tid];
824 else
825 src_tc = tcBase(tid);
826
827 //Bind Int Regs to Rename Map
828 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
829 PhysRegIndex phys_reg = freeList.getIntReg();
830
831 renameMap[tid].setEntry(ireg,phys_reg);
832 scoreboard.setReg(phys_reg);
833 }
834
835 //Bind Float Regs to Rename Map
836 for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
837 PhysRegIndex phys_reg = freeList.getFloatReg();
838
839 renameMap[tid].setEntry(freg,phys_reg);
840 scoreboard.setReg(phys_reg);
841 }
842
843 //Copy Thread Data Into RegFile
844 //this->copyFromTC(tid);
845
846 //Set PC/NPC/NNPC
847 pcState(src_tc->pcState(), tid);
848
849 src_tc->setStatus(ThreadContext::Active);
850
851 activateContext(tid,1);
852
853 //Reset ROB/IQ/LSQ Entries
854 commit.rob->resetEntries();
855 iew.resetEntries();
856}
857
858template <class Impl>
859void
860FullO3CPU<Impl>::removeThread(ThreadID tid)
861{
862 DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
863
864 // Copy Thread Data From RegFile
865 // If thread is suspended, it might be re-allocated
866 // this->copyToTC(tid);
867
868
869 // @todo: 2-27-2008: Fix how we free up rename mappings
870 // here to alleviate the case for double-freeing registers
871 // in SMT workloads.
872
873 // Unbind Int Regs from Rename Map
874 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
875 PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
876
877 scoreboard.unsetReg(phys_reg);
878 freeList.addReg(phys_reg);
879 }
880
881 // Unbind Float Regs from Rename Map
882 for (int freg = TheISA::NumIntRegs; freg < TheISA::NumFloatRegs; freg++) {
883 PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
884
885 scoreboard.unsetReg(phys_reg);
886 freeList.addReg(phys_reg);
887 }
888
889 // Squash Throughout Pipeline
890 DynInstPtr inst = commit.rob->readHeadInst(tid);
891 InstSeqNum squash_seq_num = inst->seqNum;
892 fetch.squash(0, squash_seq_num, inst, tid);
893 decode.squash(tid);
894 rename.squash(squash_seq_num, tid);
895 iew.squash(tid);
896 iew.ldstQueue.squash(squash_seq_num, tid);
897 commit.rob->squash(squash_seq_num, tid);
898
899
900 assert(iew.instQueue.getCount(tid) == 0);
901 assert(iew.ldstQueue.getCount(tid) == 0);
902
903 // Reset ROB/IQ/LSQ Entries
904
905 // Commented out for now. This should be possible to do by
906 // telling all the pipeline stages to drain first, and then
907 // checking until the drain completes. Once the pipeline is
908 // drained, call resetEntries(). - 10-09-06 ktlim
909/*
910 if (activeThreads.size() >= 1) {
911 commit.rob->resetEntries();
912 iew.resetEntries();
913 }
914*/
915}
916
917
918template <class Impl>
919void
920FullO3CPU<Impl>::activateWhenReady(ThreadID tid)
921{
922 DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming"
923 "(e.g. PhysRegs/ROB/IQ/LSQ) \n",
924 tid);
925
926 bool ready = true;
927
928 if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) {
929 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
930 "Phys. Int. Regs.\n",
931 tid);
932 ready = false;
933 } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) {
934 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
935 "Phys. Float. Regs.\n",
936 tid);
937 ready = false;
938 } else if (commit.rob->numFreeEntries() >=
939 commit.rob->entryAmount(activeThreads.size() + 1)) {
940 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
941 "ROB entries.\n",
942 tid);
943 ready = false;
944 } else if (iew.instQueue.numFreeEntries() >=
945 iew.instQueue.entryAmount(activeThreads.size() + 1)) {
946 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
947 "IQ entries.\n",
948 tid);
949 ready = false;
950 } else if (iew.ldstQueue.numFreeEntries() >=
951 iew.ldstQueue.entryAmount(activeThreads.size() + 1)) {
952 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
953 "LSQ entries.\n",
954 tid);
955 ready = false;
956 }
957
958 if (ready) {
959 insertThread(tid);
960
961 contextSwitch = false;
962
963 cpuWaitList.remove(tid);
964 } else {
965 suspendContext(tid);
966
967 //blocks fetch
968 contextSwitch = true;
969
970 //@todo: dont always add to waitlist
971 //do waitlist
972 cpuWaitList.push_back(tid);
973 }
974}
975
976template <class Impl>
977Fault
978FullO3CPU<Impl>::hwrei(ThreadID tid)
979{
980#if THE_ISA == ALPHA_ISA
981 // Need to clear the lock flag upon returning from an interrupt.
982 this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
983
984 this->thread[tid]->kernelStats->hwrei();
985
986 // FIXME: XXX check for interrupts? XXX
987#endif
988 return NoFault;
989}
990
991template <class Impl>
992bool
993FullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid)
994{
995#if THE_ISA == ALPHA_ISA
996 if (this->thread[tid]->kernelStats)
997 this->thread[tid]->kernelStats->callpal(palFunc,
998 this->threadContexts[tid]);
999
1000 switch (palFunc) {
1001 case PAL::halt:
1002 halt();
1003 if (--System::numSystemsRunning == 0)
1004 exitSimLoop("all cpus halted");
1005 break;
1006
1007 case PAL::bpt:
1008 case PAL::bugchk:
1009 if (this->system->breakpoint())
1010 return false;
1011 break;
1012 }
1013#endif
1014 return true;
1015}
1016
1017template <class Impl>
1018Fault
1019FullO3CPU<Impl>::getInterrupts()
1020{
1021 // Check if there are any outstanding interrupts
1022 return this->interrupts->getInterrupt(this->threadContexts[0]);
1023}
1024
1025template <class Impl>
1026void
1027FullO3CPU<Impl>::processInterrupts(Fault interrupt)
1028{
1029 // Check for interrupts here. For now can copy the code that
1030 // exists within isa_fullsys_traits.hh. Also assume that thread 0
1031 // is the one that handles the interrupts.
1032 // @todo: Possibly consolidate the interrupt checking code.
1033 // @todo: Allow other threads to handle interrupts.
1034
1035 assert(interrupt != NoFault);
1036 this->interrupts->updateIntrInfo(this->threadContexts[0]);
1037
1038 DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
1039 this->trap(interrupt, 0, NULL);
1040}
1041
1042template <class Impl>
1043void
1044FullO3CPU<Impl>::trap(Fault fault, ThreadID tid, StaticInstPtr inst)
1045{
1046 // Pass the thread's TC into the invoke method.
1047 fault->invoke(this->threadContexts[tid], inst);
1048}
1049
1050template <class Impl>
1051void
1052FullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid)
1053{
1054 DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid);
1055
1056 DPRINTF(Activity,"Activity: syscall() called.\n");
1057
1058 // Temporarily increase this by one to account for the syscall
1059 // instruction.
1060 ++(this->thread[tid]->funcExeInst);
1061
1062 // Execute the actual syscall.
1063 this->thread[tid]->syscall(callnum);
1064
1065 // Decrease funcExeInst by one as the normal commit will handle
1066 // incrementing it.
1067 --(this->thread[tid]->funcExeInst);
1068}
1069
1070template <class Impl>
1071void
1072FullO3CPU<Impl>::serialize(std::ostream &os)
1073{
1074 SimObject::State so_state = SimObject::getState();
1075 SERIALIZE_ENUM(so_state);
1076 BaseCPU::serialize(os);
1077 nameOut(os, csprintf("%s.tickEvent", name()));
1078 tickEvent.serialize(os);
1079
1080 // Use SimpleThread's ability to checkpoint to make it easier to
1081 // write out the registers. Also make this static so it doesn't
1082 // get instantiated multiple times (causes a panic in statistics).
1083 static SimpleThread temp;
1084
1085 ThreadID size = thread.size();
1086 for (ThreadID i = 0; i < size; i++) {
1087 nameOut(os, csprintf("%s.xc.%i", name(), i));
1088 temp.copyTC(thread[i]->getTC());
1089 temp.serialize(os);
1090 }
1091}
1092
1093template <class Impl>
1094void
1095FullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion)
1096{
1097 SimObject::State so_state;
1098 UNSERIALIZE_ENUM(so_state);
1099 BaseCPU::unserialize(cp, section);
1100 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
1101
1102 // Use SimpleThread's ability to checkpoint to make it easier to
1103 // read in the registers. Also make this static so it doesn't
1104 // get instantiated multiple times (causes a panic in statistics).
1105 static SimpleThread temp;
1106
1107 ThreadID size = thread.size();
1108 for (ThreadID i = 0; i < size; i++) {
1109 temp.copyTC(thread[i]->getTC());
1110 temp.unserialize(cp, csprintf("%s.xc.%i", section, i));
1111 thread[i]->getTC()->copyArchRegs(temp.getTC());
1112 }
1113}
1114
1115template <class Impl>
1116unsigned int
1117FullO3CPU<Impl>::drain(Event *drain_event)
1118{
1119 DPRINTF(O3CPU, "Switching out\n");
1120
1121 // If the CPU isn't doing anything, then return immediately.
1122 if (_status == Idle || _status == SwitchedOut) {
1123 return 0;
1124 }
1125
1126 drainCount = 0;
1127 fetch.drain();
1128 decode.drain();
1129 rename.drain();
1130 iew.drain();
1131 commit.drain();
1132
1133 // Wake the CPU and record activity so everything can drain out if
1134 // the CPU was not able to immediately drain.
1135 if (getState() != SimObject::Drained) {
1136 // A bit of a hack...set the drainEvent after all the drain()
1137 // calls have been made, that way if all of the stages drain
1138 // immediately, the signalDrained() function knows not to call
1139 // process on the drain event.
1140 drainEvent = drain_event;
1141
1142 wakeCPU();
1143 activityRec.activity();
1144
1145 return 1;
1146 } else {
1147 return 0;
1148 }
1149}
1150
1151template <class Impl>
1152void
1153FullO3CPU<Impl>::resume()
1154{
1155 fetch.resume();
1156 decode.resume();
1157 rename.resume();
1158 iew.resume();
1159 commit.resume();
1160
1161 changeState(SimObject::Running);
1162
1163 if (_status == SwitchedOut || _status == Idle)
1164 return;
1165
1166 assert(system->getMemoryMode() == Enums::timing);
1167
1168 if (!tickEvent.scheduled())
1169 schedule(tickEvent, nextCycle());
1170 _status = Running;
1171}
1172
1173template <class Impl>
1174void
1175FullO3CPU<Impl>::signalDrained()
1176{
1177 if (++drainCount == NumStages) {
1178 if (tickEvent.scheduled())
1179 tickEvent.squash();
1180
1181 changeState(SimObject::Drained);
1182
1183 BaseCPU::switchOut();
1184
1185 if (drainEvent) {
1186 drainEvent->process();
1187 drainEvent = NULL;
1188 }
1189 }
1190 assert(drainCount <= 5);
1191}
1192
1193template <class Impl>
1194void
1195FullO3CPU<Impl>::switchOut()
1196{
1197 fetch.switchOut();
1198 rename.switchOut();
1199 iew.switchOut();
1200 commit.switchOut();
1201 instList.clear();
1202 while (!removeList.empty()) {
1203 removeList.pop();
1204 }
1205
1206 _status = SwitchedOut;
1207
1208 if (checker)
1209 checker->switchOut();
1210
1211 if (tickEvent.scheduled())
1212 tickEvent.squash();
1213}
1214
1215template <class Impl>
1216void
1217FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
1218{
1219 // Flush out any old data from the time buffers.
1220 for (int i = 0; i < timeBuffer.getSize(); ++i) {
1221 timeBuffer.advance();
1222 fetchQueue.advance();
1223 decodeQueue.advance();
1224 renameQueue.advance();
1225 iewQueue.advance();
1226 }
1227
1228 activityRec.reset();
1229
1230 BaseCPU::takeOverFrom(oldCPU);
1231
1232 fetch.takeOverFrom();
1233 decode.takeOverFrom();
1234 rename.takeOverFrom();
1235 iew.takeOverFrom();
1236 commit.takeOverFrom();
1237
1238 assert(!tickEvent.scheduled() || tickEvent.squashed());
1239
1240 // @todo: Figure out how to properly select the tid to put onto
1241 // the active threads list.
1242 ThreadID tid = 0;
1243
1244 list<ThreadID>::iterator isActive =
1245 std::find(activeThreads.begin(), activeThreads.end(), tid);
1246
1247 if (isActive == activeThreads.end()) {
1248 //May Need to Re-code this if the delay variable is the delay
1249 //needed for thread to activate
1250 DPRINTF(O3CPU, "Adding Thread %i to active threads list\n",
1251 tid);
1252
1253 activeThreads.push_back(tid);
1254 }
1255
1256 // Set all statuses to active, schedule the CPU's tick event.
1257 // @todo: Fix up statuses so this is handled properly
1258 ThreadID size = threadContexts.size();
1259 for (ThreadID i = 0; i < size; ++i) {
1260 ThreadContext *tc = threadContexts[i];
1261 if (tc->status() == ThreadContext::Active && _status != Running) {
1262 _status = Running;
1263 reschedule(tickEvent, nextCycle(), true);
1264 }
1265 }
1266 if (!tickEvent.scheduled())
1267 schedule(tickEvent, nextCycle());
1268
1269 lastRunningCycle = curTick();
1270}
1271
1272template <class Impl>
1273TheISA::MiscReg
1274FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid)
1275{
1276 return this->isa[tid].readMiscRegNoEffect(misc_reg);
1277}
1278
1279template <class Impl>
1280TheISA::MiscReg
1281FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
1282{
1283 miscRegfileReads++;
1284 return this->isa[tid].readMiscReg(misc_reg, tcBase(tid));
1285}
1286
1287template <class Impl>
1288void
1289FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
1290 const TheISA::MiscReg &val, ThreadID tid)
1291{
1292 this->isa[tid].setMiscRegNoEffect(misc_reg, val);
1293}
1294
1295template <class Impl>
1296void
1297FullO3CPU<Impl>::setMiscReg(int misc_reg,
1298 const TheISA::MiscReg &val, ThreadID tid)
1299{
1300 miscRegfileWrites++;
1301 this->isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
1302}
1303
1304template <class Impl>
1305uint64_t
1306FullO3CPU<Impl>::readIntReg(int reg_idx)
1307{
1308 intRegfileReads++;
1309 return regFile.readIntReg(reg_idx);
1310}
1311
1312template <class Impl>
1313FloatReg
1314FullO3CPU<Impl>::readFloatReg(int reg_idx)
1315{
1316 fpRegfileReads++;
1317 return regFile.readFloatReg(reg_idx);
1318}
1319
1320template <class Impl>
1321FloatRegBits
1322FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
1323{
1324 fpRegfileReads++;
1325 return regFile.readFloatRegBits(reg_idx);
1326}
1327
1328template <class Impl>
1329void
1330FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
1331{
1332 intRegfileWrites++;
1333 regFile.setIntReg(reg_idx, val);
1334}
1335
1336template <class Impl>
1337void
1338FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
1339{
1340 fpRegfileWrites++;
1341 regFile.setFloatReg(reg_idx, val);
1342}
1343
1344template <class Impl>
1345void
1346FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
1347{
1348 fpRegfileWrites++;
1349 regFile.setFloatRegBits(reg_idx, val);
1350}
1351
1352template <class Impl>
1353uint64_t
1354FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1355{
1356 intRegfileReads++;
1357 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1358
1359 return regFile.readIntReg(phys_reg);
1360}
1361
1362template <class Impl>
1363float
1364FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
1365{
1366 fpRegfileReads++;
1367 int idx = reg_idx + TheISA::NumIntRegs;
1368 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1369
1370 return regFile.readFloatReg(phys_reg);
1371}
1372
1373template <class Impl>
1374uint64_t
1375FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid)
1376{
1377 fpRegfileReads++;
1378 int idx = reg_idx + TheISA::NumIntRegs;
1379 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1380
1381 return regFile.readFloatRegBits(phys_reg);
1382}
1383
1384template <class Impl>
1385void
1386FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
1387{
1388 intRegfileWrites++;
1389 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1390
1391 regFile.setIntReg(phys_reg, val);
1392}
1393
1394template <class Impl>
1395void
1396FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid)
1397{
1398 fpRegfileWrites++;
1399 int idx = reg_idx + TheISA::NumIntRegs;
1400 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1401
1402 regFile.setFloatReg(phys_reg, val);
1403}
1404
1405template <class Impl>
1406void
1407FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid)
1408{
1409 fpRegfileWrites++;
1410 int idx = reg_idx + TheISA::NumIntRegs;
1411 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1412
1413 regFile.setFloatRegBits(phys_reg, val);
1414}
1415
1416template <class Impl>
1417TheISA::PCState
1418FullO3CPU<Impl>::pcState(ThreadID tid)
1419{
1420 return commit.pcState(tid);
1421}
1422
1423template <class Impl>
1424void
1425FullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid)
1426{
1427 commit.pcState(val, tid);
1428}
1429
1430template <class Impl>
1431Addr
1432FullO3CPU<Impl>::instAddr(ThreadID tid)
1433{
1434 return commit.instAddr(tid);
1435}
1436
1437template <class Impl>
1438Addr
1439FullO3CPU<Impl>::nextInstAddr(ThreadID tid)
1440{
1441 return commit.nextInstAddr(tid);
1442}
1443
1444template <class Impl>
1445MicroPC
1446FullO3CPU<Impl>::microPC(ThreadID tid)
1447{
1448 return commit.microPC(tid);
1449}
1450
1451template <class Impl>
1452void
1453FullO3CPU<Impl>::squashFromTC(ThreadID tid)
1454{
1455 this->thread[tid]->inSyscall = true;
1456 this->commit.generateTCEvent(tid);
1457}
1458
1459template <class Impl>
1460typename FullO3CPU<Impl>::ListIt
1461FullO3CPU<Impl>::addInst(DynInstPtr &inst)
1462{
1463 instList.push_back(inst);
1464
1465 return --(instList.end());
1466}
1467
1468template <class Impl>
1469void
1470FullO3CPU<Impl>::instDone(ThreadID tid, DynInstPtr &inst)
1471{
1472 // Keep an instruction count.
1473 if (!inst->isMicroop() || inst->isLastMicroop()) {
1474 thread[tid]->numInst++;
1475 thread[tid]->numInsts++;
1476 committedInsts[tid]++;
1477 totalCommittedInsts++;
1478 }
1479 thread[tid]->numOp++;
1480 thread[tid]->numOps++;
1481 committedOps[tid]++;
1482
1483 system->totalNumInsts++;
1484 // Check for instruction-count-based events.
1485 comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1486 system->instEventQueue.serviceEvents(system->totalNumInsts);
1487}
1488
1489template <class Impl>
1490void
1491FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
1492{
1493 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s "
1494 "[sn:%lli]\n",
1495 inst->threadNumber, inst->pcState(), inst->seqNum);
1496
1497 removeInstsThisCycle = true;
1498
1499 // Remove the front instruction.
1500 removeList.push(inst->getInstListIt());
1501}
1502
1503template <class Impl>
1504void
1505FullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid)
1506{
1507 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1508 " list.\n", tid);
1509
1510 ListIt end_it;
1511
1512 bool rob_empty = false;
1513
1514 if (instList.empty()) {
1515 return;
1516 } else if (rob.isEmpty(/*tid*/)) {
1517 DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1518 end_it = instList.begin();
1519 rob_empty = true;
1520 } else {
1521 end_it = (rob.readTailInst(tid))->getInstListIt();
1522 DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1523 }
1524
1525 removeInstsThisCycle = true;
1526
1527 ListIt inst_it = instList.end();
1528
1529 inst_it--;
1530
1531 // Walk through the instruction list, removing any instructions
1532 // that were inserted after the given instruction iterator, end_it.
1533 while (inst_it != end_it) {
1534 assert(!instList.empty());
1535
1536 squashInstIt(inst_it, tid);
1537
1538 inst_it--;
1539 }
1540
1541 // If the ROB was empty, then we actually need to remove the first
1542 // instruction as well.
1543 if (rob_empty) {
1544 squashInstIt(inst_it, tid);
1545 }
1546}
1547
1548template <class Impl>
1549void
1550FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1551{
1552 assert(!instList.empty());
1553
1554 removeInstsThisCycle = true;
1555
1556 ListIt inst_iter = instList.end();
1557
1558 inst_iter--;
1559
1560 DPRINTF(O3CPU, "Deleting instructions from instruction "
1561 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1562 tid, seq_num, (*inst_iter)->seqNum);
1563
1564 while ((*inst_iter)->seqNum > seq_num) {
1565
1566 bool break_loop = (inst_iter == instList.begin());
1567
1568 squashInstIt(inst_iter, tid);
1569
1570 inst_iter--;
1571
1572 if (break_loop)
1573 break;
1574 }
1575}
1576
1577template <class Impl>
1578inline void
1579FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid)
1580{
1581 if ((*instIt)->threadNumber == tid) {
1582 DPRINTF(O3CPU, "Squashing instruction, "
1583 "[tid:%i] [sn:%lli] PC %s\n",
1584 (*instIt)->threadNumber,
1585 (*instIt)->seqNum,
1586 (*instIt)->pcState());
1587
1588 // Mark it as squashed.
1589 (*instIt)->setSquashed();
1590
1591 // @todo: Formulate a consistent method for deleting
1592 // instructions from the instruction list
1593 // Remove the instruction from the list.
1594 removeList.push(instIt);
1595 }
1596}
1597
1598template <class Impl>
1599void
1600FullO3CPU<Impl>::cleanUpRemovedInsts()
1601{
1602 while (!removeList.empty()) {
1603 DPRINTF(O3CPU, "Removing instruction, "
1604 "[tid:%i] [sn:%lli] PC %s\n",
1605 (*removeList.front())->threadNumber,
1606 (*removeList.front())->seqNum,
1607 (*removeList.front())->pcState());
1608
1609 instList.erase(removeList.front());
1610
1611 removeList.pop();
1612 }
1613
1614 removeInstsThisCycle = false;
1615}
1616/*
1617template <class Impl>
1618void
1619FullO3CPU<Impl>::removeAllInsts()
1620{
1621 instList.clear();
1622}
1623*/
1624template <class Impl>
1625void
1626FullO3CPU<Impl>::dumpInsts()
1627{
1628 int num = 0;
1629
1630 ListIt inst_list_it = instList.begin();
1631
1632 cprintf("Dumping Instruction List\n");
1633
1634 while (inst_list_it != instList.end()) {
1635 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1636 "Squashed:%i\n\n",
1637 num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber,
1638 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1639 (*inst_list_it)->isSquashed());
1640 inst_list_it++;
1641 ++num;
1642 }
1643}
1644/*
1645template <class Impl>
1646void
1647FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
1648{
1649 iew.wakeDependents(inst);
1650}
1651*/
1652template <class Impl>
1653void
1654FullO3CPU<Impl>::wakeCPU()
1655{
1656 if (activityRec.active() || tickEvent.scheduled()) {
1657 DPRINTF(Activity, "CPU already running.\n");
1658 return;
1659 }
1660
1661 DPRINTF(Activity, "Waking up CPU\n");
1662
1663 idleCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
1664 numCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
1665
1666 schedule(tickEvent, nextCycle());
1667}
1668
1669template <class Impl>
1670void
1671FullO3CPU<Impl>::wakeup()
1672{
1673 if (this->thread[0]->status() != ThreadContext::Suspended)
1674 return;
1675
1676 this->wakeCPU();
1677
1678 DPRINTF(Quiesce, "Suspended Processor woken\n");
1679 this->threadContexts[0]->activate();
1680}
1681
1682template <class Impl>
1683ThreadID
1684FullO3CPU<Impl>::getFreeTid()
1685{
1686 for (ThreadID tid = 0; tid < numThreads; tid++) {
1687 if (!tids[tid]) {
1688 tids[tid] = true;
1689 return tid;
1690 }
1691 }
1692
1693 return InvalidThreadID;
1694}
1695
1696template <class Impl>
1697void
1698FullO3CPU<Impl>::doContextSwitch()
1699{
1700 if (contextSwitch) {
1701
1702 //ADD CODE TO DEACTIVE THREAD HERE (???)
1703
1704 ThreadID size = cpuWaitList.size();
1705 for (ThreadID tid = 0; tid < size; tid++) {
1706 activateWhenReady(tid);
1707 }
1708
1709 if (cpuWaitList.size() == 0)
1710 contextSwitch = true;
1711 }
1712}
1713
1714template <class Impl>
1715void
1716FullO3CPU<Impl>::updateThreadPriority()
1717{
1718 if (activeThreads.size() > 1) {
1719 //DEFAULT TO ROUND ROBIN SCHEME
1720 //e.g. Move highest priority to end of thread list
1721 list<ThreadID>::iterator list_begin = activeThreads.begin();
1722
1723 unsigned high_thread = *list_begin;
1724
1725 activeThreads.erase(list_begin);
1726
1727 activeThreads.push_back(high_thread);
1728 }
1729}
1730
1731// Forward declaration of FullO3CPU.
1732template class FullO3CPU<O3CPUImpl>;
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