1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 * Korey Sewell
43 * Rick Strong
44 */
45
46#include "arch/kernel_stats.hh"
47#include "config/the_isa.hh"
| 1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 * Korey Sewell
43 * Rick Strong
44 */
45
46#include "arch/kernel_stats.hh"
47#include "config/the_isa.hh"
|
48#include "config/use_checker.hh"
| 48#include "cpu/checker/cpu.hh"
49#include "cpu/checker/thread_context.hh"
|
49#include "cpu/o3/cpu.hh"
50#include "cpu/o3/isa_specific.hh"
51#include "cpu/o3/thread_context.hh"
52#include "cpu/activity.hh"
53#include "cpu/quiesce_event.hh"
54#include "cpu/simple_thread.hh"
55#include "cpu/thread_context.hh"
56#include "debug/Activity.hh"
57#include "debug/O3CPU.hh"
58#include "debug/Quiesce.hh"
59#include "enums/MemoryMode.hh"
60#include "sim/core.hh"
61#include "sim/full_system.hh"
62#include "sim/process.hh"
63#include "sim/stat_control.hh"
64#include "sim/system.hh"
65
| 50#include "cpu/o3/cpu.hh"
51#include "cpu/o3/isa_specific.hh"
52#include "cpu/o3/thread_context.hh"
53#include "cpu/activity.hh"
54#include "cpu/quiesce_event.hh"
55#include "cpu/simple_thread.hh"
56#include "cpu/thread_context.hh"
57#include "debug/Activity.hh"
58#include "debug/O3CPU.hh"
59#include "debug/Quiesce.hh"
60#include "enums/MemoryMode.hh"
61#include "sim/core.hh"
62#include "sim/full_system.hh"
63#include "sim/process.hh"
64#include "sim/stat_control.hh"
65#include "sim/system.hh"
66
|
66#if USE_CHECKER
67#include "cpu/checker/cpu.hh"
68#include "cpu/checker/thread_context.hh"
69#endif
70
| |
71#if THE_ISA == ALPHA_ISA
72#include "arch/alpha/osfpal.hh"
73#include "debug/Activity.hh"
74#endif
75
76struct BaseCPUParams;
77
78using namespace TheISA;
79using namespace std;
80
81BaseO3CPU::BaseO3CPU(BaseCPUParams *params)
82 : BaseCPU(params)
83{
84}
85
86void
87BaseO3CPU::regStats()
88{
89 BaseCPU::regStats();
90}
91
92template<class Impl>
93bool
94FullO3CPU<Impl>::IcachePort::recvTiming(PacketPtr pkt)
95{
96 DPRINTF(O3CPU, "Fetch unit received timing\n");
97 if (pkt->isResponse()) {
98 // We shouldn't ever get a block in ownership state
99 assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted()));
100
101 fetch->processCacheCompletion(pkt);
102 }
103 //else Snooped a coherence request, just return
104 return true;
105}
106
107template<class Impl>
108void
109FullO3CPU<Impl>::IcachePort::recvRetry()
110{
111 fetch->recvRetry();
112}
113
114template <class Impl>
115bool
116FullO3CPU<Impl>::DcachePort::recvTiming(PacketPtr pkt)
117{
118 return lsq->recvTiming(pkt);
119}
120
121template <class Impl>
122void
123FullO3CPU<Impl>::DcachePort::recvRetry()
124{
125 lsq->recvRetry();
126}
127
128template <class Impl>
129FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
130 : Event(CPU_Tick_Pri), cpu(c)
131{
132}
133
134template <class Impl>
135void
136FullO3CPU<Impl>::TickEvent::process()
137{
138 cpu->tick();
139}
140
141template <class Impl>
142const char *
143FullO3CPU<Impl>::TickEvent::description() const
144{
145 return "FullO3CPU tick";
146}
147
148template <class Impl>
149FullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent()
150 : Event(CPU_Switch_Pri)
151{
152}
153
154template <class Impl>
155void
156FullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num,
157 FullO3CPU<Impl> *thread_cpu)
158{
159 tid = thread_num;
160 cpu = thread_cpu;
161}
162
163template <class Impl>
164void
165FullO3CPU<Impl>::ActivateThreadEvent::process()
166{
167 cpu->activateThread(tid);
168}
169
170template <class Impl>
171const char *
172FullO3CPU<Impl>::ActivateThreadEvent::description() const
173{
174 return "FullO3CPU \"Activate Thread\"";
175}
176
177template <class Impl>
178FullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent()
179 : Event(CPU_Tick_Pri), tid(0), remove(false), cpu(NULL)
180{
181}
182
183template <class Impl>
184void
185FullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num,
186 FullO3CPU<Impl> *thread_cpu)
187{
188 tid = thread_num;
189 cpu = thread_cpu;
190 remove = false;
191}
192
193template <class Impl>
194void
195FullO3CPU<Impl>::DeallocateContextEvent::process()
196{
197 cpu->deactivateThread(tid);
198 if (remove)
199 cpu->removeThread(tid);
200}
201
202template <class Impl>
203const char *
204FullO3CPU<Impl>::DeallocateContextEvent::description() const
205{
206 return "FullO3CPU \"Deallocate Context\"";
207}
208
209template <class Impl>
210FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
211 : BaseO3CPU(params),
212 itb(params->itb),
213 dtb(params->dtb),
214 tickEvent(this),
215#ifndef NDEBUG
216 instcount(0),
217#endif
218 removeInstsThisCycle(false),
219 fetch(this, params),
220 decode(this, params),
221 rename(this, params),
222 iew(this, params),
223 commit(this, params),
224
225 regFile(this, params->numPhysIntRegs,
226 params->numPhysFloatRegs),
227
228 freeList(params->numThreads,
229 TheISA::NumIntRegs, params->numPhysIntRegs,
230 TheISA::NumFloatRegs, params->numPhysFloatRegs),
231
232 rob(this,
233 params->numROBEntries, params->squashWidth,
234 params->smtROBPolicy, params->smtROBThreshold,
235 params->numThreads),
236
237 scoreboard(params->numThreads,
238 TheISA::NumIntRegs, params->numPhysIntRegs,
239 TheISA::NumFloatRegs, params->numPhysFloatRegs,
240 TheISA::NumMiscRegs * numThreads,
241 TheISA::ZeroReg),
242
243 icachePort(&fetch, this),
244 dcachePort(&iew.ldstQueue, this),
245
246 timeBuffer(params->backComSize, params->forwardComSize),
247 fetchQueue(params->backComSize, params->forwardComSize),
248 decodeQueue(params->backComSize, params->forwardComSize),
249 renameQueue(params->backComSize, params->forwardComSize),
250 iewQueue(params->backComSize, params->forwardComSize),
251 activityRec(name(), NumStages,
252 params->backComSize + params->forwardComSize,
253 params->activity),
254
255 globalSeqNum(1),
256 system(params->system),
257 drainCount(0),
258 deferRegistration(params->defer_registration)
259{
260 if (!deferRegistration) {
261 _status = Running;
262 } else {
263 _status = Idle;
264 }
265
| 67#if THE_ISA == ALPHA_ISA
68#include "arch/alpha/osfpal.hh"
69#include "debug/Activity.hh"
70#endif
71
72struct BaseCPUParams;
73
74using namespace TheISA;
75using namespace std;
76
77BaseO3CPU::BaseO3CPU(BaseCPUParams *params)
78 : BaseCPU(params)
79{
80}
81
82void
83BaseO3CPU::regStats()
84{
85 BaseCPU::regStats();
86}
87
88template<class Impl>
89bool
90FullO3CPU<Impl>::IcachePort::recvTiming(PacketPtr pkt)
91{
92 DPRINTF(O3CPU, "Fetch unit received timing\n");
93 if (pkt->isResponse()) {
94 // We shouldn't ever get a block in ownership state
95 assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted()));
96
97 fetch->processCacheCompletion(pkt);
98 }
99 //else Snooped a coherence request, just return
100 return true;
101}
102
103template<class Impl>
104void
105FullO3CPU<Impl>::IcachePort::recvRetry()
106{
107 fetch->recvRetry();
108}
109
110template <class Impl>
111bool
112FullO3CPU<Impl>::DcachePort::recvTiming(PacketPtr pkt)
113{
114 return lsq->recvTiming(pkt);
115}
116
117template <class Impl>
118void
119FullO3CPU<Impl>::DcachePort::recvRetry()
120{
121 lsq->recvRetry();
122}
123
124template <class Impl>
125FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
126 : Event(CPU_Tick_Pri), cpu(c)
127{
128}
129
130template <class Impl>
131void
132FullO3CPU<Impl>::TickEvent::process()
133{
134 cpu->tick();
135}
136
137template <class Impl>
138const char *
139FullO3CPU<Impl>::TickEvent::description() const
140{
141 return "FullO3CPU tick";
142}
143
144template <class Impl>
145FullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent()
146 : Event(CPU_Switch_Pri)
147{
148}
149
150template <class Impl>
151void
152FullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num,
153 FullO3CPU<Impl> *thread_cpu)
154{
155 tid = thread_num;
156 cpu = thread_cpu;
157}
158
159template <class Impl>
160void
161FullO3CPU<Impl>::ActivateThreadEvent::process()
162{
163 cpu->activateThread(tid);
164}
165
166template <class Impl>
167const char *
168FullO3CPU<Impl>::ActivateThreadEvent::description() const
169{
170 return "FullO3CPU \"Activate Thread\"";
171}
172
173template <class Impl>
174FullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent()
175 : Event(CPU_Tick_Pri), tid(0), remove(false), cpu(NULL)
176{
177}
178
179template <class Impl>
180void
181FullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num,
182 FullO3CPU<Impl> *thread_cpu)
183{
184 tid = thread_num;
185 cpu = thread_cpu;
186 remove = false;
187}
188
189template <class Impl>
190void
191FullO3CPU<Impl>::DeallocateContextEvent::process()
192{
193 cpu->deactivateThread(tid);
194 if (remove)
195 cpu->removeThread(tid);
196}
197
198template <class Impl>
199const char *
200FullO3CPU<Impl>::DeallocateContextEvent::description() const
201{
202 return "FullO3CPU \"Deallocate Context\"";
203}
204
205template <class Impl>
206FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
207 : BaseO3CPU(params),
208 itb(params->itb),
209 dtb(params->dtb),
210 tickEvent(this),
211#ifndef NDEBUG
212 instcount(0),
213#endif
214 removeInstsThisCycle(false),
215 fetch(this, params),
216 decode(this, params),
217 rename(this, params),
218 iew(this, params),
219 commit(this, params),
220
221 regFile(this, params->numPhysIntRegs,
222 params->numPhysFloatRegs),
223
224 freeList(params->numThreads,
225 TheISA::NumIntRegs, params->numPhysIntRegs,
226 TheISA::NumFloatRegs, params->numPhysFloatRegs),
227
228 rob(this,
229 params->numROBEntries, params->squashWidth,
230 params->smtROBPolicy, params->smtROBThreshold,
231 params->numThreads),
232
233 scoreboard(params->numThreads,
234 TheISA::NumIntRegs, params->numPhysIntRegs,
235 TheISA::NumFloatRegs, params->numPhysFloatRegs,
236 TheISA::NumMiscRegs * numThreads,
237 TheISA::ZeroReg),
238
239 icachePort(&fetch, this),
240 dcachePort(&iew.ldstQueue, this),
241
242 timeBuffer(params->backComSize, params->forwardComSize),
243 fetchQueue(params->backComSize, params->forwardComSize),
244 decodeQueue(params->backComSize, params->forwardComSize),
245 renameQueue(params->backComSize, params->forwardComSize),
246 iewQueue(params->backComSize, params->forwardComSize),
247 activityRec(name(), NumStages,
248 params->backComSize + params->forwardComSize,
249 params->activity),
250
251 globalSeqNum(1),
252 system(params->system),
253 drainCount(0),
254 deferRegistration(params->defer_registration)
255{
256 if (!deferRegistration) {
257 _status = Running;
258 } else {
259 _status = Idle;
260 }
261
|
266#if USE_CHECKER
| |
267 if (params->checker) {
268 BaseCPU *temp_checker = params->checker;
269 checker = dynamic_cast<Checker<Impl> *>(temp_checker);
270 checker->setIcachePort(&icachePort);
271 checker->setSystem(params->system);
272 } else {
273 checker = NULL;
274 }
| 262 if (params->checker) {
263 BaseCPU *temp_checker = params->checker;
264 checker = dynamic_cast<Checker<Impl> *>(temp_checker);
265 checker->setIcachePort(&icachePort);
266 checker->setSystem(params->system);
267 } else {
268 checker = NULL;
269 }
|
275#endif // USE_CHECKER
| |
276
277 if (!FullSystem) {
278 thread.resize(numThreads);
279 tids.resize(numThreads);
280 }
281
282 // The stages also need their CPU pointer setup. However this
283 // must be done at the upper level CPU because they have pointers
284 // to the upper level CPU, and not this FullO3CPU.
285
286 // Set up Pointers to the activeThreads list for each stage
287 fetch.setActiveThreads(&activeThreads);
288 decode.setActiveThreads(&activeThreads);
289 rename.setActiveThreads(&activeThreads);
290 iew.setActiveThreads(&activeThreads);
291 commit.setActiveThreads(&activeThreads);
292
293 // Give each of the stages the time buffer they will use.
294 fetch.setTimeBuffer(&timeBuffer);
295 decode.setTimeBuffer(&timeBuffer);
296 rename.setTimeBuffer(&timeBuffer);
297 iew.setTimeBuffer(&timeBuffer);
298 commit.setTimeBuffer(&timeBuffer);
299
300 // Also setup each of the stages' queues.
301 fetch.setFetchQueue(&fetchQueue);
302 decode.setFetchQueue(&fetchQueue);
303 commit.setFetchQueue(&fetchQueue);
304 decode.setDecodeQueue(&decodeQueue);
305 rename.setDecodeQueue(&decodeQueue);
306 rename.setRenameQueue(&renameQueue);
307 iew.setRenameQueue(&renameQueue);
308 iew.setIEWQueue(&iewQueue);
309 commit.setIEWQueue(&iewQueue);
310 commit.setRenameQueue(&renameQueue);
311
312 commit.setIEWStage(&iew);
313 rename.setIEWStage(&iew);
314 rename.setCommitStage(&commit);
315
316 ThreadID active_threads;
317 if (FullSystem) {
318 active_threads = 1;
319 } else {
320 active_threads = params->workload.size();
321
322 if (active_threads > Impl::MaxThreads) {
323 panic("Workload Size too large. Increase the 'MaxThreads' "
324 "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) "
325 "or edit your workload size.");
326 }
327 }
328
329 //Make Sure That this a Valid Architeture
330 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs);
331 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
332
333 rename.setScoreboard(&scoreboard);
334 iew.setScoreboard(&scoreboard);
335
336 // Setup the rename map for whichever stages need it.
337 PhysRegIndex lreg_idx = 0;
338 PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs
339
340 for (ThreadID tid = 0; tid < numThreads; tid++) {
341 bool bindRegs = (tid <= active_threads - 1);
342
343 commitRenameMap[tid].init(TheISA::NumIntRegs,
344 params->numPhysIntRegs,
345 lreg_idx, //Index for Logical. Regs
346
347 TheISA::NumFloatRegs,
348 params->numPhysFloatRegs,
349 freg_idx, //Index for Float Regs
350
351 TheISA::NumMiscRegs,
352
353 TheISA::ZeroReg,
354 TheISA::ZeroReg,
355
356 tid,
357 false);
358
359 renameMap[tid].init(TheISA::NumIntRegs,
360 params->numPhysIntRegs,
361 lreg_idx, //Index for Logical. Regs
362
363 TheISA::NumFloatRegs,
364 params->numPhysFloatRegs,
365 freg_idx, //Index for Float Regs
366
367 TheISA::NumMiscRegs,
368
369 TheISA::ZeroReg,
370 TheISA::ZeroReg,
371
372 tid,
373 bindRegs);
374
375 activateThreadEvent[tid].init(tid, this);
376 deallocateContextEvent[tid].init(tid, this);
377 }
378
379 rename.setRenameMap(renameMap);
380 commit.setRenameMap(commitRenameMap);
381
382 // Give renameMap & rename stage access to the freeList;
383 for (ThreadID tid = 0; tid < numThreads; tid++)
384 renameMap[tid].setFreeList(&freeList);
385 rename.setFreeList(&freeList);
386
387 // Setup the ROB for whichever stages need it.
388 commit.setROB(&rob);
389
390 lastRunningCycle = curTick();
391
392 lastActivatedCycle = -1;
393#if 0
394 // Give renameMap & rename stage access to the freeList;
395 for (ThreadID tid = 0; tid < numThreads; tid++)
396 globalSeqNum[tid] = 1;
397#endif
398
399 contextSwitch = false;
400 DPRINTF(O3CPU, "Creating O3CPU object.\n");
401
402 // Setup any thread state.
403 this->thread.resize(this->numThreads);
404
405 for (ThreadID tid = 0; tid < this->numThreads; ++tid) {
406 if (FullSystem) {
407 // SMT is not supported in FS mode yet.
408 assert(this->numThreads == 1);
409 this->thread[tid] = new Thread(this, 0, NULL);
410 } else {
411 if (tid < params->workload.size()) {
412 DPRINTF(O3CPU, "Workload[%i] process is %#x",
413 tid, this->thread[tid]);
414 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
415 (typename Impl::O3CPU *)(this),
416 tid, params->workload[tid]);
417
418 //usedTids[tid] = true;
419 //threadMap[tid] = tid;
420 } else {
421 //Allocate Empty thread so M5 can use later
422 //when scheduling threads to CPU
423 Process* dummy_proc = NULL;
424
425 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
426 (typename Impl::O3CPU *)(this),
427 tid, dummy_proc);
428 //usedTids[tid] = false;
429 }
430 }
431
432 ThreadContext *tc;
433
434 // Setup the TC that will serve as the interface to the threads/CPU.
435 O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>;
436
437 tc = o3_tc;
438
439 // If we're using a checker, then the TC should be the
440 // CheckerThreadContext.
| 270
271 if (!FullSystem) {
272 thread.resize(numThreads);
273 tids.resize(numThreads);
274 }
275
276 // The stages also need their CPU pointer setup. However this
277 // must be done at the upper level CPU because they have pointers
278 // to the upper level CPU, and not this FullO3CPU.
279
280 // Set up Pointers to the activeThreads list for each stage
281 fetch.setActiveThreads(&activeThreads);
282 decode.setActiveThreads(&activeThreads);
283 rename.setActiveThreads(&activeThreads);
284 iew.setActiveThreads(&activeThreads);
285 commit.setActiveThreads(&activeThreads);
286
287 // Give each of the stages the time buffer they will use.
288 fetch.setTimeBuffer(&timeBuffer);
289 decode.setTimeBuffer(&timeBuffer);
290 rename.setTimeBuffer(&timeBuffer);
291 iew.setTimeBuffer(&timeBuffer);
292 commit.setTimeBuffer(&timeBuffer);
293
294 // Also setup each of the stages' queues.
295 fetch.setFetchQueue(&fetchQueue);
296 decode.setFetchQueue(&fetchQueue);
297 commit.setFetchQueue(&fetchQueue);
298 decode.setDecodeQueue(&decodeQueue);
299 rename.setDecodeQueue(&decodeQueue);
300 rename.setRenameQueue(&renameQueue);
301 iew.setRenameQueue(&renameQueue);
302 iew.setIEWQueue(&iewQueue);
303 commit.setIEWQueue(&iewQueue);
304 commit.setRenameQueue(&renameQueue);
305
306 commit.setIEWStage(&iew);
307 rename.setIEWStage(&iew);
308 rename.setCommitStage(&commit);
309
310 ThreadID active_threads;
311 if (FullSystem) {
312 active_threads = 1;
313 } else {
314 active_threads = params->workload.size();
315
316 if (active_threads > Impl::MaxThreads) {
317 panic("Workload Size too large. Increase the 'MaxThreads' "
318 "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) "
319 "or edit your workload size.");
320 }
321 }
322
323 //Make Sure That this a Valid Architeture
324 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs);
325 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
326
327 rename.setScoreboard(&scoreboard);
328 iew.setScoreboard(&scoreboard);
329
330 // Setup the rename map for whichever stages need it.
331 PhysRegIndex lreg_idx = 0;
332 PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs
333
334 for (ThreadID tid = 0; tid < numThreads; tid++) {
335 bool bindRegs = (tid <= active_threads - 1);
336
337 commitRenameMap[tid].init(TheISA::NumIntRegs,
338 params->numPhysIntRegs,
339 lreg_idx, //Index for Logical. Regs
340
341 TheISA::NumFloatRegs,
342 params->numPhysFloatRegs,
343 freg_idx, //Index for Float Regs
344
345 TheISA::NumMiscRegs,
346
347 TheISA::ZeroReg,
348 TheISA::ZeroReg,
349
350 tid,
351 false);
352
353 renameMap[tid].init(TheISA::NumIntRegs,
354 params->numPhysIntRegs,
355 lreg_idx, //Index for Logical. Regs
356
357 TheISA::NumFloatRegs,
358 params->numPhysFloatRegs,
359 freg_idx, //Index for Float Regs
360
361 TheISA::NumMiscRegs,
362
363 TheISA::ZeroReg,
364 TheISA::ZeroReg,
365
366 tid,
367 bindRegs);
368
369 activateThreadEvent[tid].init(tid, this);
370 deallocateContextEvent[tid].init(tid, this);
371 }
372
373 rename.setRenameMap(renameMap);
374 commit.setRenameMap(commitRenameMap);
375
376 // Give renameMap & rename stage access to the freeList;
377 for (ThreadID tid = 0; tid < numThreads; tid++)
378 renameMap[tid].setFreeList(&freeList);
379 rename.setFreeList(&freeList);
380
381 // Setup the ROB for whichever stages need it.
382 commit.setROB(&rob);
383
384 lastRunningCycle = curTick();
385
386 lastActivatedCycle = -1;
387#if 0
388 // Give renameMap & rename stage access to the freeList;
389 for (ThreadID tid = 0; tid < numThreads; tid++)
390 globalSeqNum[tid] = 1;
391#endif
392
393 contextSwitch = false;
394 DPRINTF(O3CPU, "Creating O3CPU object.\n");
395
396 // Setup any thread state.
397 this->thread.resize(this->numThreads);
398
399 for (ThreadID tid = 0; tid < this->numThreads; ++tid) {
400 if (FullSystem) {
401 // SMT is not supported in FS mode yet.
402 assert(this->numThreads == 1);
403 this->thread[tid] = new Thread(this, 0, NULL);
404 } else {
405 if (tid < params->workload.size()) {
406 DPRINTF(O3CPU, "Workload[%i] process is %#x",
407 tid, this->thread[tid]);
408 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
409 (typename Impl::O3CPU *)(this),
410 tid, params->workload[tid]);
411
412 //usedTids[tid] = true;
413 //threadMap[tid] = tid;
414 } else {
415 //Allocate Empty thread so M5 can use later
416 //when scheduling threads to CPU
417 Process* dummy_proc = NULL;
418
419 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
420 (typename Impl::O3CPU *)(this),
421 tid, dummy_proc);
422 //usedTids[tid] = false;
423 }
424 }
425
426 ThreadContext *tc;
427
428 // Setup the TC that will serve as the interface to the threads/CPU.
429 O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>;
430
431 tc = o3_tc;
432
433 // If we're using a checker, then the TC should be the
434 // CheckerThreadContext.
|
441#if USE_CHECKER
| |
442 if (params->checker) {
443 tc = new CheckerThreadContext<O3ThreadContext<Impl> >(
444 o3_tc, this->checker);
445 }
| 435 if (params->checker) {
436 tc = new CheckerThreadContext<O3ThreadContext<Impl> >(
437 o3_tc, this->checker);
438 }
|
446#endif
| |
447
448 o3_tc->cpu = (typename Impl::O3CPU *)(this);
449 assert(o3_tc->cpu);
450 o3_tc->thread = this->thread[tid];
451
452 if (FullSystem) {
453 // Setup quiesce event.
454 this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
455 }
456 // Give the thread the TC.
457 this->thread[tid]->tc = tc;
458
459 // Add the TC to the CPU's list of TC's.
460 this->threadContexts.push_back(tc);
461 }
462
463 // FullO3CPU always requires an interrupt controller.
464 if (!params->defer_registration && !interrupts) {
465 fatal("FullO3CPU %s has no interrupt controller.\n"
466 "Ensure createInterruptController() is called.\n", name());
467 }
468
469 for (ThreadID tid = 0; tid < this->numThreads; tid++)
470 this->thread[tid]->setFuncExeInst(0);
471
472 lockAddr = 0;
473 lockFlag = false;
474}
475
476template <class Impl>
477FullO3CPU<Impl>::~FullO3CPU()
478{
479}
480
481template <class Impl>
482void
483FullO3CPU<Impl>::regStats()
484{
485 BaseO3CPU::regStats();
486
487 // Register any of the O3CPU's stats here.
488 timesIdled
489 .name(name() + ".timesIdled")
490 .desc("Number of times that the entire CPU went into an idle state and"
491 " unscheduled itself")
492 .prereq(timesIdled);
493
494 idleCycles
495 .name(name() + ".idleCycles")
496 .desc("Total number of cycles that the CPU has spent unscheduled due "
497 "to idling")
498 .prereq(idleCycles);
499
500 quiesceCycles
501 .name(name() + ".quiesceCycles")
502 .desc("Total number of cycles that CPU has spent quiesced or waiting "
503 "for an interrupt")
504 .prereq(quiesceCycles);
505
506 // Number of Instructions simulated
507 // --------------------------------
508 // Should probably be in Base CPU but need templated
509 // MaxThreads so put in here instead
510 committedInsts
511 .init(numThreads)
512 .name(name() + ".committedInsts")
513 .desc("Number of Instructions Simulated");
514
515 committedOps
516 .init(numThreads)
517 .name(name() + ".committedOps")
518 .desc("Number of Ops (including micro ops) Simulated");
519
520 totalCommittedInsts
521 .name(name() + ".committedInsts_total")
522 .desc("Number of Instructions Simulated");
523
524 cpi
525 .name(name() + ".cpi")
526 .desc("CPI: Cycles Per Instruction")
527 .precision(6);
528 cpi = numCycles / committedInsts;
529
530 totalCpi
531 .name(name() + ".cpi_total")
532 .desc("CPI: Total CPI of All Threads")
533 .precision(6);
534 totalCpi = numCycles / totalCommittedInsts;
535
536 ipc
537 .name(name() + ".ipc")
538 .desc("IPC: Instructions Per Cycle")
539 .precision(6);
540 ipc = committedInsts / numCycles;
541
542 totalIpc
543 .name(name() + ".ipc_total")
544 .desc("IPC: Total IPC of All Threads")
545 .precision(6);
546 totalIpc = totalCommittedInsts / numCycles;
547
548 this->fetch.regStats();
549 this->decode.regStats();
550 this->rename.regStats();
551 this->iew.regStats();
552 this->commit.regStats();
553 this->rob.regStats();
554
555 intRegfileReads
556 .name(name() + ".int_regfile_reads")
557 .desc("number of integer regfile reads")
558 .prereq(intRegfileReads);
559
560 intRegfileWrites
561 .name(name() + ".int_regfile_writes")
562 .desc("number of integer regfile writes")
563 .prereq(intRegfileWrites);
564
565 fpRegfileReads
566 .name(name() + ".fp_regfile_reads")
567 .desc("number of floating regfile reads")
568 .prereq(fpRegfileReads);
569
570 fpRegfileWrites
571 .name(name() + ".fp_regfile_writes")
572 .desc("number of floating regfile writes")
573 .prereq(fpRegfileWrites);
574
575 miscRegfileReads
576 .name(name() + ".misc_regfile_reads")
577 .desc("number of misc regfile reads")
578 .prereq(miscRegfileReads);
579
580 miscRegfileWrites
581 .name(name() + ".misc_regfile_writes")
582 .desc("number of misc regfile writes")
583 .prereq(miscRegfileWrites);
584}
585
586template <class Impl>
587void
588FullO3CPU<Impl>::tick()
589{
590 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
591
592 ++numCycles;
593
594// activity = false;
595
596 //Tick each of the stages
597 fetch.tick();
598
599 decode.tick();
600
601 rename.tick();
602
603 iew.tick();
604
605 commit.tick();
606
607 if (!FullSystem)
608 doContextSwitch();
609
610 // Now advance the time buffers
611 timeBuffer.advance();
612
613 fetchQueue.advance();
614 decodeQueue.advance();
615 renameQueue.advance();
616 iewQueue.advance();
617
618 activityRec.advance();
619
620 if (removeInstsThisCycle) {
621 cleanUpRemovedInsts();
622 }
623
624 if (!tickEvent.scheduled()) {
625 if (_status == SwitchedOut ||
626 getState() == SimObject::Drained) {
627 DPRINTF(O3CPU, "Switched out!\n");
628 // increment stat
629 lastRunningCycle = curTick();
630 } else if (!activityRec.active() || _status == Idle) {
631 DPRINTF(O3CPU, "Idle!\n");
632 lastRunningCycle = curTick();
633 timesIdled++;
634 } else {
635 schedule(tickEvent, nextCycle(curTick() + ticks(1)));
636 DPRINTF(O3CPU, "Scheduling next tick!\n");
637 }
638 }
639
640 if (!FullSystem)
641 updateThreadPriority();
642}
643
644template <class Impl>
645void
646FullO3CPU<Impl>::init()
647{
648 BaseCPU::init();
649
650 // Set inSyscall so that the CPU doesn't squash when initially
651 // setting up registers.
652 for (ThreadID tid = 0; tid < numThreads; ++tid)
653 thread[tid]->inSyscall = true;
654
655 // this CPU could still be unconnected if we are restoring from a
656 // checkpoint and this CPU is to be switched in, thus we can only
657 // do this here if the instruction port is actually connected, if
658 // not we have to do it as part of takeOverFrom
659 if (icachePort.isConnected())
660 fetch.setIcache();
661
662 if (FullSystem && !params()->defer_registration) {
663 for (ThreadID tid = 0; tid < numThreads; tid++) {
664 ThreadContext *src_tc = threadContexts[tid];
665 TheISA::initCPU(src_tc, src_tc->contextId());
666 // Initialise the ThreadContext's memory proxies
667 thread[tid]->initMemProxies(thread[tid]->getTC());
668 }
669 }
670
671 // Clear inSyscall.
672 for (int tid = 0; tid < numThreads; ++tid)
673 thread[tid]->inSyscall = false;
674
675 // Initialize stages.
676 fetch.initStage();
677 iew.initStage();
678 rename.initStage();
679 commit.initStage();
680
681 commit.setThreads(thread);
682}
683
684template <class Impl>
685void
686FullO3CPU<Impl>::activateThread(ThreadID tid)
687{
688 list<ThreadID>::iterator isActive =
689 std::find(activeThreads.begin(), activeThreads.end(), tid);
690
691 DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid);
692
693 if (isActive == activeThreads.end()) {
694 DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n",
695 tid);
696
697 activeThreads.push_back(tid);
698 }
699}
700
701template <class Impl>
702void
703FullO3CPU<Impl>::deactivateThread(ThreadID tid)
704{
705 //Remove From Active List, if Active
706 list<ThreadID>::iterator thread_it =
707 std::find(activeThreads.begin(), activeThreads.end(), tid);
708
709 DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid);
710
711 if (thread_it != activeThreads.end()) {
712 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
713 tid);
714 activeThreads.erase(thread_it);
715 }
716}
717
718template <class Impl>
719Counter
720FullO3CPU<Impl>::totalInsts() const
721{
722 Counter total(0);
723
724 ThreadID size = thread.size();
725 for (ThreadID i = 0; i < size; i++)
726 total += thread[i]->numInst;
727
728 return total;
729}
730
731template <class Impl>
732Counter
733FullO3CPU<Impl>::totalOps() const
734{
735 Counter total(0);
736
737 ThreadID size = thread.size();
738 for (ThreadID i = 0; i < size; i++)
739 total += thread[i]->numOp;
740
741 return total;
742}
743
744template <class Impl>
745void
746FullO3CPU<Impl>::activateContext(ThreadID tid, int delay)
747{
748 // Needs to set each stage to running as well.
749 if (delay){
750 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate "
751 "on cycle %d\n", tid, curTick() + ticks(delay));
752 scheduleActivateThreadEvent(tid, delay);
753 } else {
754 activateThread(tid);
755 }
756
757 if (lastActivatedCycle < curTick()) {
758 scheduleTickEvent(delay);
759
760 // Be sure to signal that there's some activity so the CPU doesn't
761 // deschedule itself.
762 activityRec.activity();
763 fetch.wakeFromQuiesce();
764
765 quiesceCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
766
767 lastActivatedCycle = curTick();
768
769 _status = Running;
770 }
771}
772
773template <class Impl>
774bool
775FullO3CPU<Impl>::scheduleDeallocateContext(ThreadID tid, bool remove,
776 int delay)
777{
778 // Schedule removal of thread data from CPU
779 if (delay){
780 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate "
781 "on cycle %d\n", tid, curTick() + ticks(delay));
782 scheduleDeallocateContextEvent(tid, remove, delay);
783 return false;
784 } else {
785 deactivateThread(tid);
786 if (remove)
787 removeThread(tid);
788 return true;
789 }
790}
791
792template <class Impl>
793void
794FullO3CPU<Impl>::suspendContext(ThreadID tid)
795{
796 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
797 bool deallocated = scheduleDeallocateContext(tid, false, 1);
798 // If this was the last thread then unschedule the tick event.
799 if ((activeThreads.size() == 1 && !deallocated) ||
800 activeThreads.size() == 0)
801 unscheduleTickEvent();
802
803 DPRINTF(Quiesce, "Suspending Context\n");
804 lastRunningCycle = curTick();
805 _status = Idle;
806}
807
808template <class Impl>
809void
810FullO3CPU<Impl>::haltContext(ThreadID tid)
811{
812 //For now, this is the same as deallocate
813 DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
814 scheduleDeallocateContext(tid, true, 1);
815}
816
817template <class Impl>
818void
819FullO3CPU<Impl>::insertThread(ThreadID tid)
820{
821 DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
822 // Will change now that the PC and thread state is internal to the CPU
823 // and not in the ThreadContext.
824 ThreadContext *src_tc;
825 if (FullSystem)
826 src_tc = system->threadContexts[tid];
827 else
828 src_tc = tcBase(tid);
829
830 //Bind Int Regs to Rename Map
831 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
832 PhysRegIndex phys_reg = freeList.getIntReg();
833
834 renameMap[tid].setEntry(ireg,phys_reg);
835 scoreboard.setReg(phys_reg);
836 }
837
838 //Bind Float Regs to Rename Map
839 for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
840 PhysRegIndex phys_reg = freeList.getFloatReg();
841
842 renameMap[tid].setEntry(freg,phys_reg);
843 scoreboard.setReg(phys_reg);
844 }
845
846 //Copy Thread Data Into RegFile
847 //this->copyFromTC(tid);
848
849 //Set PC/NPC/NNPC
850 pcState(src_tc->pcState(), tid);
851
852 src_tc->setStatus(ThreadContext::Active);
853
854 activateContext(tid,1);
855
856 //Reset ROB/IQ/LSQ Entries
857 commit.rob->resetEntries();
858 iew.resetEntries();
859}
860
861template <class Impl>
862void
863FullO3CPU<Impl>::removeThread(ThreadID tid)
864{
865 DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
866
867 // Copy Thread Data From RegFile
868 // If thread is suspended, it might be re-allocated
869 // this->copyToTC(tid);
870
871
872 // @todo: 2-27-2008: Fix how we free up rename mappings
873 // here to alleviate the case for double-freeing registers
874 // in SMT workloads.
875
876 // Unbind Int Regs from Rename Map
877 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
878 PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
879
880 scoreboard.unsetReg(phys_reg);
881 freeList.addReg(phys_reg);
882 }
883
884 // Unbind Float Regs from Rename Map
885 for (int freg = TheISA::NumIntRegs; freg < TheISA::NumFloatRegs; freg++) {
886 PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
887
888 scoreboard.unsetReg(phys_reg);
889 freeList.addReg(phys_reg);
890 }
891
892 // Squash Throughout Pipeline
893 DynInstPtr inst = commit.rob->readHeadInst(tid);
894 InstSeqNum squash_seq_num = inst->seqNum;
895 fetch.squash(0, squash_seq_num, inst, tid);
896 decode.squash(tid);
897 rename.squash(squash_seq_num, tid);
898 iew.squash(tid);
899 iew.ldstQueue.squash(squash_seq_num, tid);
900 commit.rob->squash(squash_seq_num, tid);
901
902
903 assert(iew.instQueue.getCount(tid) == 0);
904 assert(iew.ldstQueue.getCount(tid) == 0);
905
906 // Reset ROB/IQ/LSQ Entries
907
908 // Commented out for now. This should be possible to do by
909 // telling all the pipeline stages to drain first, and then
910 // checking until the drain completes. Once the pipeline is
911 // drained, call resetEntries(). - 10-09-06 ktlim
912/*
913 if (activeThreads.size() >= 1) {
914 commit.rob->resetEntries();
915 iew.resetEntries();
916 }
917*/
918}
919
920
921template <class Impl>
922void
923FullO3CPU<Impl>::activateWhenReady(ThreadID tid)
924{
925 DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming"
926 "(e.g. PhysRegs/ROB/IQ/LSQ) \n",
927 tid);
928
929 bool ready = true;
930
931 if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) {
932 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
933 "Phys. Int. Regs.\n",
934 tid);
935 ready = false;
936 } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) {
937 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
938 "Phys. Float. Regs.\n",
939 tid);
940 ready = false;
941 } else if (commit.rob->numFreeEntries() >=
942 commit.rob->entryAmount(activeThreads.size() + 1)) {
943 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
944 "ROB entries.\n",
945 tid);
946 ready = false;
947 } else if (iew.instQueue.numFreeEntries() >=
948 iew.instQueue.entryAmount(activeThreads.size() + 1)) {
949 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
950 "IQ entries.\n",
951 tid);
952 ready = false;
953 } else if (iew.ldstQueue.numFreeEntries() >=
954 iew.ldstQueue.entryAmount(activeThreads.size() + 1)) {
955 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
956 "LSQ entries.\n",
957 tid);
958 ready = false;
959 }
960
961 if (ready) {
962 insertThread(tid);
963
964 contextSwitch = false;
965
966 cpuWaitList.remove(tid);
967 } else {
968 suspendContext(tid);
969
970 //blocks fetch
971 contextSwitch = true;
972
973 //@todo: dont always add to waitlist
974 //do waitlist
975 cpuWaitList.push_back(tid);
976 }
977}
978
979template <class Impl>
980Fault
981FullO3CPU<Impl>::hwrei(ThreadID tid)
982{
983#if THE_ISA == ALPHA_ISA
984 // Need to clear the lock flag upon returning from an interrupt.
985 this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
986
987 this->thread[tid]->kernelStats->hwrei();
988
989 // FIXME: XXX check for interrupts? XXX
990#endif
991 return NoFault;
992}
993
994template <class Impl>
995bool
996FullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid)
997{
998#if THE_ISA == ALPHA_ISA
999 if (this->thread[tid]->kernelStats)
1000 this->thread[tid]->kernelStats->callpal(palFunc,
1001 this->threadContexts[tid]);
1002
1003 switch (palFunc) {
1004 case PAL::halt:
1005 halt();
1006 if (--System::numSystemsRunning == 0)
1007 exitSimLoop("all cpus halted");
1008 break;
1009
1010 case PAL::bpt:
1011 case PAL::bugchk:
1012 if (this->system->breakpoint())
1013 return false;
1014 break;
1015 }
1016#endif
1017 return true;
1018}
1019
1020template <class Impl>
1021Fault
1022FullO3CPU<Impl>::getInterrupts()
1023{
1024 // Check if there are any outstanding interrupts
1025 return this->interrupts->getInterrupt(this->threadContexts[0]);
1026}
1027
1028template <class Impl>
1029void
1030FullO3CPU<Impl>::processInterrupts(Fault interrupt)
1031{
1032 // Check for interrupts here. For now can copy the code that
1033 // exists within isa_fullsys_traits.hh. Also assume that thread 0
1034 // is the one that handles the interrupts.
1035 // @todo: Possibly consolidate the interrupt checking code.
1036 // @todo: Allow other threads to handle interrupts.
1037
1038 assert(interrupt != NoFault);
1039 this->interrupts->updateIntrInfo(this->threadContexts[0]);
1040
1041 DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
1042 this->trap(interrupt, 0, NULL);
1043}
1044
1045template <class Impl>
1046void
1047FullO3CPU<Impl>::trap(Fault fault, ThreadID tid, StaticInstPtr inst)
1048{
1049 // Pass the thread's TC into the invoke method.
1050 fault->invoke(this->threadContexts[tid], inst);
1051}
1052
1053template <class Impl>
1054void
1055FullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid)
1056{
1057 DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid);
1058
1059 DPRINTF(Activity,"Activity: syscall() called.\n");
1060
1061 // Temporarily increase this by one to account for the syscall
1062 // instruction.
1063 ++(this->thread[tid]->funcExeInst);
1064
1065 // Execute the actual syscall.
1066 this->thread[tid]->syscall(callnum);
1067
1068 // Decrease funcExeInst by one as the normal commit will handle
1069 // incrementing it.
1070 --(this->thread[tid]->funcExeInst);
1071}
1072
1073template <class Impl>
1074void
1075FullO3CPU<Impl>::serialize(std::ostream &os)
1076{
1077 SimObject::State so_state = SimObject::getState();
1078 SERIALIZE_ENUM(so_state);
1079 BaseCPU::serialize(os);
1080 nameOut(os, csprintf("%s.tickEvent", name()));
1081 tickEvent.serialize(os);
1082
1083 // Use SimpleThread's ability to checkpoint to make it easier to
1084 // write out the registers. Also make this static so it doesn't
1085 // get instantiated multiple times (causes a panic in statistics).
1086 static SimpleThread temp;
1087
1088 ThreadID size = thread.size();
1089 for (ThreadID i = 0; i < size; i++) {
1090 nameOut(os, csprintf("%s.xc.%i", name(), i));
1091 temp.copyTC(thread[i]->getTC());
1092 temp.serialize(os);
1093 }
1094}
1095
1096template <class Impl>
1097void
1098FullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion)
1099{
1100 SimObject::State so_state;
1101 UNSERIALIZE_ENUM(so_state);
1102 BaseCPU::unserialize(cp, section);
1103 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
1104
1105 // Use SimpleThread's ability to checkpoint to make it easier to
1106 // read in the registers. Also make this static so it doesn't
1107 // get instantiated multiple times (causes a panic in statistics).
1108 static SimpleThread temp;
1109
1110 ThreadID size = thread.size();
1111 for (ThreadID i = 0; i < size; i++) {
1112 temp.copyTC(thread[i]->getTC());
1113 temp.unserialize(cp, csprintf("%s.xc.%i", section, i));
1114 thread[i]->getTC()->copyArchRegs(temp.getTC());
1115 }
1116}
1117
1118template <class Impl>
1119unsigned int
1120FullO3CPU<Impl>::drain(Event *drain_event)
1121{
1122 DPRINTF(O3CPU, "Switching out\n");
1123
1124 // If the CPU isn't doing anything, then return immediately.
1125 if (_status == Idle || _status == SwitchedOut) {
1126 return 0;
1127 }
1128
1129 drainCount = 0;
1130 fetch.drain();
1131 decode.drain();
1132 rename.drain();
1133 iew.drain();
1134 commit.drain();
1135
1136 // Wake the CPU and record activity so everything can drain out if
1137 // the CPU was not able to immediately drain.
1138 if (getState() != SimObject::Drained) {
1139 // A bit of a hack...set the drainEvent after all the drain()
1140 // calls have been made, that way if all of the stages drain
1141 // immediately, the signalDrained() function knows not to call
1142 // process on the drain event.
1143 drainEvent = drain_event;
1144
1145 wakeCPU();
1146 activityRec.activity();
1147
1148 return 1;
1149 } else {
1150 return 0;
1151 }
1152}
1153
1154template <class Impl>
1155void
1156FullO3CPU<Impl>::resume()
1157{
1158 fetch.resume();
1159 decode.resume();
1160 rename.resume();
1161 iew.resume();
1162 commit.resume();
1163
1164 changeState(SimObject::Running);
1165
1166 if (_status == SwitchedOut || _status == Idle)
1167 return;
1168
1169 assert(system->getMemoryMode() == Enums::timing);
1170
1171 if (!tickEvent.scheduled())
1172 schedule(tickEvent, nextCycle());
1173 _status = Running;
1174}
1175
1176template <class Impl>
1177void
1178FullO3CPU<Impl>::signalDrained()
1179{
1180 if (++drainCount == NumStages) {
1181 if (tickEvent.scheduled())
1182 tickEvent.squash();
1183
1184 changeState(SimObject::Drained);
1185
1186 BaseCPU::switchOut();
1187
1188 if (drainEvent) {
1189 drainEvent->process();
1190 drainEvent = NULL;
1191 }
1192 }
1193 assert(drainCount <= 5);
1194}
1195
1196template <class Impl>
1197void
1198FullO3CPU<Impl>::switchOut()
1199{
1200 fetch.switchOut();
1201 rename.switchOut();
1202 iew.switchOut();
1203 commit.switchOut();
1204 instList.clear();
1205 while (!removeList.empty()) {
1206 removeList.pop();
1207 }
1208
1209 _status = SwitchedOut;
| 439
440 o3_tc->cpu = (typename Impl::O3CPU *)(this);
441 assert(o3_tc->cpu);
442 o3_tc->thread = this->thread[tid];
443
444 if (FullSystem) {
445 // Setup quiesce event.
446 this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
447 }
448 // Give the thread the TC.
449 this->thread[tid]->tc = tc;
450
451 // Add the TC to the CPU's list of TC's.
452 this->threadContexts.push_back(tc);
453 }
454
455 // FullO3CPU always requires an interrupt controller.
456 if (!params->defer_registration && !interrupts) {
457 fatal("FullO3CPU %s has no interrupt controller.\n"
458 "Ensure createInterruptController() is called.\n", name());
459 }
460
461 for (ThreadID tid = 0; tid < this->numThreads; tid++)
462 this->thread[tid]->setFuncExeInst(0);
463
464 lockAddr = 0;
465 lockFlag = false;
466}
467
468template <class Impl>
469FullO3CPU<Impl>::~FullO3CPU()
470{
471}
472
473template <class Impl>
474void
475FullO3CPU<Impl>::regStats()
476{
477 BaseO3CPU::regStats();
478
479 // Register any of the O3CPU's stats here.
480 timesIdled
481 .name(name() + ".timesIdled")
482 .desc("Number of times that the entire CPU went into an idle state and"
483 " unscheduled itself")
484 .prereq(timesIdled);
485
486 idleCycles
487 .name(name() + ".idleCycles")
488 .desc("Total number of cycles that the CPU has spent unscheduled due "
489 "to idling")
490 .prereq(idleCycles);
491
492 quiesceCycles
493 .name(name() + ".quiesceCycles")
494 .desc("Total number of cycles that CPU has spent quiesced or waiting "
495 "for an interrupt")
496 .prereq(quiesceCycles);
497
498 // Number of Instructions simulated
499 // --------------------------------
500 // Should probably be in Base CPU but need templated
501 // MaxThreads so put in here instead
502 committedInsts
503 .init(numThreads)
504 .name(name() + ".committedInsts")
505 .desc("Number of Instructions Simulated");
506
507 committedOps
508 .init(numThreads)
509 .name(name() + ".committedOps")
510 .desc("Number of Ops (including micro ops) Simulated");
511
512 totalCommittedInsts
513 .name(name() + ".committedInsts_total")
514 .desc("Number of Instructions Simulated");
515
516 cpi
517 .name(name() + ".cpi")
518 .desc("CPI: Cycles Per Instruction")
519 .precision(6);
520 cpi = numCycles / committedInsts;
521
522 totalCpi
523 .name(name() + ".cpi_total")
524 .desc("CPI: Total CPI of All Threads")
525 .precision(6);
526 totalCpi = numCycles / totalCommittedInsts;
527
528 ipc
529 .name(name() + ".ipc")
530 .desc("IPC: Instructions Per Cycle")
531 .precision(6);
532 ipc = committedInsts / numCycles;
533
534 totalIpc
535 .name(name() + ".ipc_total")
536 .desc("IPC: Total IPC of All Threads")
537 .precision(6);
538 totalIpc = totalCommittedInsts / numCycles;
539
540 this->fetch.regStats();
541 this->decode.regStats();
542 this->rename.regStats();
543 this->iew.regStats();
544 this->commit.regStats();
545 this->rob.regStats();
546
547 intRegfileReads
548 .name(name() + ".int_regfile_reads")
549 .desc("number of integer regfile reads")
550 .prereq(intRegfileReads);
551
552 intRegfileWrites
553 .name(name() + ".int_regfile_writes")
554 .desc("number of integer regfile writes")
555 .prereq(intRegfileWrites);
556
557 fpRegfileReads
558 .name(name() + ".fp_regfile_reads")
559 .desc("number of floating regfile reads")
560 .prereq(fpRegfileReads);
561
562 fpRegfileWrites
563 .name(name() + ".fp_regfile_writes")
564 .desc("number of floating regfile writes")
565 .prereq(fpRegfileWrites);
566
567 miscRegfileReads
568 .name(name() + ".misc_regfile_reads")
569 .desc("number of misc regfile reads")
570 .prereq(miscRegfileReads);
571
572 miscRegfileWrites
573 .name(name() + ".misc_regfile_writes")
574 .desc("number of misc regfile writes")
575 .prereq(miscRegfileWrites);
576}
577
578template <class Impl>
579void
580FullO3CPU<Impl>::tick()
581{
582 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
583
584 ++numCycles;
585
586// activity = false;
587
588 //Tick each of the stages
589 fetch.tick();
590
591 decode.tick();
592
593 rename.tick();
594
595 iew.tick();
596
597 commit.tick();
598
599 if (!FullSystem)
600 doContextSwitch();
601
602 // Now advance the time buffers
603 timeBuffer.advance();
604
605 fetchQueue.advance();
606 decodeQueue.advance();
607 renameQueue.advance();
608 iewQueue.advance();
609
610 activityRec.advance();
611
612 if (removeInstsThisCycle) {
613 cleanUpRemovedInsts();
614 }
615
616 if (!tickEvent.scheduled()) {
617 if (_status == SwitchedOut ||
618 getState() == SimObject::Drained) {
619 DPRINTF(O3CPU, "Switched out!\n");
620 // increment stat
621 lastRunningCycle = curTick();
622 } else if (!activityRec.active() || _status == Idle) {
623 DPRINTF(O3CPU, "Idle!\n");
624 lastRunningCycle = curTick();
625 timesIdled++;
626 } else {
627 schedule(tickEvent, nextCycle(curTick() + ticks(1)));
628 DPRINTF(O3CPU, "Scheduling next tick!\n");
629 }
630 }
631
632 if (!FullSystem)
633 updateThreadPriority();
634}
635
636template <class Impl>
637void
638FullO3CPU<Impl>::init()
639{
640 BaseCPU::init();
641
642 // Set inSyscall so that the CPU doesn't squash when initially
643 // setting up registers.
644 for (ThreadID tid = 0; tid < numThreads; ++tid)
645 thread[tid]->inSyscall = true;
646
647 // this CPU could still be unconnected if we are restoring from a
648 // checkpoint and this CPU is to be switched in, thus we can only
649 // do this here if the instruction port is actually connected, if
650 // not we have to do it as part of takeOverFrom
651 if (icachePort.isConnected())
652 fetch.setIcache();
653
654 if (FullSystem && !params()->defer_registration) {
655 for (ThreadID tid = 0; tid < numThreads; tid++) {
656 ThreadContext *src_tc = threadContexts[tid];
657 TheISA::initCPU(src_tc, src_tc->contextId());
658 // Initialise the ThreadContext's memory proxies
659 thread[tid]->initMemProxies(thread[tid]->getTC());
660 }
661 }
662
663 // Clear inSyscall.
664 for (int tid = 0; tid < numThreads; ++tid)
665 thread[tid]->inSyscall = false;
666
667 // Initialize stages.
668 fetch.initStage();
669 iew.initStage();
670 rename.initStage();
671 commit.initStage();
672
673 commit.setThreads(thread);
674}
675
676template <class Impl>
677void
678FullO3CPU<Impl>::activateThread(ThreadID tid)
679{
680 list<ThreadID>::iterator isActive =
681 std::find(activeThreads.begin(), activeThreads.end(), tid);
682
683 DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid);
684
685 if (isActive == activeThreads.end()) {
686 DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n",
687 tid);
688
689 activeThreads.push_back(tid);
690 }
691}
692
693template <class Impl>
694void
695FullO3CPU<Impl>::deactivateThread(ThreadID tid)
696{
697 //Remove From Active List, if Active
698 list<ThreadID>::iterator thread_it =
699 std::find(activeThreads.begin(), activeThreads.end(), tid);
700
701 DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid);
702
703 if (thread_it != activeThreads.end()) {
704 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
705 tid);
706 activeThreads.erase(thread_it);
707 }
708}
709
710template <class Impl>
711Counter
712FullO3CPU<Impl>::totalInsts() const
713{
714 Counter total(0);
715
716 ThreadID size = thread.size();
717 for (ThreadID i = 0; i < size; i++)
718 total += thread[i]->numInst;
719
720 return total;
721}
722
723template <class Impl>
724Counter
725FullO3CPU<Impl>::totalOps() const
726{
727 Counter total(0);
728
729 ThreadID size = thread.size();
730 for (ThreadID i = 0; i < size; i++)
731 total += thread[i]->numOp;
732
733 return total;
734}
735
736template <class Impl>
737void
738FullO3CPU<Impl>::activateContext(ThreadID tid, int delay)
739{
740 // Needs to set each stage to running as well.
741 if (delay){
742 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate "
743 "on cycle %d\n", tid, curTick() + ticks(delay));
744 scheduleActivateThreadEvent(tid, delay);
745 } else {
746 activateThread(tid);
747 }
748
749 if (lastActivatedCycle < curTick()) {
750 scheduleTickEvent(delay);
751
752 // Be sure to signal that there's some activity so the CPU doesn't
753 // deschedule itself.
754 activityRec.activity();
755 fetch.wakeFromQuiesce();
756
757 quiesceCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
758
759 lastActivatedCycle = curTick();
760
761 _status = Running;
762 }
763}
764
765template <class Impl>
766bool
767FullO3CPU<Impl>::scheduleDeallocateContext(ThreadID tid, bool remove,
768 int delay)
769{
770 // Schedule removal of thread data from CPU
771 if (delay){
772 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate "
773 "on cycle %d\n", tid, curTick() + ticks(delay));
774 scheduleDeallocateContextEvent(tid, remove, delay);
775 return false;
776 } else {
777 deactivateThread(tid);
778 if (remove)
779 removeThread(tid);
780 return true;
781 }
782}
783
784template <class Impl>
785void
786FullO3CPU<Impl>::suspendContext(ThreadID tid)
787{
788 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
789 bool deallocated = scheduleDeallocateContext(tid, false, 1);
790 // If this was the last thread then unschedule the tick event.
791 if ((activeThreads.size() == 1 && !deallocated) ||
792 activeThreads.size() == 0)
793 unscheduleTickEvent();
794
795 DPRINTF(Quiesce, "Suspending Context\n");
796 lastRunningCycle = curTick();
797 _status = Idle;
798}
799
800template <class Impl>
801void
802FullO3CPU<Impl>::haltContext(ThreadID tid)
803{
804 //For now, this is the same as deallocate
805 DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
806 scheduleDeallocateContext(tid, true, 1);
807}
808
809template <class Impl>
810void
811FullO3CPU<Impl>::insertThread(ThreadID tid)
812{
813 DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
814 // Will change now that the PC and thread state is internal to the CPU
815 // and not in the ThreadContext.
816 ThreadContext *src_tc;
817 if (FullSystem)
818 src_tc = system->threadContexts[tid];
819 else
820 src_tc = tcBase(tid);
821
822 //Bind Int Regs to Rename Map
823 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
824 PhysRegIndex phys_reg = freeList.getIntReg();
825
826 renameMap[tid].setEntry(ireg,phys_reg);
827 scoreboard.setReg(phys_reg);
828 }
829
830 //Bind Float Regs to Rename Map
831 for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
832 PhysRegIndex phys_reg = freeList.getFloatReg();
833
834 renameMap[tid].setEntry(freg,phys_reg);
835 scoreboard.setReg(phys_reg);
836 }
837
838 //Copy Thread Data Into RegFile
839 //this->copyFromTC(tid);
840
841 //Set PC/NPC/NNPC
842 pcState(src_tc->pcState(), tid);
843
844 src_tc->setStatus(ThreadContext::Active);
845
846 activateContext(tid,1);
847
848 //Reset ROB/IQ/LSQ Entries
849 commit.rob->resetEntries();
850 iew.resetEntries();
851}
852
853template <class Impl>
854void
855FullO3CPU<Impl>::removeThread(ThreadID tid)
856{
857 DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
858
859 // Copy Thread Data From RegFile
860 // If thread is suspended, it might be re-allocated
861 // this->copyToTC(tid);
862
863
864 // @todo: 2-27-2008: Fix how we free up rename mappings
865 // here to alleviate the case for double-freeing registers
866 // in SMT workloads.
867
868 // Unbind Int Regs from Rename Map
869 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
870 PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
871
872 scoreboard.unsetReg(phys_reg);
873 freeList.addReg(phys_reg);
874 }
875
876 // Unbind Float Regs from Rename Map
877 for (int freg = TheISA::NumIntRegs; freg < TheISA::NumFloatRegs; freg++) {
878 PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
879
880 scoreboard.unsetReg(phys_reg);
881 freeList.addReg(phys_reg);
882 }
883
884 // Squash Throughout Pipeline
885 DynInstPtr inst = commit.rob->readHeadInst(tid);
886 InstSeqNum squash_seq_num = inst->seqNum;
887 fetch.squash(0, squash_seq_num, inst, tid);
888 decode.squash(tid);
889 rename.squash(squash_seq_num, tid);
890 iew.squash(tid);
891 iew.ldstQueue.squash(squash_seq_num, tid);
892 commit.rob->squash(squash_seq_num, tid);
893
894
895 assert(iew.instQueue.getCount(tid) == 0);
896 assert(iew.ldstQueue.getCount(tid) == 0);
897
898 // Reset ROB/IQ/LSQ Entries
899
900 // Commented out for now. This should be possible to do by
901 // telling all the pipeline stages to drain first, and then
902 // checking until the drain completes. Once the pipeline is
903 // drained, call resetEntries(). - 10-09-06 ktlim
904/*
905 if (activeThreads.size() >= 1) {
906 commit.rob->resetEntries();
907 iew.resetEntries();
908 }
909*/
910}
911
912
913template <class Impl>
914void
915FullO3CPU<Impl>::activateWhenReady(ThreadID tid)
916{
917 DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming"
918 "(e.g. PhysRegs/ROB/IQ/LSQ) \n",
919 tid);
920
921 bool ready = true;
922
923 if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) {
924 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
925 "Phys. Int. Regs.\n",
926 tid);
927 ready = false;
928 } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) {
929 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
930 "Phys. Float. Regs.\n",
931 tid);
932 ready = false;
933 } else if (commit.rob->numFreeEntries() >=
934 commit.rob->entryAmount(activeThreads.size() + 1)) {
935 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
936 "ROB entries.\n",
937 tid);
938 ready = false;
939 } else if (iew.instQueue.numFreeEntries() >=
940 iew.instQueue.entryAmount(activeThreads.size() + 1)) {
941 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
942 "IQ entries.\n",
943 tid);
944 ready = false;
945 } else if (iew.ldstQueue.numFreeEntries() >=
946 iew.ldstQueue.entryAmount(activeThreads.size() + 1)) {
947 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
948 "LSQ entries.\n",
949 tid);
950 ready = false;
951 }
952
953 if (ready) {
954 insertThread(tid);
955
956 contextSwitch = false;
957
958 cpuWaitList.remove(tid);
959 } else {
960 suspendContext(tid);
961
962 //blocks fetch
963 contextSwitch = true;
964
965 //@todo: dont always add to waitlist
966 //do waitlist
967 cpuWaitList.push_back(tid);
968 }
969}
970
971template <class Impl>
972Fault
973FullO3CPU<Impl>::hwrei(ThreadID tid)
974{
975#if THE_ISA == ALPHA_ISA
976 // Need to clear the lock flag upon returning from an interrupt.
977 this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
978
979 this->thread[tid]->kernelStats->hwrei();
980
981 // FIXME: XXX check for interrupts? XXX
982#endif
983 return NoFault;
984}
985
986template <class Impl>
987bool
988FullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid)
989{
990#if THE_ISA == ALPHA_ISA
991 if (this->thread[tid]->kernelStats)
992 this->thread[tid]->kernelStats->callpal(palFunc,
993 this->threadContexts[tid]);
994
995 switch (palFunc) {
996 case PAL::halt:
997 halt();
998 if (--System::numSystemsRunning == 0)
999 exitSimLoop("all cpus halted");
1000 break;
1001
1002 case PAL::bpt:
1003 case PAL::bugchk:
1004 if (this->system->breakpoint())
1005 return false;
1006 break;
1007 }
1008#endif
1009 return true;
1010}
1011
1012template <class Impl>
1013Fault
1014FullO3CPU<Impl>::getInterrupts()
1015{
1016 // Check if there are any outstanding interrupts
1017 return this->interrupts->getInterrupt(this->threadContexts[0]);
1018}
1019
1020template <class Impl>
1021void
1022FullO3CPU<Impl>::processInterrupts(Fault interrupt)
1023{
1024 // Check for interrupts here. For now can copy the code that
1025 // exists within isa_fullsys_traits.hh. Also assume that thread 0
1026 // is the one that handles the interrupts.
1027 // @todo: Possibly consolidate the interrupt checking code.
1028 // @todo: Allow other threads to handle interrupts.
1029
1030 assert(interrupt != NoFault);
1031 this->interrupts->updateIntrInfo(this->threadContexts[0]);
1032
1033 DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
1034 this->trap(interrupt, 0, NULL);
1035}
1036
1037template <class Impl>
1038void
1039FullO3CPU<Impl>::trap(Fault fault, ThreadID tid, StaticInstPtr inst)
1040{
1041 // Pass the thread's TC into the invoke method.
1042 fault->invoke(this->threadContexts[tid], inst);
1043}
1044
1045template <class Impl>
1046void
1047FullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid)
1048{
1049 DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid);
1050
1051 DPRINTF(Activity,"Activity: syscall() called.\n");
1052
1053 // Temporarily increase this by one to account for the syscall
1054 // instruction.
1055 ++(this->thread[tid]->funcExeInst);
1056
1057 // Execute the actual syscall.
1058 this->thread[tid]->syscall(callnum);
1059
1060 // Decrease funcExeInst by one as the normal commit will handle
1061 // incrementing it.
1062 --(this->thread[tid]->funcExeInst);
1063}
1064
1065template <class Impl>
1066void
1067FullO3CPU<Impl>::serialize(std::ostream &os)
1068{
1069 SimObject::State so_state = SimObject::getState();
1070 SERIALIZE_ENUM(so_state);
1071 BaseCPU::serialize(os);
1072 nameOut(os, csprintf("%s.tickEvent", name()));
1073 tickEvent.serialize(os);
1074
1075 // Use SimpleThread's ability to checkpoint to make it easier to
1076 // write out the registers. Also make this static so it doesn't
1077 // get instantiated multiple times (causes a panic in statistics).
1078 static SimpleThread temp;
1079
1080 ThreadID size = thread.size();
1081 for (ThreadID i = 0; i < size; i++) {
1082 nameOut(os, csprintf("%s.xc.%i", name(), i));
1083 temp.copyTC(thread[i]->getTC());
1084 temp.serialize(os);
1085 }
1086}
1087
1088template <class Impl>
1089void
1090FullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion)
1091{
1092 SimObject::State so_state;
1093 UNSERIALIZE_ENUM(so_state);
1094 BaseCPU::unserialize(cp, section);
1095 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
1096
1097 // Use SimpleThread's ability to checkpoint to make it easier to
1098 // read in the registers. Also make this static so it doesn't
1099 // get instantiated multiple times (causes a panic in statistics).
1100 static SimpleThread temp;
1101
1102 ThreadID size = thread.size();
1103 for (ThreadID i = 0; i < size; i++) {
1104 temp.copyTC(thread[i]->getTC());
1105 temp.unserialize(cp, csprintf("%s.xc.%i", section, i));
1106 thread[i]->getTC()->copyArchRegs(temp.getTC());
1107 }
1108}
1109
1110template <class Impl>
1111unsigned int
1112FullO3CPU<Impl>::drain(Event *drain_event)
1113{
1114 DPRINTF(O3CPU, "Switching out\n");
1115
1116 // If the CPU isn't doing anything, then return immediately.
1117 if (_status == Idle || _status == SwitchedOut) {
1118 return 0;
1119 }
1120
1121 drainCount = 0;
1122 fetch.drain();
1123 decode.drain();
1124 rename.drain();
1125 iew.drain();
1126 commit.drain();
1127
1128 // Wake the CPU and record activity so everything can drain out if
1129 // the CPU was not able to immediately drain.
1130 if (getState() != SimObject::Drained) {
1131 // A bit of a hack...set the drainEvent after all the drain()
1132 // calls have been made, that way if all of the stages drain
1133 // immediately, the signalDrained() function knows not to call
1134 // process on the drain event.
1135 drainEvent = drain_event;
1136
1137 wakeCPU();
1138 activityRec.activity();
1139
1140 return 1;
1141 } else {
1142 return 0;
1143 }
1144}
1145
1146template <class Impl>
1147void
1148FullO3CPU<Impl>::resume()
1149{
1150 fetch.resume();
1151 decode.resume();
1152 rename.resume();
1153 iew.resume();
1154 commit.resume();
1155
1156 changeState(SimObject::Running);
1157
1158 if (_status == SwitchedOut || _status == Idle)
1159 return;
1160
1161 assert(system->getMemoryMode() == Enums::timing);
1162
1163 if (!tickEvent.scheduled())
1164 schedule(tickEvent, nextCycle());
1165 _status = Running;
1166}
1167
1168template <class Impl>
1169void
1170FullO3CPU<Impl>::signalDrained()
1171{
1172 if (++drainCount == NumStages) {
1173 if (tickEvent.scheduled())
1174 tickEvent.squash();
1175
1176 changeState(SimObject::Drained);
1177
1178 BaseCPU::switchOut();
1179
1180 if (drainEvent) {
1181 drainEvent->process();
1182 drainEvent = NULL;
1183 }
1184 }
1185 assert(drainCount <= 5);
1186}
1187
1188template <class Impl>
1189void
1190FullO3CPU<Impl>::switchOut()
1191{
1192 fetch.switchOut();
1193 rename.switchOut();
1194 iew.switchOut();
1195 commit.switchOut();
1196 instList.clear();
1197 while (!removeList.empty()) {
1198 removeList.pop();
1199 }
1200
1201 _status = SwitchedOut;
|
1210#if USE_CHECKER
| 1202
|
1211 if (checker)
1212 checker->switchOut();
| 1203 if (checker)
1204 checker->switchOut();
|
1213#endif
| 1205
|
1214 if (tickEvent.scheduled())
1215 tickEvent.squash();
1216}
1217
1218template <class Impl>
1219void
1220FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
1221{
1222 // Flush out any old data from the time buffers.
1223 for (int i = 0; i < timeBuffer.getSize(); ++i) {
1224 timeBuffer.advance();
1225 fetchQueue.advance();
1226 decodeQueue.advance();
1227 renameQueue.advance();
1228 iewQueue.advance();
1229 }
1230
1231 activityRec.reset();
1232
1233 BaseCPU::takeOverFrom(oldCPU);
1234
1235 fetch.takeOverFrom();
1236 decode.takeOverFrom();
1237 rename.takeOverFrom();
1238 iew.takeOverFrom();
1239 commit.takeOverFrom();
1240
1241 assert(!tickEvent.scheduled() || tickEvent.squashed());
1242
1243 // @todo: Figure out how to properly select the tid to put onto
1244 // the active threads list.
1245 ThreadID tid = 0;
1246
1247 list<ThreadID>::iterator isActive =
1248 std::find(activeThreads.begin(), activeThreads.end(), tid);
1249
1250 if (isActive == activeThreads.end()) {
1251 //May Need to Re-code this if the delay variable is the delay
1252 //needed for thread to activate
1253 DPRINTF(O3CPU, "Adding Thread %i to active threads list\n",
1254 tid);
1255
1256 activeThreads.push_back(tid);
1257 }
1258
1259 // Set all statuses to active, schedule the CPU's tick event.
1260 // @todo: Fix up statuses so this is handled properly
1261 ThreadID size = threadContexts.size();
1262 for (ThreadID i = 0; i < size; ++i) {
1263 ThreadContext *tc = threadContexts[i];
1264 if (tc->status() == ThreadContext::Active && _status != Running) {
1265 _status = Running;
1266 reschedule(tickEvent, nextCycle(), true);
1267 }
1268 }
1269 if (!tickEvent.scheduled())
1270 schedule(tickEvent, nextCycle());
1271
1272 lastRunningCycle = curTick();
1273}
1274
1275template <class Impl>
1276TheISA::MiscReg
1277FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid)
1278{
1279 return this->isa[tid].readMiscRegNoEffect(misc_reg);
1280}
1281
1282template <class Impl>
1283TheISA::MiscReg
1284FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
1285{
1286 miscRegfileReads++;
1287 return this->isa[tid].readMiscReg(misc_reg, tcBase(tid));
1288}
1289
1290template <class Impl>
1291void
1292FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
1293 const TheISA::MiscReg &val, ThreadID tid)
1294{
1295 this->isa[tid].setMiscRegNoEffect(misc_reg, val);
1296}
1297
1298template <class Impl>
1299void
1300FullO3CPU<Impl>::setMiscReg(int misc_reg,
1301 const TheISA::MiscReg &val, ThreadID tid)
1302{
1303 miscRegfileWrites++;
1304 this->isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
1305}
1306
1307template <class Impl>
1308uint64_t
1309FullO3CPU<Impl>::readIntReg(int reg_idx)
1310{
1311 intRegfileReads++;
1312 return regFile.readIntReg(reg_idx);
1313}
1314
1315template <class Impl>
1316FloatReg
1317FullO3CPU<Impl>::readFloatReg(int reg_idx)
1318{
1319 fpRegfileReads++;
1320 return regFile.readFloatReg(reg_idx);
1321}
1322
1323template <class Impl>
1324FloatRegBits
1325FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
1326{
1327 fpRegfileReads++;
1328 return regFile.readFloatRegBits(reg_idx);
1329}
1330
1331template <class Impl>
1332void
1333FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
1334{
1335 intRegfileWrites++;
1336 regFile.setIntReg(reg_idx, val);
1337}
1338
1339template <class Impl>
1340void
1341FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
1342{
1343 fpRegfileWrites++;
1344 regFile.setFloatReg(reg_idx, val);
1345}
1346
1347template <class Impl>
1348void
1349FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
1350{
1351 fpRegfileWrites++;
1352 regFile.setFloatRegBits(reg_idx, val);
1353}
1354
1355template <class Impl>
1356uint64_t
1357FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1358{
1359 intRegfileReads++;
1360 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1361
1362 return regFile.readIntReg(phys_reg);
1363}
1364
1365template <class Impl>
1366float
1367FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
1368{
1369 fpRegfileReads++;
1370 int idx = reg_idx + TheISA::NumIntRegs;
1371 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1372
1373 return regFile.readFloatReg(phys_reg);
1374}
1375
1376template <class Impl>
1377uint64_t
1378FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid)
1379{
1380 fpRegfileReads++;
1381 int idx = reg_idx + TheISA::NumIntRegs;
1382 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1383
1384 return regFile.readFloatRegBits(phys_reg);
1385}
1386
1387template <class Impl>
1388void
1389FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
1390{
1391 intRegfileWrites++;
1392 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1393
1394 regFile.setIntReg(phys_reg, val);
1395}
1396
1397template <class Impl>
1398void
1399FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid)
1400{
1401 fpRegfileWrites++;
1402 int idx = reg_idx + TheISA::NumIntRegs;
1403 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1404
1405 regFile.setFloatReg(phys_reg, val);
1406}
1407
1408template <class Impl>
1409void
1410FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid)
1411{
1412 fpRegfileWrites++;
1413 int idx = reg_idx + TheISA::NumIntRegs;
1414 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1415
1416 regFile.setFloatRegBits(phys_reg, val);
1417}
1418
1419template <class Impl>
1420TheISA::PCState
1421FullO3CPU<Impl>::pcState(ThreadID tid)
1422{
1423 return commit.pcState(tid);
1424}
1425
1426template <class Impl>
1427void
1428FullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid)
1429{
1430 commit.pcState(val, tid);
1431}
1432
1433template <class Impl>
1434Addr
1435FullO3CPU<Impl>::instAddr(ThreadID tid)
1436{
1437 return commit.instAddr(tid);
1438}
1439
1440template <class Impl>
1441Addr
1442FullO3CPU<Impl>::nextInstAddr(ThreadID tid)
1443{
1444 return commit.nextInstAddr(tid);
1445}
1446
1447template <class Impl>
1448MicroPC
1449FullO3CPU<Impl>::microPC(ThreadID tid)
1450{
1451 return commit.microPC(tid);
1452}
1453
1454template <class Impl>
1455void
1456FullO3CPU<Impl>::squashFromTC(ThreadID tid)
1457{
1458 this->thread[tid]->inSyscall = true;
1459 this->commit.generateTCEvent(tid);
1460}
1461
1462template <class Impl>
1463typename FullO3CPU<Impl>::ListIt
1464FullO3CPU<Impl>::addInst(DynInstPtr &inst)
1465{
1466 instList.push_back(inst);
1467
1468 return --(instList.end());
1469}
1470
1471template <class Impl>
1472void
1473FullO3CPU<Impl>::instDone(ThreadID tid, DynInstPtr &inst)
1474{
1475 // Keep an instruction count.
1476 if (!inst->isMicroop() || inst->isLastMicroop()) {
1477 thread[tid]->numInst++;
1478 thread[tid]->numInsts++;
1479 committedInsts[tid]++;
1480 totalCommittedInsts++;
1481 }
1482 thread[tid]->numOp++;
1483 thread[tid]->numOps++;
1484 committedOps[tid]++;
1485
1486 system->totalNumInsts++;
1487 // Check for instruction-count-based events.
1488 comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1489 system->instEventQueue.serviceEvents(system->totalNumInsts);
1490}
1491
1492template <class Impl>
1493void
1494FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
1495{
1496 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s "
1497 "[sn:%lli]\n",
1498 inst->threadNumber, inst->pcState(), inst->seqNum);
1499
1500 removeInstsThisCycle = true;
1501
1502 // Remove the front instruction.
1503 removeList.push(inst->getInstListIt());
1504}
1505
1506template <class Impl>
1507void
1508FullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid)
1509{
1510 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1511 " list.\n", tid);
1512
1513 ListIt end_it;
1514
1515 bool rob_empty = false;
1516
1517 if (instList.empty()) {
1518 return;
1519 } else if (rob.isEmpty(/*tid*/)) {
1520 DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1521 end_it = instList.begin();
1522 rob_empty = true;
1523 } else {
1524 end_it = (rob.readTailInst(tid))->getInstListIt();
1525 DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1526 }
1527
1528 removeInstsThisCycle = true;
1529
1530 ListIt inst_it = instList.end();
1531
1532 inst_it--;
1533
1534 // Walk through the instruction list, removing any instructions
1535 // that were inserted after the given instruction iterator, end_it.
1536 while (inst_it != end_it) {
1537 assert(!instList.empty());
1538
1539 squashInstIt(inst_it, tid);
1540
1541 inst_it--;
1542 }
1543
1544 // If the ROB was empty, then we actually need to remove the first
1545 // instruction as well.
1546 if (rob_empty) {
1547 squashInstIt(inst_it, tid);
1548 }
1549}
1550
1551template <class Impl>
1552void
1553FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1554{
1555 assert(!instList.empty());
1556
1557 removeInstsThisCycle = true;
1558
1559 ListIt inst_iter = instList.end();
1560
1561 inst_iter--;
1562
1563 DPRINTF(O3CPU, "Deleting instructions from instruction "
1564 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1565 tid, seq_num, (*inst_iter)->seqNum);
1566
1567 while ((*inst_iter)->seqNum > seq_num) {
1568
1569 bool break_loop = (inst_iter == instList.begin());
1570
1571 squashInstIt(inst_iter, tid);
1572
1573 inst_iter--;
1574
1575 if (break_loop)
1576 break;
1577 }
1578}
1579
1580template <class Impl>
1581inline void
1582FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid)
1583{
1584 if ((*instIt)->threadNumber == tid) {
1585 DPRINTF(O3CPU, "Squashing instruction, "
1586 "[tid:%i] [sn:%lli] PC %s\n",
1587 (*instIt)->threadNumber,
1588 (*instIt)->seqNum,
1589 (*instIt)->pcState());
1590
1591 // Mark it as squashed.
1592 (*instIt)->setSquashed();
1593
1594 // @todo: Formulate a consistent method for deleting
1595 // instructions from the instruction list
1596 // Remove the instruction from the list.
1597 removeList.push(instIt);
1598 }
1599}
1600
1601template <class Impl>
1602void
1603FullO3CPU<Impl>::cleanUpRemovedInsts()
1604{
1605 while (!removeList.empty()) {
1606 DPRINTF(O3CPU, "Removing instruction, "
1607 "[tid:%i] [sn:%lli] PC %s\n",
1608 (*removeList.front())->threadNumber,
1609 (*removeList.front())->seqNum,
1610 (*removeList.front())->pcState());
1611
1612 instList.erase(removeList.front());
1613
1614 removeList.pop();
1615 }
1616
1617 removeInstsThisCycle = false;
1618}
1619/*
1620template <class Impl>
1621void
1622FullO3CPU<Impl>::removeAllInsts()
1623{
1624 instList.clear();
1625}
1626*/
1627template <class Impl>
1628void
1629FullO3CPU<Impl>::dumpInsts()
1630{
1631 int num = 0;
1632
1633 ListIt inst_list_it = instList.begin();
1634
1635 cprintf("Dumping Instruction List\n");
1636
1637 while (inst_list_it != instList.end()) {
1638 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1639 "Squashed:%i\n\n",
1640 num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber,
1641 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1642 (*inst_list_it)->isSquashed());
1643 inst_list_it++;
1644 ++num;
1645 }
1646}
1647/*
1648template <class Impl>
1649void
1650FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
1651{
1652 iew.wakeDependents(inst);
1653}
1654*/
1655template <class Impl>
1656void
1657FullO3CPU<Impl>::wakeCPU()
1658{
1659 if (activityRec.active() || tickEvent.scheduled()) {
1660 DPRINTF(Activity, "CPU already running.\n");
1661 return;
1662 }
1663
1664 DPRINTF(Activity, "Waking up CPU\n");
1665
1666 idleCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
1667 numCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
1668
1669 schedule(tickEvent, nextCycle());
1670}
1671
1672template <class Impl>
1673void
1674FullO3CPU<Impl>::wakeup()
1675{
1676 if (this->thread[0]->status() != ThreadContext::Suspended)
1677 return;
1678
1679 this->wakeCPU();
1680
1681 DPRINTF(Quiesce, "Suspended Processor woken\n");
1682 this->threadContexts[0]->activate();
1683}
1684
1685template <class Impl>
1686ThreadID
1687FullO3CPU<Impl>::getFreeTid()
1688{
1689 for (ThreadID tid = 0; tid < numThreads; tid++) {
1690 if (!tids[tid]) {
1691 tids[tid] = true;
1692 return tid;
1693 }
1694 }
1695
1696 return InvalidThreadID;
1697}
1698
1699template <class Impl>
1700void
1701FullO3CPU<Impl>::doContextSwitch()
1702{
1703 if (contextSwitch) {
1704
1705 //ADD CODE TO DEACTIVE THREAD HERE (???)
1706
1707 ThreadID size = cpuWaitList.size();
1708 for (ThreadID tid = 0; tid < size; tid++) {
1709 activateWhenReady(tid);
1710 }
1711
1712 if (cpuWaitList.size() == 0)
1713 contextSwitch = true;
1714 }
1715}
1716
1717template <class Impl>
1718void
1719FullO3CPU<Impl>::updateThreadPriority()
1720{
1721 if (activeThreads.size() > 1) {
1722 //DEFAULT TO ROUND ROBIN SCHEME
1723 //e.g. Move highest priority to end of thread list
1724 list<ThreadID>::iterator list_begin = activeThreads.begin();
1725
1726 unsigned high_thread = *list_begin;
1727
1728 activeThreads.erase(list_begin);
1729
1730 activeThreads.push_back(high_thread);
1731 }
1732}
1733
1734// Forward declaration of FullO3CPU.
1735template class FullO3CPU<O3CPUImpl>;
| 1206 if (tickEvent.scheduled())
1207 tickEvent.squash();
1208}
1209
1210template <class Impl>
1211void
1212FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
1213{
1214 // Flush out any old data from the time buffers.
1215 for (int i = 0; i < timeBuffer.getSize(); ++i) {
1216 timeBuffer.advance();
1217 fetchQueue.advance();
1218 decodeQueue.advance();
1219 renameQueue.advance();
1220 iewQueue.advance();
1221 }
1222
1223 activityRec.reset();
1224
1225 BaseCPU::takeOverFrom(oldCPU);
1226
1227 fetch.takeOverFrom();
1228 decode.takeOverFrom();
1229 rename.takeOverFrom();
1230 iew.takeOverFrom();
1231 commit.takeOverFrom();
1232
1233 assert(!tickEvent.scheduled() || tickEvent.squashed());
1234
1235 // @todo: Figure out how to properly select the tid to put onto
1236 // the active threads list.
1237 ThreadID tid = 0;
1238
1239 list<ThreadID>::iterator isActive =
1240 std::find(activeThreads.begin(), activeThreads.end(), tid);
1241
1242 if (isActive == activeThreads.end()) {
1243 //May Need to Re-code this if the delay variable is the delay
1244 //needed for thread to activate
1245 DPRINTF(O3CPU, "Adding Thread %i to active threads list\n",
1246 tid);
1247
1248 activeThreads.push_back(tid);
1249 }
1250
1251 // Set all statuses to active, schedule the CPU's tick event.
1252 // @todo: Fix up statuses so this is handled properly
1253 ThreadID size = threadContexts.size();
1254 for (ThreadID i = 0; i < size; ++i) {
1255 ThreadContext *tc = threadContexts[i];
1256 if (tc->status() == ThreadContext::Active && _status != Running) {
1257 _status = Running;
1258 reschedule(tickEvent, nextCycle(), true);
1259 }
1260 }
1261 if (!tickEvent.scheduled())
1262 schedule(tickEvent, nextCycle());
1263
1264 lastRunningCycle = curTick();
1265}
1266
1267template <class Impl>
1268TheISA::MiscReg
1269FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid)
1270{
1271 return this->isa[tid].readMiscRegNoEffect(misc_reg);
1272}
1273
1274template <class Impl>
1275TheISA::MiscReg
1276FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
1277{
1278 miscRegfileReads++;
1279 return this->isa[tid].readMiscReg(misc_reg, tcBase(tid));
1280}
1281
1282template <class Impl>
1283void
1284FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
1285 const TheISA::MiscReg &val, ThreadID tid)
1286{
1287 this->isa[tid].setMiscRegNoEffect(misc_reg, val);
1288}
1289
1290template <class Impl>
1291void
1292FullO3CPU<Impl>::setMiscReg(int misc_reg,
1293 const TheISA::MiscReg &val, ThreadID tid)
1294{
1295 miscRegfileWrites++;
1296 this->isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
1297}
1298
1299template <class Impl>
1300uint64_t
1301FullO3CPU<Impl>::readIntReg(int reg_idx)
1302{
1303 intRegfileReads++;
1304 return regFile.readIntReg(reg_idx);
1305}
1306
1307template <class Impl>
1308FloatReg
1309FullO3CPU<Impl>::readFloatReg(int reg_idx)
1310{
1311 fpRegfileReads++;
1312 return regFile.readFloatReg(reg_idx);
1313}
1314
1315template <class Impl>
1316FloatRegBits
1317FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
1318{
1319 fpRegfileReads++;
1320 return regFile.readFloatRegBits(reg_idx);
1321}
1322
1323template <class Impl>
1324void
1325FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
1326{
1327 intRegfileWrites++;
1328 regFile.setIntReg(reg_idx, val);
1329}
1330
1331template <class Impl>
1332void
1333FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
1334{
1335 fpRegfileWrites++;
1336 regFile.setFloatReg(reg_idx, val);
1337}
1338
1339template <class Impl>
1340void
1341FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
1342{
1343 fpRegfileWrites++;
1344 regFile.setFloatRegBits(reg_idx, val);
1345}
1346
1347template <class Impl>
1348uint64_t
1349FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1350{
1351 intRegfileReads++;
1352 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1353
1354 return regFile.readIntReg(phys_reg);
1355}
1356
1357template <class Impl>
1358float
1359FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
1360{
1361 fpRegfileReads++;
1362 int idx = reg_idx + TheISA::NumIntRegs;
1363 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1364
1365 return regFile.readFloatReg(phys_reg);
1366}
1367
1368template <class Impl>
1369uint64_t
1370FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid)
1371{
1372 fpRegfileReads++;
1373 int idx = reg_idx + TheISA::NumIntRegs;
1374 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1375
1376 return regFile.readFloatRegBits(phys_reg);
1377}
1378
1379template <class Impl>
1380void
1381FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
1382{
1383 intRegfileWrites++;
1384 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1385
1386 regFile.setIntReg(phys_reg, val);
1387}
1388
1389template <class Impl>
1390void
1391FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid)
1392{
1393 fpRegfileWrites++;
1394 int idx = reg_idx + TheISA::NumIntRegs;
1395 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1396
1397 regFile.setFloatReg(phys_reg, val);
1398}
1399
1400template <class Impl>
1401void
1402FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid)
1403{
1404 fpRegfileWrites++;
1405 int idx = reg_idx + TheISA::NumIntRegs;
1406 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1407
1408 regFile.setFloatRegBits(phys_reg, val);
1409}
1410
1411template <class Impl>
1412TheISA::PCState
1413FullO3CPU<Impl>::pcState(ThreadID tid)
1414{
1415 return commit.pcState(tid);
1416}
1417
1418template <class Impl>
1419void
1420FullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid)
1421{
1422 commit.pcState(val, tid);
1423}
1424
1425template <class Impl>
1426Addr
1427FullO3CPU<Impl>::instAddr(ThreadID tid)
1428{
1429 return commit.instAddr(tid);
1430}
1431
1432template <class Impl>
1433Addr
1434FullO3CPU<Impl>::nextInstAddr(ThreadID tid)
1435{
1436 return commit.nextInstAddr(tid);
1437}
1438
1439template <class Impl>
1440MicroPC
1441FullO3CPU<Impl>::microPC(ThreadID tid)
1442{
1443 return commit.microPC(tid);
1444}
1445
1446template <class Impl>
1447void
1448FullO3CPU<Impl>::squashFromTC(ThreadID tid)
1449{
1450 this->thread[tid]->inSyscall = true;
1451 this->commit.generateTCEvent(tid);
1452}
1453
1454template <class Impl>
1455typename FullO3CPU<Impl>::ListIt
1456FullO3CPU<Impl>::addInst(DynInstPtr &inst)
1457{
1458 instList.push_back(inst);
1459
1460 return --(instList.end());
1461}
1462
1463template <class Impl>
1464void
1465FullO3CPU<Impl>::instDone(ThreadID tid, DynInstPtr &inst)
1466{
1467 // Keep an instruction count.
1468 if (!inst->isMicroop() || inst->isLastMicroop()) {
1469 thread[tid]->numInst++;
1470 thread[tid]->numInsts++;
1471 committedInsts[tid]++;
1472 totalCommittedInsts++;
1473 }
1474 thread[tid]->numOp++;
1475 thread[tid]->numOps++;
1476 committedOps[tid]++;
1477
1478 system->totalNumInsts++;
1479 // Check for instruction-count-based events.
1480 comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1481 system->instEventQueue.serviceEvents(system->totalNumInsts);
1482}
1483
1484template <class Impl>
1485void
1486FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
1487{
1488 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s "
1489 "[sn:%lli]\n",
1490 inst->threadNumber, inst->pcState(), inst->seqNum);
1491
1492 removeInstsThisCycle = true;
1493
1494 // Remove the front instruction.
1495 removeList.push(inst->getInstListIt());
1496}
1497
1498template <class Impl>
1499void
1500FullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid)
1501{
1502 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1503 " list.\n", tid);
1504
1505 ListIt end_it;
1506
1507 bool rob_empty = false;
1508
1509 if (instList.empty()) {
1510 return;
1511 } else if (rob.isEmpty(/*tid*/)) {
1512 DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1513 end_it = instList.begin();
1514 rob_empty = true;
1515 } else {
1516 end_it = (rob.readTailInst(tid))->getInstListIt();
1517 DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1518 }
1519
1520 removeInstsThisCycle = true;
1521
1522 ListIt inst_it = instList.end();
1523
1524 inst_it--;
1525
1526 // Walk through the instruction list, removing any instructions
1527 // that were inserted after the given instruction iterator, end_it.
1528 while (inst_it != end_it) {
1529 assert(!instList.empty());
1530
1531 squashInstIt(inst_it, tid);
1532
1533 inst_it--;
1534 }
1535
1536 // If the ROB was empty, then we actually need to remove the first
1537 // instruction as well.
1538 if (rob_empty) {
1539 squashInstIt(inst_it, tid);
1540 }
1541}
1542
1543template <class Impl>
1544void
1545FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1546{
1547 assert(!instList.empty());
1548
1549 removeInstsThisCycle = true;
1550
1551 ListIt inst_iter = instList.end();
1552
1553 inst_iter--;
1554
1555 DPRINTF(O3CPU, "Deleting instructions from instruction "
1556 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1557 tid, seq_num, (*inst_iter)->seqNum);
1558
1559 while ((*inst_iter)->seqNum > seq_num) {
1560
1561 bool break_loop = (inst_iter == instList.begin());
1562
1563 squashInstIt(inst_iter, tid);
1564
1565 inst_iter--;
1566
1567 if (break_loop)
1568 break;
1569 }
1570}
1571
1572template <class Impl>
1573inline void
1574FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid)
1575{
1576 if ((*instIt)->threadNumber == tid) {
1577 DPRINTF(O3CPU, "Squashing instruction, "
1578 "[tid:%i] [sn:%lli] PC %s\n",
1579 (*instIt)->threadNumber,
1580 (*instIt)->seqNum,
1581 (*instIt)->pcState());
1582
1583 // Mark it as squashed.
1584 (*instIt)->setSquashed();
1585
1586 // @todo: Formulate a consistent method for deleting
1587 // instructions from the instruction list
1588 // Remove the instruction from the list.
1589 removeList.push(instIt);
1590 }
1591}
1592
1593template <class Impl>
1594void
1595FullO3CPU<Impl>::cleanUpRemovedInsts()
1596{
1597 while (!removeList.empty()) {
1598 DPRINTF(O3CPU, "Removing instruction, "
1599 "[tid:%i] [sn:%lli] PC %s\n",
1600 (*removeList.front())->threadNumber,
1601 (*removeList.front())->seqNum,
1602 (*removeList.front())->pcState());
1603
1604 instList.erase(removeList.front());
1605
1606 removeList.pop();
1607 }
1608
1609 removeInstsThisCycle = false;
1610}
1611/*
1612template <class Impl>
1613void
1614FullO3CPU<Impl>::removeAllInsts()
1615{
1616 instList.clear();
1617}
1618*/
1619template <class Impl>
1620void
1621FullO3CPU<Impl>::dumpInsts()
1622{
1623 int num = 0;
1624
1625 ListIt inst_list_it = instList.begin();
1626
1627 cprintf("Dumping Instruction List\n");
1628
1629 while (inst_list_it != instList.end()) {
1630 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1631 "Squashed:%i\n\n",
1632 num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber,
1633 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1634 (*inst_list_it)->isSquashed());
1635 inst_list_it++;
1636 ++num;
1637 }
1638}
1639/*
1640template <class Impl>
1641void
1642FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
1643{
1644 iew.wakeDependents(inst);
1645}
1646*/
1647template <class Impl>
1648void
1649FullO3CPU<Impl>::wakeCPU()
1650{
1651 if (activityRec.active() || tickEvent.scheduled()) {
1652 DPRINTF(Activity, "CPU already running.\n");
1653 return;
1654 }
1655
1656 DPRINTF(Activity, "Waking up CPU\n");
1657
1658 idleCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
1659 numCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
1660
1661 schedule(tickEvent, nextCycle());
1662}
1663
1664template <class Impl>
1665void
1666FullO3CPU<Impl>::wakeup()
1667{
1668 if (this->thread[0]->status() != ThreadContext::Suspended)
1669 return;
1670
1671 this->wakeCPU();
1672
1673 DPRINTF(Quiesce, "Suspended Processor woken\n");
1674 this->threadContexts[0]->activate();
1675}
1676
1677template <class Impl>
1678ThreadID
1679FullO3CPU<Impl>::getFreeTid()
1680{
1681 for (ThreadID tid = 0; tid < numThreads; tid++) {
1682 if (!tids[tid]) {
1683 tids[tid] = true;
1684 return tid;
1685 }
1686 }
1687
1688 return InvalidThreadID;
1689}
1690
1691template <class Impl>
1692void
1693FullO3CPU<Impl>::doContextSwitch()
1694{
1695 if (contextSwitch) {
1696
1697 //ADD CODE TO DEACTIVE THREAD HERE (???)
1698
1699 ThreadID size = cpuWaitList.size();
1700 for (ThreadID tid = 0; tid < size; tid++) {
1701 activateWhenReady(tid);
1702 }
1703
1704 if (cpuWaitList.size() == 0)
1705 contextSwitch = true;
1706 }
1707}
1708
1709template <class Impl>
1710void
1711FullO3CPU<Impl>::updateThreadPriority()
1712{
1713 if (activeThreads.size() > 1) {
1714 //DEFAULT TO ROUND ROBIN SCHEME
1715 //e.g. Move highest priority to end of thread list
1716 list<ThreadID>::iterator list_begin = activeThreads.begin();
1717
1718 unsigned high_thread = *list_begin;
1719
1720 activeThreads.erase(list_begin);
1721
1722 activeThreads.push_back(high_thread);
1723 }
1724}
1725
1726// Forward declaration of FullO3CPU.
1727template class FullO3CPU<O3CPUImpl>;
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