cpu.cc (8834:21e8d54ecf07) cpu.cc (8850:ed91b534ed04)
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 * Korey Sewell
43 * Rick Strong
44 */
45
46#include "arch/kernel_stats.hh"
47#include "config/the_isa.hh"
48#include "config/use_checker.hh"
49#include "cpu/o3/cpu.hh"
50#include "cpu/o3/isa_specific.hh"
51#include "cpu/o3/thread_context.hh"
52#include "cpu/activity.hh"
53#include "cpu/quiesce_event.hh"
54#include "cpu/simple_thread.hh"
55#include "cpu/thread_context.hh"
56#include "debug/Activity.hh"
57#include "debug/O3CPU.hh"
58#include "debug/Quiesce.hh"
59#include "enums/MemoryMode.hh"
60#include "sim/core.hh"
61#include "sim/full_system.hh"
62#include "sim/process.hh"
63#include "sim/stat_control.hh"
64#include "sim/system.hh"
65
66#if USE_CHECKER
67#include "cpu/checker/cpu.hh"
68#include "cpu/checker/thread_context.hh"
69#endif
70
71#if THE_ISA == ALPHA_ISA
72#include "arch/alpha/osfpal.hh"
73#include "debug/Activity.hh"
74#endif
75
76struct BaseCPUParams;
77
78using namespace TheISA;
79using namespace std;
80
81BaseO3CPU::BaseO3CPU(BaseCPUParams *params)
82 : BaseCPU(params)
83{
84}
85
86void
87BaseO3CPU::regStats()
88{
89 BaseCPU::regStats();
90}
91
92template<class Impl>
93bool
94FullO3CPU<Impl>::IcachePort::recvTiming(PacketPtr pkt)
95{
96 DPRINTF(O3CPU, "Fetch unit received timing\n");
97 if (pkt->isResponse()) {
98 // We shouldn't ever get a block in ownership state
99 assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted()));
100
101 fetch->processCacheCompletion(pkt);
102 }
103 //else Snooped a coherence request, just return
104 return true;
105}
106
107template<class Impl>
108void
109FullO3CPU<Impl>::IcachePort::recvRetry()
110{
111 fetch->recvRetry();
112}
113
114template <class Impl>
115bool
116FullO3CPU<Impl>::DcachePort::recvTiming(PacketPtr pkt)
117{
118 return lsq->recvTiming(pkt);
119}
120
121template <class Impl>
122void
123FullO3CPU<Impl>::DcachePort::recvRetry()
124{
125 lsq->recvRetry();
126}
127
128template <class Impl>
129FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
130 : Event(CPU_Tick_Pri), cpu(c)
131{
132}
133
134template <class Impl>
135void
136FullO3CPU<Impl>::TickEvent::process()
137{
138 cpu->tick();
139}
140
141template <class Impl>
142const char *
143FullO3CPU<Impl>::TickEvent::description() const
144{
145 return "FullO3CPU tick";
146}
147
148template <class Impl>
149FullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent()
150 : Event(CPU_Switch_Pri)
151{
152}
153
154template <class Impl>
155void
156FullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num,
157 FullO3CPU<Impl> *thread_cpu)
158{
159 tid = thread_num;
160 cpu = thread_cpu;
161}
162
163template <class Impl>
164void
165FullO3CPU<Impl>::ActivateThreadEvent::process()
166{
167 cpu->activateThread(tid);
168}
169
170template <class Impl>
171const char *
172FullO3CPU<Impl>::ActivateThreadEvent::description() const
173{
174 return "FullO3CPU \"Activate Thread\"";
175}
176
177template <class Impl>
178FullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent()
179 : Event(CPU_Tick_Pri), tid(0), remove(false), cpu(NULL)
180{
181}
182
183template <class Impl>
184void
185FullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num,
186 FullO3CPU<Impl> *thread_cpu)
187{
188 tid = thread_num;
189 cpu = thread_cpu;
190 remove = false;
191}
192
193template <class Impl>
194void
195FullO3CPU<Impl>::DeallocateContextEvent::process()
196{
197 cpu->deactivateThread(tid);
198 if (remove)
199 cpu->removeThread(tid);
200}
201
202template <class Impl>
203const char *
204FullO3CPU<Impl>::DeallocateContextEvent::description() const
205{
206 return "FullO3CPU \"Deallocate Context\"";
207}
208
209template <class Impl>
210FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
211 : BaseO3CPU(params),
212 itb(params->itb),
213 dtb(params->dtb),
214 tickEvent(this),
215#ifndef NDEBUG
216 instcount(0),
217#endif
218 removeInstsThisCycle(false),
219 fetch(this, params),
220 decode(this, params),
221 rename(this, params),
222 iew(this, params),
223 commit(this, params),
224
225 regFile(this, params->numPhysIntRegs,
226 params->numPhysFloatRegs),
227
228 freeList(params->numThreads,
229 TheISA::NumIntRegs, params->numPhysIntRegs,
230 TheISA::NumFloatRegs, params->numPhysFloatRegs),
231
232 rob(this,
233 params->numROBEntries, params->squashWidth,
234 params->smtROBPolicy, params->smtROBThreshold,
235 params->numThreads),
236
237 scoreboard(params->numThreads,
238 TheISA::NumIntRegs, params->numPhysIntRegs,
239 TheISA::NumFloatRegs, params->numPhysFloatRegs,
240 TheISA::NumMiscRegs * numThreads,
241 TheISA::ZeroReg),
242
243 icachePort(&fetch, this),
244 dcachePort(&iew.ldstQueue, this),
245
246 timeBuffer(params->backComSize, params->forwardComSize),
247 fetchQueue(params->backComSize, params->forwardComSize),
248 decodeQueue(params->backComSize, params->forwardComSize),
249 renameQueue(params->backComSize, params->forwardComSize),
250 iewQueue(params->backComSize, params->forwardComSize),
251 activityRec(name(), NumStages,
252 params->backComSize + params->forwardComSize,
253 params->activity),
254
255 globalSeqNum(1),
256 system(params->system),
257 drainCount(0),
258 deferRegistration(params->defer_registration)
259{
260 if (!deferRegistration) {
261 _status = Running;
262 } else {
263 _status = Idle;
264 }
265
266#if USE_CHECKER
267 if (params->checker) {
268 BaseCPU *temp_checker = params->checker;
269 checker = dynamic_cast<Checker<Impl> *>(temp_checker);
270 checker->setIcachePort(&icachePort);
271 checker->setSystem(params->system);
272 } else {
273 checker = NULL;
274 }
275#endif // USE_CHECKER
276
277 if (!FullSystem) {
278 thread.resize(numThreads);
279 tids.resize(numThreads);
280 }
281
282 // The stages also need their CPU pointer setup. However this
283 // must be done at the upper level CPU because they have pointers
284 // to the upper level CPU, and not this FullO3CPU.
285
286 // Set up Pointers to the activeThreads list for each stage
287 fetch.setActiveThreads(&activeThreads);
288 decode.setActiveThreads(&activeThreads);
289 rename.setActiveThreads(&activeThreads);
290 iew.setActiveThreads(&activeThreads);
291 commit.setActiveThreads(&activeThreads);
292
293 // Give each of the stages the time buffer they will use.
294 fetch.setTimeBuffer(&timeBuffer);
295 decode.setTimeBuffer(&timeBuffer);
296 rename.setTimeBuffer(&timeBuffer);
297 iew.setTimeBuffer(&timeBuffer);
298 commit.setTimeBuffer(&timeBuffer);
299
300 // Also setup each of the stages' queues.
301 fetch.setFetchQueue(&fetchQueue);
302 decode.setFetchQueue(&fetchQueue);
303 commit.setFetchQueue(&fetchQueue);
304 decode.setDecodeQueue(&decodeQueue);
305 rename.setDecodeQueue(&decodeQueue);
306 rename.setRenameQueue(&renameQueue);
307 iew.setRenameQueue(&renameQueue);
308 iew.setIEWQueue(&iewQueue);
309 commit.setIEWQueue(&iewQueue);
310 commit.setRenameQueue(&renameQueue);
311
312 commit.setIEWStage(&iew);
313 rename.setIEWStage(&iew);
314 rename.setCommitStage(&commit);
315
316 ThreadID active_threads;
317 if (FullSystem) {
318 active_threads = 1;
319 } else {
320 active_threads = params->workload.size();
321
322 if (active_threads > Impl::MaxThreads) {
323 panic("Workload Size too large. Increase the 'MaxThreads' "
324 "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) "
325 "or edit your workload size.");
326 }
327 }
328
329 //Make Sure That this a Valid Architeture
330 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs);
331 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
332
333 rename.setScoreboard(&scoreboard);
334 iew.setScoreboard(&scoreboard);
335
336 // Setup the rename map for whichever stages need it.
337 PhysRegIndex lreg_idx = 0;
338 PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs
339
340 for (ThreadID tid = 0; tid < numThreads; tid++) {
341 bool bindRegs = (tid <= active_threads - 1);
342
343 commitRenameMap[tid].init(TheISA::NumIntRegs,
344 params->numPhysIntRegs,
345 lreg_idx, //Index for Logical. Regs
346
347 TheISA::NumFloatRegs,
348 params->numPhysFloatRegs,
349 freg_idx, //Index for Float Regs
350
351 TheISA::NumMiscRegs,
352
353 TheISA::ZeroReg,
354 TheISA::ZeroReg,
355
356 tid,
357 false);
358
359 renameMap[tid].init(TheISA::NumIntRegs,
360 params->numPhysIntRegs,
361 lreg_idx, //Index for Logical. Regs
362
363 TheISA::NumFloatRegs,
364 params->numPhysFloatRegs,
365 freg_idx, //Index for Float Regs
366
367 TheISA::NumMiscRegs,
368
369 TheISA::ZeroReg,
370 TheISA::ZeroReg,
371
372 tid,
373 bindRegs);
374
375 activateThreadEvent[tid].init(tid, this);
376 deallocateContextEvent[tid].init(tid, this);
377 }
378
379 rename.setRenameMap(renameMap);
380 commit.setRenameMap(commitRenameMap);
381
382 // Give renameMap & rename stage access to the freeList;
383 for (ThreadID tid = 0; tid < numThreads; tid++)
384 renameMap[tid].setFreeList(&freeList);
385 rename.setFreeList(&freeList);
386
387 // Setup the ROB for whichever stages need it.
388 commit.setROB(&rob);
389
390 lastRunningCycle = curTick();
391
392 lastActivatedCycle = -1;
393#if 0
394 // Give renameMap & rename stage access to the freeList;
395 for (ThreadID tid = 0; tid < numThreads; tid++)
396 globalSeqNum[tid] = 1;
397#endif
398
399 contextSwitch = false;
400 DPRINTF(O3CPU, "Creating O3CPU object.\n");
401
402 // Setup any thread state.
403 this->thread.resize(this->numThreads);
404
405 for (ThreadID tid = 0; tid < this->numThreads; ++tid) {
406 if (FullSystem) {
407 // SMT is not supported in FS mode yet.
408 assert(this->numThreads == 1);
409 this->thread[tid] = new Thread(this, 0, NULL);
410 } else {
411 if (tid < params->workload.size()) {
412 DPRINTF(O3CPU, "Workload[%i] process is %#x",
413 tid, this->thread[tid]);
414 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
415 (typename Impl::O3CPU *)(this),
416 tid, params->workload[tid]);
417
418 //usedTids[tid] = true;
419 //threadMap[tid] = tid;
420 } else {
421 //Allocate Empty thread so M5 can use later
422 //when scheduling threads to CPU
423 Process* dummy_proc = NULL;
424
425 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
426 (typename Impl::O3CPU *)(this),
427 tid, dummy_proc);
428 //usedTids[tid] = false;
429 }
430 }
431
432 ThreadContext *tc;
433
434 // Setup the TC that will serve as the interface to the threads/CPU.
435 O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>;
436
437 tc = o3_tc;
438
439 // If we're using a checker, then the TC should be the
440 // CheckerThreadContext.
441#if USE_CHECKER
442 if (params->checker) {
443 tc = new CheckerThreadContext<O3ThreadContext<Impl> >(
444 o3_tc, this->checker);
445 }
446#endif
447
448 o3_tc->cpu = (typename Impl::O3CPU *)(this);
449 assert(o3_tc->cpu);
450 o3_tc->thread = this->thread[tid];
451
452 if (FullSystem) {
453 // Setup quiesce event.
454 this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
455 }
456 // Give the thread the TC.
457 this->thread[tid]->tc = tc;
458
459 // Add the TC to the CPU's list of TC's.
460 this->threadContexts.push_back(tc);
461 }
462
463 for (ThreadID tid = 0; tid < this->numThreads; tid++)
464 this->thread[tid]->setFuncExeInst(0);
465
466 lockAddr = 0;
467 lockFlag = false;
468}
469
470template <class Impl>
471FullO3CPU<Impl>::~FullO3CPU()
472{
473}
474
475template <class Impl>
476void
477FullO3CPU<Impl>::regStats()
478{
479 BaseO3CPU::regStats();
480
481 // Register any of the O3CPU's stats here.
482 timesIdled
483 .name(name() + ".timesIdled")
484 .desc("Number of times that the entire CPU went into an idle state and"
485 " unscheduled itself")
486 .prereq(timesIdled);
487
488 idleCycles
489 .name(name() + ".idleCycles")
490 .desc("Total number of cycles that the CPU has spent unscheduled due "
491 "to idling")
492 .prereq(idleCycles);
493
494 quiesceCycles
495 .name(name() + ".quiesceCycles")
496 .desc("Total number of cycles that CPU has spent quiesced or waiting "
497 "for an interrupt")
498 .prereq(quiesceCycles);
499
500 // Number of Instructions simulated
501 // --------------------------------
502 // Should probably be in Base CPU but need templated
503 // MaxThreads so put in here instead
504 committedInsts
505 .init(numThreads)
506 .name(name() + ".committedInsts")
507 .desc("Number of Instructions Simulated");
508
509 committedOps
510 .init(numThreads)
511 .name(name() + ".committedOps")
512 .desc("Number of Ops (including micro ops) Simulated");
513
514 totalCommittedInsts
515 .name(name() + ".committedInsts_total")
516 .desc("Number of Instructions Simulated");
517
518 cpi
519 .name(name() + ".cpi")
520 .desc("CPI: Cycles Per Instruction")
521 .precision(6);
522 cpi = numCycles / committedInsts;
523
524 totalCpi
525 .name(name() + ".cpi_total")
526 .desc("CPI: Total CPI of All Threads")
527 .precision(6);
528 totalCpi = numCycles / totalCommittedInsts;
529
530 ipc
531 .name(name() + ".ipc")
532 .desc("IPC: Instructions Per Cycle")
533 .precision(6);
534 ipc = committedInsts / numCycles;
535
536 totalIpc
537 .name(name() + ".ipc_total")
538 .desc("IPC: Total IPC of All Threads")
539 .precision(6);
540 totalIpc = totalCommittedInsts / numCycles;
541
542 this->fetch.regStats();
543 this->decode.regStats();
544 this->rename.regStats();
545 this->iew.regStats();
546 this->commit.regStats();
547 this->rob.regStats();
548
549 intRegfileReads
550 .name(name() + ".int_regfile_reads")
551 .desc("number of integer regfile reads")
552 .prereq(intRegfileReads);
553
554 intRegfileWrites
555 .name(name() + ".int_regfile_writes")
556 .desc("number of integer regfile writes")
557 .prereq(intRegfileWrites);
558
559 fpRegfileReads
560 .name(name() + ".fp_regfile_reads")
561 .desc("number of floating regfile reads")
562 .prereq(fpRegfileReads);
563
564 fpRegfileWrites
565 .name(name() + ".fp_regfile_writes")
566 .desc("number of floating regfile writes")
567 .prereq(fpRegfileWrites);
568
569 miscRegfileReads
570 .name(name() + ".misc_regfile_reads")
571 .desc("number of misc regfile reads")
572 .prereq(miscRegfileReads);
573
574 miscRegfileWrites
575 .name(name() + ".misc_regfile_writes")
576 .desc("number of misc regfile writes")
577 .prereq(miscRegfileWrites);
578}
579
580template <class Impl>
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 * Korey Sewell
43 * Rick Strong
44 */
45
46#include "arch/kernel_stats.hh"
47#include "config/the_isa.hh"
48#include "config/use_checker.hh"
49#include "cpu/o3/cpu.hh"
50#include "cpu/o3/isa_specific.hh"
51#include "cpu/o3/thread_context.hh"
52#include "cpu/activity.hh"
53#include "cpu/quiesce_event.hh"
54#include "cpu/simple_thread.hh"
55#include "cpu/thread_context.hh"
56#include "debug/Activity.hh"
57#include "debug/O3CPU.hh"
58#include "debug/Quiesce.hh"
59#include "enums/MemoryMode.hh"
60#include "sim/core.hh"
61#include "sim/full_system.hh"
62#include "sim/process.hh"
63#include "sim/stat_control.hh"
64#include "sim/system.hh"
65
66#if USE_CHECKER
67#include "cpu/checker/cpu.hh"
68#include "cpu/checker/thread_context.hh"
69#endif
70
71#if THE_ISA == ALPHA_ISA
72#include "arch/alpha/osfpal.hh"
73#include "debug/Activity.hh"
74#endif
75
76struct BaseCPUParams;
77
78using namespace TheISA;
79using namespace std;
80
81BaseO3CPU::BaseO3CPU(BaseCPUParams *params)
82 : BaseCPU(params)
83{
84}
85
86void
87BaseO3CPU::regStats()
88{
89 BaseCPU::regStats();
90}
91
92template<class Impl>
93bool
94FullO3CPU<Impl>::IcachePort::recvTiming(PacketPtr pkt)
95{
96 DPRINTF(O3CPU, "Fetch unit received timing\n");
97 if (pkt->isResponse()) {
98 // We shouldn't ever get a block in ownership state
99 assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted()));
100
101 fetch->processCacheCompletion(pkt);
102 }
103 //else Snooped a coherence request, just return
104 return true;
105}
106
107template<class Impl>
108void
109FullO3CPU<Impl>::IcachePort::recvRetry()
110{
111 fetch->recvRetry();
112}
113
114template <class Impl>
115bool
116FullO3CPU<Impl>::DcachePort::recvTiming(PacketPtr pkt)
117{
118 return lsq->recvTiming(pkt);
119}
120
121template <class Impl>
122void
123FullO3CPU<Impl>::DcachePort::recvRetry()
124{
125 lsq->recvRetry();
126}
127
128template <class Impl>
129FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
130 : Event(CPU_Tick_Pri), cpu(c)
131{
132}
133
134template <class Impl>
135void
136FullO3CPU<Impl>::TickEvent::process()
137{
138 cpu->tick();
139}
140
141template <class Impl>
142const char *
143FullO3CPU<Impl>::TickEvent::description() const
144{
145 return "FullO3CPU tick";
146}
147
148template <class Impl>
149FullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent()
150 : Event(CPU_Switch_Pri)
151{
152}
153
154template <class Impl>
155void
156FullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num,
157 FullO3CPU<Impl> *thread_cpu)
158{
159 tid = thread_num;
160 cpu = thread_cpu;
161}
162
163template <class Impl>
164void
165FullO3CPU<Impl>::ActivateThreadEvent::process()
166{
167 cpu->activateThread(tid);
168}
169
170template <class Impl>
171const char *
172FullO3CPU<Impl>::ActivateThreadEvent::description() const
173{
174 return "FullO3CPU \"Activate Thread\"";
175}
176
177template <class Impl>
178FullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent()
179 : Event(CPU_Tick_Pri), tid(0), remove(false), cpu(NULL)
180{
181}
182
183template <class Impl>
184void
185FullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num,
186 FullO3CPU<Impl> *thread_cpu)
187{
188 tid = thread_num;
189 cpu = thread_cpu;
190 remove = false;
191}
192
193template <class Impl>
194void
195FullO3CPU<Impl>::DeallocateContextEvent::process()
196{
197 cpu->deactivateThread(tid);
198 if (remove)
199 cpu->removeThread(tid);
200}
201
202template <class Impl>
203const char *
204FullO3CPU<Impl>::DeallocateContextEvent::description() const
205{
206 return "FullO3CPU \"Deallocate Context\"";
207}
208
209template <class Impl>
210FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
211 : BaseO3CPU(params),
212 itb(params->itb),
213 dtb(params->dtb),
214 tickEvent(this),
215#ifndef NDEBUG
216 instcount(0),
217#endif
218 removeInstsThisCycle(false),
219 fetch(this, params),
220 decode(this, params),
221 rename(this, params),
222 iew(this, params),
223 commit(this, params),
224
225 regFile(this, params->numPhysIntRegs,
226 params->numPhysFloatRegs),
227
228 freeList(params->numThreads,
229 TheISA::NumIntRegs, params->numPhysIntRegs,
230 TheISA::NumFloatRegs, params->numPhysFloatRegs),
231
232 rob(this,
233 params->numROBEntries, params->squashWidth,
234 params->smtROBPolicy, params->smtROBThreshold,
235 params->numThreads),
236
237 scoreboard(params->numThreads,
238 TheISA::NumIntRegs, params->numPhysIntRegs,
239 TheISA::NumFloatRegs, params->numPhysFloatRegs,
240 TheISA::NumMiscRegs * numThreads,
241 TheISA::ZeroReg),
242
243 icachePort(&fetch, this),
244 dcachePort(&iew.ldstQueue, this),
245
246 timeBuffer(params->backComSize, params->forwardComSize),
247 fetchQueue(params->backComSize, params->forwardComSize),
248 decodeQueue(params->backComSize, params->forwardComSize),
249 renameQueue(params->backComSize, params->forwardComSize),
250 iewQueue(params->backComSize, params->forwardComSize),
251 activityRec(name(), NumStages,
252 params->backComSize + params->forwardComSize,
253 params->activity),
254
255 globalSeqNum(1),
256 system(params->system),
257 drainCount(0),
258 deferRegistration(params->defer_registration)
259{
260 if (!deferRegistration) {
261 _status = Running;
262 } else {
263 _status = Idle;
264 }
265
266#if USE_CHECKER
267 if (params->checker) {
268 BaseCPU *temp_checker = params->checker;
269 checker = dynamic_cast<Checker<Impl> *>(temp_checker);
270 checker->setIcachePort(&icachePort);
271 checker->setSystem(params->system);
272 } else {
273 checker = NULL;
274 }
275#endif // USE_CHECKER
276
277 if (!FullSystem) {
278 thread.resize(numThreads);
279 tids.resize(numThreads);
280 }
281
282 // The stages also need their CPU pointer setup. However this
283 // must be done at the upper level CPU because they have pointers
284 // to the upper level CPU, and not this FullO3CPU.
285
286 // Set up Pointers to the activeThreads list for each stage
287 fetch.setActiveThreads(&activeThreads);
288 decode.setActiveThreads(&activeThreads);
289 rename.setActiveThreads(&activeThreads);
290 iew.setActiveThreads(&activeThreads);
291 commit.setActiveThreads(&activeThreads);
292
293 // Give each of the stages the time buffer they will use.
294 fetch.setTimeBuffer(&timeBuffer);
295 decode.setTimeBuffer(&timeBuffer);
296 rename.setTimeBuffer(&timeBuffer);
297 iew.setTimeBuffer(&timeBuffer);
298 commit.setTimeBuffer(&timeBuffer);
299
300 // Also setup each of the stages' queues.
301 fetch.setFetchQueue(&fetchQueue);
302 decode.setFetchQueue(&fetchQueue);
303 commit.setFetchQueue(&fetchQueue);
304 decode.setDecodeQueue(&decodeQueue);
305 rename.setDecodeQueue(&decodeQueue);
306 rename.setRenameQueue(&renameQueue);
307 iew.setRenameQueue(&renameQueue);
308 iew.setIEWQueue(&iewQueue);
309 commit.setIEWQueue(&iewQueue);
310 commit.setRenameQueue(&renameQueue);
311
312 commit.setIEWStage(&iew);
313 rename.setIEWStage(&iew);
314 rename.setCommitStage(&commit);
315
316 ThreadID active_threads;
317 if (FullSystem) {
318 active_threads = 1;
319 } else {
320 active_threads = params->workload.size();
321
322 if (active_threads > Impl::MaxThreads) {
323 panic("Workload Size too large. Increase the 'MaxThreads' "
324 "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) "
325 "or edit your workload size.");
326 }
327 }
328
329 //Make Sure That this a Valid Architeture
330 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs);
331 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
332
333 rename.setScoreboard(&scoreboard);
334 iew.setScoreboard(&scoreboard);
335
336 // Setup the rename map for whichever stages need it.
337 PhysRegIndex lreg_idx = 0;
338 PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs
339
340 for (ThreadID tid = 0; tid < numThreads; tid++) {
341 bool bindRegs = (tid <= active_threads - 1);
342
343 commitRenameMap[tid].init(TheISA::NumIntRegs,
344 params->numPhysIntRegs,
345 lreg_idx, //Index for Logical. Regs
346
347 TheISA::NumFloatRegs,
348 params->numPhysFloatRegs,
349 freg_idx, //Index for Float Regs
350
351 TheISA::NumMiscRegs,
352
353 TheISA::ZeroReg,
354 TheISA::ZeroReg,
355
356 tid,
357 false);
358
359 renameMap[tid].init(TheISA::NumIntRegs,
360 params->numPhysIntRegs,
361 lreg_idx, //Index for Logical. Regs
362
363 TheISA::NumFloatRegs,
364 params->numPhysFloatRegs,
365 freg_idx, //Index for Float Regs
366
367 TheISA::NumMiscRegs,
368
369 TheISA::ZeroReg,
370 TheISA::ZeroReg,
371
372 tid,
373 bindRegs);
374
375 activateThreadEvent[tid].init(tid, this);
376 deallocateContextEvent[tid].init(tid, this);
377 }
378
379 rename.setRenameMap(renameMap);
380 commit.setRenameMap(commitRenameMap);
381
382 // Give renameMap & rename stage access to the freeList;
383 for (ThreadID tid = 0; tid < numThreads; tid++)
384 renameMap[tid].setFreeList(&freeList);
385 rename.setFreeList(&freeList);
386
387 // Setup the ROB for whichever stages need it.
388 commit.setROB(&rob);
389
390 lastRunningCycle = curTick();
391
392 lastActivatedCycle = -1;
393#if 0
394 // Give renameMap & rename stage access to the freeList;
395 for (ThreadID tid = 0; tid < numThreads; tid++)
396 globalSeqNum[tid] = 1;
397#endif
398
399 contextSwitch = false;
400 DPRINTF(O3CPU, "Creating O3CPU object.\n");
401
402 // Setup any thread state.
403 this->thread.resize(this->numThreads);
404
405 for (ThreadID tid = 0; tid < this->numThreads; ++tid) {
406 if (FullSystem) {
407 // SMT is not supported in FS mode yet.
408 assert(this->numThreads == 1);
409 this->thread[tid] = new Thread(this, 0, NULL);
410 } else {
411 if (tid < params->workload.size()) {
412 DPRINTF(O3CPU, "Workload[%i] process is %#x",
413 tid, this->thread[tid]);
414 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
415 (typename Impl::O3CPU *)(this),
416 tid, params->workload[tid]);
417
418 //usedTids[tid] = true;
419 //threadMap[tid] = tid;
420 } else {
421 //Allocate Empty thread so M5 can use later
422 //when scheduling threads to CPU
423 Process* dummy_proc = NULL;
424
425 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
426 (typename Impl::O3CPU *)(this),
427 tid, dummy_proc);
428 //usedTids[tid] = false;
429 }
430 }
431
432 ThreadContext *tc;
433
434 // Setup the TC that will serve as the interface to the threads/CPU.
435 O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>;
436
437 tc = o3_tc;
438
439 // If we're using a checker, then the TC should be the
440 // CheckerThreadContext.
441#if USE_CHECKER
442 if (params->checker) {
443 tc = new CheckerThreadContext<O3ThreadContext<Impl> >(
444 o3_tc, this->checker);
445 }
446#endif
447
448 o3_tc->cpu = (typename Impl::O3CPU *)(this);
449 assert(o3_tc->cpu);
450 o3_tc->thread = this->thread[tid];
451
452 if (FullSystem) {
453 // Setup quiesce event.
454 this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
455 }
456 // Give the thread the TC.
457 this->thread[tid]->tc = tc;
458
459 // Add the TC to the CPU's list of TC's.
460 this->threadContexts.push_back(tc);
461 }
462
463 for (ThreadID tid = 0; tid < this->numThreads; tid++)
464 this->thread[tid]->setFuncExeInst(0);
465
466 lockAddr = 0;
467 lockFlag = false;
468}
469
470template <class Impl>
471FullO3CPU<Impl>::~FullO3CPU()
472{
473}
474
475template <class Impl>
476void
477FullO3CPU<Impl>::regStats()
478{
479 BaseO3CPU::regStats();
480
481 // Register any of the O3CPU's stats here.
482 timesIdled
483 .name(name() + ".timesIdled")
484 .desc("Number of times that the entire CPU went into an idle state and"
485 " unscheduled itself")
486 .prereq(timesIdled);
487
488 idleCycles
489 .name(name() + ".idleCycles")
490 .desc("Total number of cycles that the CPU has spent unscheduled due "
491 "to idling")
492 .prereq(idleCycles);
493
494 quiesceCycles
495 .name(name() + ".quiesceCycles")
496 .desc("Total number of cycles that CPU has spent quiesced or waiting "
497 "for an interrupt")
498 .prereq(quiesceCycles);
499
500 // Number of Instructions simulated
501 // --------------------------------
502 // Should probably be in Base CPU but need templated
503 // MaxThreads so put in here instead
504 committedInsts
505 .init(numThreads)
506 .name(name() + ".committedInsts")
507 .desc("Number of Instructions Simulated");
508
509 committedOps
510 .init(numThreads)
511 .name(name() + ".committedOps")
512 .desc("Number of Ops (including micro ops) Simulated");
513
514 totalCommittedInsts
515 .name(name() + ".committedInsts_total")
516 .desc("Number of Instructions Simulated");
517
518 cpi
519 .name(name() + ".cpi")
520 .desc("CPI: Cycles Per Instruction")
521 .precision(6);
522 cpi = numCycles / committedInsts;
523
524 totalCpi
525 .name(name() + ".cpi_total")
526 .desc("CPI: Total CPI of All Threads")
527 .precision(6);
528 totalCpi = numCycles / totalCommittedInsts;
529
530 ipc
531 .name(name() + ".ipc")
532 .desc("IPC: Instructions Per Cycle")
533 .precision(6);
534 ipc = committedInsts / numCycles;
535
536 totalIpc
537 .name(name() + ".ipc_total")
538 .desc("IPC: Total IPC of All Threads")
539 .precision(6);
540 totalIpc = totalCommittedInsts / numCycles;
541
542 this->fetch.regStats();
543 this->decode.regStats();
544 this->rename.regStats();
545 this->iew.regStats();
546 this->commit.regStats();
547 this->rob.regStats();
548
549 intRegfileReads
550 .name(name() + ".int_regfile_reads")
551 .desc("number of integer regfile reads")
552 .prereq(intRegfileReads);
553
554 intRegfileWrites
555 .name(name() + ".int_regfile_writes")
556 .desc("number of integer regfile writes")
557 .prereq(intRegfileWrites);
558
559 fpRegfileReads
560 .name(name() + ".fp_regfile_reads")
561 .desc("number of floating regfile reads")
562 .prereq(fpRegfileReads);
563
564 fpRegfileWrites
565 .name(name() + ".fp_regfile_writes")
566 .desc("number of floating regfile writes")
567 .prereq(fpRegfileWrites);
568
569 miscRegfileReads
570 .name(name() + ".misc_regfile_reads")
571 .desc("number of misc regfile reads")
572 .prereq(miscRegfileReads);
573
574 miscRegfileWrites
575 .name(name() + ".misc_regfile_writes")
576 .desc("number of misc regfile writes")
577 .prereq(miscRegfileWrites);
578}
579
580template <class Impl>
581Port *
582FullO3CPU<Impl>::getPort(const std::string &if_name, int idx)
583{
584 if (if_name == "dcache_port")
585 return &dcachePort;
586 else if (if_name == "icache_port")
587 return &icachePort;
588 else
589 panic("No Such Port\n");
590}
591
592template <class Impl>
593void
594FullO3CPU<Impl>::tick()
595{
596 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
597
598 ++numCycles;
599
600// activity = false;
601
602 //Tick each of the stages
603 fetch.tick();
604
605 decode.tick();
606
607 rename.tick();
608
609 iew.tick();
610
611 commit.tick();
612
613 if (!FullSystem)
614 doContextSwitch();
615
616 // Now advance the time buffers
617 timeBuffer.advance();
618
619 fetchQueue.advance();
620 decodeQueue.advance();
621 renameQueue.advance();
622 iewQueue.advance();
623
624 activityRec.advance();
625
626 if (removeInstsThisCycle) {
627 cleanUpRemovedInsts();
628 }
629
630 if (!tickEvent.scheduled()) {
631 if (_status == SwitchedOut ||
632 getState() == SimObject::Drained) {
633 DPRINTF(O3CPU, "Switched out!\n");
634 // increment stat
635 lastRunningCycle = curTick();
636 } else if (!activityRec.active() || _status == Idle) {
637 DPRINTF(O3CPU, "Idle!\n");
638 lastRunningCycle = curTick();
639 timesIdled++;
640 } else {
641 schedule(tickEvent, nextCycle(curTick() + ticks(1)));
642 DPRINTF(O3CPU, "Scheduling next tick!\n");
643 }
644 }
645
646 if (!FullSystem)
647 updateThreadPriority();
648}
649
650template <class Impl>
651void
652FullO3CPU<Impl>::init()
653{
654 BaseCPU::init();
655
656 // Set inSyscall so that the CPU doesn't squash when initially
657 // setting up registers.
658 for (ThreadID tid = 0; tid < numThreads; ++tid)
659 thread[tid]->inSyscall = true;
660
661 // this CPU could still be unconnected if we are restoring from a
662 // checkpoint and this CPU is to be switched in, thus we can only
663 // do this here if the instruction port is actually connected, if
664 // not we have to do it as part of takeOverFrom
665 if (icachePort.isConnected())
666 fetch.setIcache();
667
668 if (FullSystem) {
669 for (ThreadID tid = 0; tid < numThreads; tid++) {
670 ThreadContext *src_tc = threadContexts[tid];
671 TheISA::initCPU(src_tc, src_tc->contextId());
672 // Initialise the ThreadContext's memory proxies
673 thread[tid]->initMemProxies(thread[tid]->getTC());
674 }
675 }
676
677 // Clear inSyscall.
678 for (int tid = 0; tid < numThreads; ++tid)
679 thread[tid]->inSyscall = false;
680
681 // Initialize stages.
682 fetch.initStage();
683 iew.initStage();
684 rename.initStage();
685 commit.initStage();
686
687 commit.setThreads(thread);
688}
689
690template <class Impl>
691void
692FullO3CPU<Impl>::activateThread(ThreadID tid)
693{
694 list<ThreadID>::iterator isActive =
695 std::find(activeThreads.begin(), activeThreads.end(), tid);
696
697 DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid);
698
699 if (isActive == activeThreads.end()) {
700 DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n",
701 tid);
702
703 activeThreads.push_back(tid);
704 }
705}
706
707template <class Impl>
708void
709FullO3CPU<Impl>::deactivateThread(ThreadID tid)
710{
711 //Remove From Active List, if Active
712 list<ThreadID>::iterator thread_it =
713 std::find(activeThreads.begin(), activeThreads.end(), tid);
714
715 DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid);
716
717 if (thread_it != activeThreads.end()) {
718 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
719 tid);
720 activeThreads.erase(thread_it);
721 }
722}
723
724template <class Impl>
725Counter
726FullO3CPU<Impl>::totalInsts() const
727{
728 Counter total(0);
729
730 ThreadID size = thread.size();
731 for (ThreadID i = 0; i < size; i++)
732 total += thread[i]->numInst;
733
734 return total;
735}
736
737template <class Impl>
738Counter
739FullO3CPU<Impl>::totalOps() const
740{
741 Counter total(0);
742
743 ThreadID size = thread.size();
744 for (ThreadID i = 0; i < size; i++)
745 total += thread[i]->numOp;
746
747 return total;
748}
749
750template <class Impl>
751void
752FullO3CPU<Impl>::activateContext(ThreadID tid, int delay)
753{
754 // Needs to set each stage to running as well.
755 if (delay){
756 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate "
757 "on cycle %d\n", tid, curTick() + ticks(delay));
758 scheduleActivateThreadEvent(tid, delay);
759 } else {
760 activateThread(tid);
761 }
762
763 if (lastActivatedCycle < curTick()) {
764 scheduleTickEvent(delay);
765
766 // Be sure to signal that there's some activity so the CPU doesn't
767 // deschedule itself.
768 activityRec.activity();
769 fetch.wakeFromQuiesce();
770
771 quiesceCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
772
773 lastActivatedCycle = curTick();
774
775 _status = Running;
776 }
777}
778
779template <class Impl>
780bool
781FullO3CPU<Impl>::scheduleDeallocateContext(ThreadID tid, bool remove,
782 int delay)
783{
784 // Schedule removal of thread data from CPU
785 if (delay){
786 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate "
787 "on cycle %d\n", tid, curTick() + ticks(delay));
788 scheduleDeallocateContextEvent(tid, remove, delay);
789 return false;
790 } else {
791 deactivateThread(tid);
792 if (remove)
793 removeThread(tid);
794 return true;
795 }
796}
797
798template <class Impl>
799void
800FullO3CPU<Impl>::suspendContext(ThreadID tid)
801{
802 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
803 bool deallocated = scheduleDeallocateContext(tid, false, 1);
804 // If this was the last thread then unschedule the tick event.
805 if ((activeThreads.size() == 1 && !deallocated) ||
806 activeThreads.size() == 0)
807 unscheduleTickEvent();
808
809 DPRINTF(Quiesce, "Suspending Context\n");
810 lastRunningCycle = curTick();
811 _status = Idle;
812}
813
814template <class Impl>
815void
816FullO3CPU<Impl>::haltContext(ThreadID tid)
817{
818 //For now, this is the same as deallocate
819 DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
820 scheduleDeallocateContext(tid, true, 1);
821}
822
823template <class Impl>
824void
825FullO3CPU<Impl>::insertThread(ThreadID tid)
826{
827 DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
828 // Will change now that the PC and thread state is internal to the CPU
829 // and not in the ThreadContext.
830 ThreadContext *src_tc;
831 if (FullSystem)
832 src_tc = system->threadContexts[tid];
833 else
834 src_tc = tcBase(tid);
835
836 //Bind Int Regs to Rename Map
837 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
838 PhysRegIndex phys_reg = freeList.getIntReg();
839
840 renameMap[tid].setEntry(ireg,phys_reg);
841 scoreboard.setReg(phys_reg);
842 }
843
844 //Bind Float Regs to Rename Map
845 for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
846 PhysRegIndex phys_reg = freeList.getFloatReg();
847
848 renameMap[tid].setEntry(freg,phys_reg);
849 scoreboard.setReg(phys_reg);
850 }
851
852 //Copy Thread Data Into RegFile
853 //this->copyFromTC(tid);
854
855 //Set PC/NPC/NNPC
856 pcState(src_tc->pcState(), tid);
857
858 src_tc->setStatus(ThreadContext::Active);
859
860 activateContext(tid,1);
861
862 //Reset ROB/IQ/LSQ Entries
863 commit.rob->resetEntries();
864 iew.resetEntries();
865}
866
867template <class Impl>
868void
869FullO3CPU<Impl>::removeThread(ThreadID tid)
870{
871 DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
872
873 // Copy Thread Data From RegFile
874 // If thread is suspended, it might be re-allocated
875 // this->copyToTC(tid);
876
877
878 // @todo: 2-27-2008: Fix how we free up rename mappings
879 // here to alleviate the case for double-freeing registers
880 // in SMT workloads.
881
882 // Unbind Int Regs from Rename Map
883 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
884 PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
885
886 scoreboard.unsetReg(phys_reg);
887 freeList.addReg(phys_reg);
888 }
889
890 // Unbind Float Regs from Rename Map
891 for (int freg = TheISA::NumIntRegs; freg < TheISA::NumFloatRegs; freg++) {
892 PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
893
894 scoreboard.unsetReg(phys_reg);
895 freeList.addReg(phys_reg);
896 }
897
898 // Squash Throughout Pipeline
899 DynInstPtr inst = commit.rob->readHeadInst(tid);
900 InstSeqNum squash_seq_num = inst->seqNum;
901 fetch.squash(0, squash_seq_num, inst, tid);
902 decode.squash(tid);
903 rename.squash(squash_seq_num, tid);
904 iew.squash(tid);
905 iew.ldstQueue.squash(squash_seq_num, tid);
906 commit.rob->squash(squash_seq_num, tid);
907
908
909 assert(iew.instQueue.getCount(tid) == 0);
910 assert(iew.ldstQueue.getCount(tid) == 0);
911
912 // Reset ROB/IQ/LSQ Entries
913
914 // Commented out for now. This should be possible to do by
915 // telling all the pipeline stages to drain first, and then
916 // checking until the drain completes. Once the pipeline is
917 // drained, call resetEntries(). - 10-09-06 ktlim
918/*
919 if (activeThreads.size() >= 1) {
920 commit.rob->resetEntries();
921 iew.resetEntries();
922 }
923*/
924}
925
926
927template <class Impl>
928void
929FullO3CPU<Impl>::activateWhenReady(ThreadID tid)
930{
931 DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming"
932 "(e.g. PhysRegs/ROB/IQ/LSQ) \n",
933 tid);
934
935 bool ready = true;
936
937 if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) {
938 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
939 "Phys. Int. Regs.\n",
940 tid);
941 ready = false;
942 } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) {
943 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
944 "Phys. Float. Regs.\n",
945 tid);
946 ready = false;
947 } else if (commit.rob->numFreeEntries() >=
948 commit.rob->entryAmount(activeThreads.size() + 1)) {
949 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
950 "ROB entries.\n",
951 tid);
952 ready = false;
953 } else if (iew.instQueue.numFreeEntries() >=
954 iew.instQueue.entryAmount(activeThreads.size() + 1)) {
955 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
956 "IQ entries.\n",
957 tid);
958 ready = false;
959 } else if (iew.ldstQueue.numFreeEntries() >=
960 iew.ldstQueue.entryAmount(activeThreads.size() + 1)) {
961 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
962 "LSQ entries.\n",
963 tid);
964 ready = false;
965 }
966
967 if (ready) {
968 insertThread(tid);
969
970 contextSwitch = false;
971
972 cpuWaitList.remove(tid);
973 } else {
974 suspendContext(tid);
975
976 //blocks fetch
977 contextSwitch = true;
978
979 //@todo: dont always add to waitlist
980 //do waitlist
981 cpuWaitList.push_back(tid);
982 }
983}
984
985template <class Impl>
986Fault
987FullO3CPU<Impl>::hwrei(ThreadID tid)
988{
989#if THE_ISA == ALPHA_ISA
990 // Need to clear the lock flag upon returning from an interrupt.
991 this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
992
993 this->thread[tid]->kernelStats->hwrei();
994
995 // FIXME: XXX check for interrupts? XXX
996#endif
997 return NoFault;
998}
999
1000template <class Impl>
1001bool
1002FullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid)
1003{
1004#if THE_ISA == ALPHA_ISA
1005 if (this->thread[tid]->kernelStats)
1006 this->thread[tid]->kernelStats->callpal(palFunc,
1007 this->threadContexts[tid]);
1008
1009 switch (palFunc) {
1010 case PAL::halt:
1011 halt();
1012 if (--System::numSystemsRunning == 0)
1013 exitSimLoop("all cpus halted");
1014 break;
1015
1016 case PAL::bpt:
1017 case PAL::bugchk:
1018 if (this->system->breakpoint())
1019 return false;
1020 break;
1021 }
1022#endif
1023 return true;
1024}
1025
1026template <class Impl>
1027Fault
1028FullO3CPU<Impl>::getInterrupts()
1029{
1030 // Check if there are any outstanding interrupts
1031 return this->interrupts->getInterrupt(this->threadContexts[0]);
1032}
1033
1034template <class Impl>
1035void
1036FullO3CPU<Impl>::processInterrupts(Fault interrupt)
1037{
1038 // Check for interrupts here. For now can copy the code that
1039 // exists within isa_fullsys_traits.hh. Also assume that thread 0
1040 // is the one that handles the interrupts.
1041 // @todo: Possibly consolidate the interrupt checking code.
1042 // @todo: Allow other threads to handle interrupts.
1043
1044 assert(interrupt != NoFault);
1045 this->interrupts->updateIntrInfo(this->threadContexts[0]);
1046
1047 DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
1048 this->trap(interrupt, 0, NULL);
1049}
1050
1051template <class Impl>
1052void
1053FullO3CPU<Impl>::trap(Fault fault, ThreadID tid, StaticInstPtr inst)
1054{
1055 // Pass the thread's TC into the invoke method.
1056 fault->invoke(this->threadContexts[tid], inst);
1057}
1058
1059template <class Impl>
1060void
1061FullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid)
1062{
1063 DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid);
1064
1065 DPRINTF(Activity,"Activity: syscall() called.\n");
1066
1067 // Temporarily increase this by one to account for the syscall
1068 // instruction.
1069 ++(this->thread[tid]->funcExeInst);
1070
1071 // Execute the actual syscall.
1072 this->thread[tid]->syscall(callnum);
1073
1074 // Decrease funcExeInst by one as the normal commit will handle
1075 // incrementing it.
1076 --(this->thread[tid]->funcExeInst);
1077}
1078
1079template <class Impl>
1080void
1081FullO3CPU<Impl>::serialize(std::ostream &os)
1082{
1083 SimObject::State so_state = SimObject::getState();
1084 SERIALIZE_ENUM(so_state);
1085 BaseCPU::serialize(os);
1086 nameOut(os, csprintf("%s.tickEvent", name()));
1087 tickEvent.serialize(os);
1088
1089 // Use SimpleThread's ability to checkpoint to make it easier to
1090 // write out the registers. Also make this static so it doesn't
1091 // get instantiated multiple times (causes a panic in statistics).
1092 static SimpleThread temp;
1093
1094 ThreadID size = thread.size();
1095 for (ThreadID i = 0; i < size; i++) {
1096 nameOut(os, csprintf("%s.xc.%i", name(), i));
1097 temp.copyTC(thread[i]->getTC());
1098 temp.serialize(os);
1099 }
1100}
1101
1102template <class Impl>
1103void
1104FullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string &section)
1105{
1106 SimObject::State so_state;
1107 UNSERIALIZE_ENUM(so_state);
1108 BaseCPU::unserialize(cp, section);
1109 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
1110
1111 // Use SimpleThread's ability to checkpoint to make it easier to
1112 // read in the registers. Also make this static so it doesn't
1113 // get instantiated multiple times (causes a panic in statistics).
1114 static SimpleThread temp;
1115
1116 ThreadID size = thread.size();
1117 for (ThreadID i = 0; i < size; i++) {
1118 temp.copyTC(thread[i]->getTC());
1119 temp.unserialize(cp, csprintf("%s.xc.%i", section, i));
1120 thread[i]->getTC()->copyArchRegs(temp.getTC());
1121 }
1122}
1123
1124template <class Impl>
1125unsigned int
1126FullO3CPU<Impl>::drain(Event *drain_event)
1127{
1128 DPRINTF(O3CPU, "Switching out\n");
1129
1130 // If the CPU isn't doing anything, then return immediately.
1131 if (_status == Idle || _status == SwitchedOut) {
1132 return 0;
1133 }
1134
1135 drainCount = 0;
1136 fetch.drain();
1137 decode.drain();
1138 rename.drain();
1139 iew.drain();
1140 commit.drain();
1141
1142 // Wake the CPU and record activity so everything can drain out if
1143 // the CPU was not able to immediately drain.
1144 if (getState() != SimObject::Drained) {
1145 // A bit of a hack...set the drainEvent after all the drain()
1146 // calls have been made, that way if all of the stages drain
1147 // immediately, the signalDrained() function knows not to call
1148 // process on the drain event.
1149 drainEvent = drain_event;
1150
1151 wakeCPU();
1152 activityRec.activity();
1153
1154 return 1;
1155 } else {
1156 return 0;
1157 }
1158}
1159
1160template <class Impl>
1161void
1162FullO3CPU<Impl>::resume()
1163{
1164 fetch.resume();
1165 decode.resume();
1166 rename.resume();
1167 iew.resume();
1168 commit.resume();
1169
1170 changeState(SimObject::Running);
1171
1172 if (_status == SwitchedOut || _status == Idle)
1173 return;
1174
1175 assert(system->getMemoryMode() == Enums::timing);
1176
1177 if (!tickEvent.scheduled())
1178 schedule(tickEvent, nextCycle());
1179 _status = Running;
1180}
1181
1182template <class Impl>
1183void
1184FullO3CPU<Impl>::signalDrained()
1185{
1186 if (++drainCount == NumStages) {
1187 if (tickEvent.scheduled())
1188 tickEvent.squash();
1189
1190 changeState(SimObject::Drained);
1191
1192 BaseCPU::switchOut();
1193
1194 if (drainEvent) {
1195 drainEvent->process();
1196 drainEvent = NULL;
1197 }
1198 }
1199 assert(drainCount <= 5);
1200}
1201
1202template <class Impl>
1203void
1204FullO3CPU<Impl>::switchOut()
1205{
1206 fetch.switchOut();
1207 rename.switchOut();
1208 iew.switchOut();
1209 commit.switchOut();
1210 instList.clear();
1211 while (!removeList.empty()) {
1212 removeList.pop();
1213 }
1214
1215 _status = SwitchedOut;
1216#if USE_CHECKER
1217 if (checker)
1218 checker->switchOut();
1219#endif
1220 if (tickEvent.scheduled())
1221 tickEvent.squash();
1222}
1223
1224template <class Impl>
1225void
1226FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
1227{
1228 // Flush out any old data from the time buffers.
1229 for (int i = 0; i < timeBuffer.getSize(); ++i) {
1230 timeBuffer.advance();
1231 fetchQueue.advance();
1232 decodeQueue.advance();
1233 renameQueue.advance();
1234 iewQueue.advance();
1235 }
1236
1237 activityRec.reset();
1238
1239 BaseCPU::takeOverFrom(oldCPU);
1240
1241 fetch.takeOverFrom();
1242 decode.takeOverFrom();
1243 rename.takeOverFrom();
1244 iew.takeOverFrom();
1245 commit.takeOverFrom();
1246
1247 assert(!tickEvent.scheduled() || tickEvent.squashed());
1248
1249 // @todo: Figure out how to properly select the tid to put onto
1250 // the active threads list.
1251 ThreadID tid = 0;
1252
1253 list<ThreadID>::iterator isActive =
1254 std::find(activeThreads.begin(), activeThreads.end(), tid);
1255
1256 if (isActive == activeThreads.end()) {
1257 //May Need to Re-code this if the delay variable is the delay
1258 //needed for thread to activate
1259 DPRINTF(O3CPU, "Adding Thread %i to active threads list\n",
1260 tid);
1261
1262 activeThreads.push_back(tid);
1263 }
1264
1265 // Set all statuses to active, schedule the CPU's tick event.
1266 // @todo: Fix up statuses so this is handled properly
1267 ThreadID size = threadContexts.size();
1268 for (ThreadID i = 0; i < size; ++i) {
1269 ThreadContext *tc = threadContexts[i];
1270 if (tc->status() == ThreadContext::Active && _status != Running) {
1271 _status = Running;
1272 reschedule(tickEvent, nextCycle(), true);
1273 }
1274 }
1275 if (!tickEvent.scheduled())
1276 schedule(tickEvent, nextCycle());
1277
1278 lastRunningCycle = curTick();
1279}
1280
1281template <class Impl>
1282TheISA::MiscReg
1283FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid)
1284{
1285 return this->isa[tid].readMiscRegNoEffect(misc_reg);
1286}
1287
1288template <class Impl>
1289TheISA::MiscReg
1290FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
1291{
1292 miscRegfileReads++;
1293 return this->isa[tid].readMiscReg(misc_reg, tcBase(tid));
1294}
1295
1296template <class Impl>
1297void
1298FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
1299 const TheISA::MiscReg &val, ThreadID tid)
1300{
1301 this->isa[tid].setMiscRegNoEffect(misc_reg, val);
1302}
1303
1304template <class Impl>
1305void
1306FullO3CPU<Impl>::setMiscReg(int misc_reg,
1307 const TheISA::MiscReg &val, ThreadID tid)
1308{
1309 miscRegfileWrites++;
1310 this->isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
1311}
1312
1313template <class Impl>
1314uint64_t
1315FullO3CPU<Impl>::readIntReg(int reg_idx)
1316{
1317 intRegfileReads++;
1318 return regFile.readIntReg(reg_idx);
1319}
1320
1321template <class Impl>
1322FloatReg
1323FullO3CPU<Impl>::readFloatReg(int reg_idx)
1324{
1325 fpRegfileReads++;
1326 return regFile.readFloatReg(reg_idx);
1327}
1328
1329template <class Impl>
1330FloatRegBits
1331FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
1332{
1333 fpRegfileReads++;
1334 return regFile.readFloatRegBits(reg_idx);
1335}
1336
1337template <class Impl>
1338void
1339FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
1340{
1341 intRegfileWrites++;
1342 regFile.setIntReg(reg_idx, val);
1343}
1344
1345template <class Impl>
1346void
1347FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
1348{
1349 fpRegfileWrites++;
1350 regFile.setFloatReg(reg_idx, val);
1351}
1352
1353template <class Impl>
1354void
1355FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
1356{
1357 fpRegfileWrites++;
1358 regFile.setFloatRegBits(reg_idx, val);
1359}
1360
1361template <class Impl>
1362uint64_t
1363FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1364{
1365 intRegfileReads++;
1366 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1367
1368 return regFile.readIntReg(phys_reg);
1369}
1370
1371template <class Impl>
1372float
1373FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
1374{
1375 fpRegfileReads++;
1376 int idx = reg_idx + TheISA::NumIntRegs;
1377 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1378
1379 return regFile.readFloatReg(phys_reg);
1380}
1381
1382template <class Impl>
1383uint64_t
1384FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid)
1385{
1386 fpRegfileReads++;
1387 int idx = reg_idx + TheISA::NumIntRegs;
1388 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1389
1390 return regFile.readFloatRegBits(phys_reg);
1391}
1392
1393template <class Impl>
1394void
1395FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
1396{
1397 intRegfileWrites++;
1398 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1399
1400 regFile.setIntReg(phys_reg, val);
1401}
1402
1403template <class Impl>
1404void
1405FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid)
1406{
1407 fpRegfileWrites++;
1408 int idx = reg_idx + TheISA::NumIntRegs;
1409 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1410
1411 regFile.setFloatReg(phys_reg, val);
1412}
1413
1414template <class Impl>
1415void
1416FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid)
1417{
1418 fpRegfileWrites++;
1419 int idx = reg_idx + TheISA::NumIntRegs;
1420 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1421
1422 regFile.setFloatRegBits(phys_reg, val);
1423}
1424
1425template <class Impl>
1426TheISA::PCState
1427FullO3CPU<Impl>::pcState(ThreadID tid)
1428{
1429 return commit.pcState(tid);
1430}
1431
1432template <class Impl>
1433void
1434FullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid)
1435{
1436 commit.pcState(val, tid);
1437}
1438
1439template <class Impl>
1440Addr
1441FullO3CPU<Impl>::instAddr(ThreadID tid)
1442{
1443 return commit.instAddr(tid);
1444}
1445
1446template <class Impl>
1447Addr
1448FullO3CPU<Impl>::nextInstAddr(ThreadID tid)
1449{
1450 return commit.nextInstAddr(tid);
1451}
1452
1453template <class Impl>
1454MicroPC
1455FullO3CPU<Impl>::microPC(ThreadID tid)
1456{
1457 return commit.microPC(tid);
1458}
1459
1460template <class Impl>
1461void
1462FullO3CPU<Impl>::squashFromTC(ThreadID tid)
1463{
1464 this->thread[tid]->inSyscall = true;
1465 this->commit.generateTCEvent(tid);
1466}
1467
1468template <class Impl>
1469typename FullO3CPU<Impl>::ListIt
1470FullO3CPU<Impl>::addInst(DynInstPtr &inst)
1471{
1472 instList.push_back(inst);
1473
1474 return --(instList.end());
1475}
1476
1477template <class Impl>
1478void
1479FullO3CPU<Impl>::instDone(ThreadID tid, DynInstPtr &inst)
1480{
1481 // Keep an instruction count.
1482 if (!inst->isMicroop() || inst->isLastMicroop()) {
1483 thread[tid]->numInst++;
1484 thread[tid]->numInsts++;
1485 committedInsts[tid]++;
1486 totalCommittedInsts++;
1487 }
1488 thread[tid]->numOp++;
1489 thread[tid]->numOps++;
1490 committedOps[tid]++;
1491
1492 system->totalNumInsts++;
1493 // Check for instruction-count-based events.
1494 comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1495 system->instEventQueue.serviceEvents(system->totalNumInsts);
1496}
1497
1498template <class Impl>
1499void
1500FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
1501{
1502 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s "
1503 "[sn:%lli]\n",
1504 inst->threadNumber, inst->pcState(), inst->seqNum);
1505
1506 removeInstsThisCycle = true;
1507
1508 // Remove the front instruction.
1509 removeList.push(inst->getInstListIt());
1510}
1511
1512template <class Impl>
1513void
1514FullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid)
1515{
1516 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1517 " list.\n", tid);
1518
1519 ListIt end_it;
1520
1521 bool rob_empty = false;
1522
1523 if (instList.empty()) {
1524 return;
1525 } else if (rob.isEmpty(/*tid*/)) {
1526 DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1527 end_it = instList.begin();
1528 rob_empty = true;
1529 } else {
1530 end_it = (rob.readTailInst(tid))->getInstListIt();
1531 DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1532 }
1533
1534 removeInstsThisCycle = true;
1535
1536 ListIt inst_it = instList.end();
1537
1538 inst_it--;
1539
1540 // Walk through the instruction list, removing any instructions
1541 // that were inserted after the given instruction iterator, end_it.
1542 while (inst_it != end_it) {
1543 assert(!instList.empty());
1544
1545 squashInstIt(inst_it, tid);
1546
1547 inst_it--;
1548 }
1549
1550 // If the ROB was empty, then we actually need to remove the first
1551 // instruction as well.
1552 if (rob_empty) {
1553 squashInstIt(inst_it, tid);
1554 }
1555}
1556
1557template <class Impl>
1558void
1559FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1560{
1561 assert(!instList.empty());
1562
1563 removeInstsThisCycle = true;
1564
1565 ListIt inst_iter = instList.end();
1566
1567 inst_iter--;
1568
1569 DPRINTF(O3CPU, "Deleting instructions from instruction "
1570 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1571 tid, seq_num, (*inst_iter)->seqNum);
1572
1573 while ((*inst_iter)->seqNum > seq_num) {
1574
1575 bool break_loop = (inst_iter == instList.begin());
1576
1577 squashInstIt(inst_iter, tid);
1578
1579 inst_iter--;
1580
1581 if (break_loop)
1582 break;
1583 }
1584}
1585
1586template <class Impl>
1587inline void
1588FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid)
1589{
1590 if ((*instIt)->threadNumber == tid) {
1591 DPRINTF(O3CPU, "Squashing instruction, "
1592 "[tid:%i] [sn:%lli] PC %s\n",
1593 (*instIt)->threadNumber,
1594 (*instIt)->seqNum,
1595 (*instIt)->pcState());
1596
1597 // Mark it as squashed.
1598 (*instIt)->setSquashed();
1599
1600 // @todo: Formulate a consistent method for deleting
1601 // instructions from the instruction list
1602 // Remove the instruction from the list.
1603 removeList.push(instIt);
1604 }
1605}
1606
1607template <class Impl>
1608void
1609FullO3CPU<Impl>::cleanUpRemovedInsts()
1610{
1611 while (!removeList.empty()) {
1612 DPRINTF(O3CPU, "Removing instruction, "
1613 "[tid:%i] [sn:%lli] PC %s\n",
1614 (*removeList.front())->threadNumber,
1615 (*removeList.front())->seqNum,
1616 (*removeList.front())->pcState());
1617
1618 instList.erase(removeList.front());
1619
1620 removeList.pop();
1621 }
1622
1623 removeInstsThisCycle = false;
1624}
1625/*
1626template <class Impl>
1627void
1628FullO3CPU<Impl>::removeAllInsts()
1629{
1630 instList.clear();
1631}
1632*/
1633template <class Impl>
1634void
1635FullO3CPU<Impl>::dumpInsts()
1636{
1637 int num = 0;
1638
1639 ListIt inst_list_it = instList.begin();
1640
1641 cprintf("Dumping Instruction List\n");
1642
1643 while (inst_list_it != instList.end()) {
1644 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1645 "Squashed:%i\n\n",
1646 num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber,
1647 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1648 (*inst_list_it)->isSquashed());
1649 inst_list_it++;
1650 ++num;
1651 }
1652}
1653/*
1654template <class Impl>
1655void
1656FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
1657{
1658 iew.wakeDependents(inst);
1659}
1660*/
1661template <class Impl>
1662void
1663FullO3CPU<Impl>::wakeCPU()
1664{
1665 if (activityRec.active() || tickEvent.scheduled()) {
1666 DPRINTF(Activity, "CPU already running.\n");
1667 return;
1668 }
1669
1670 DPRINTF(Activity, "Waking up CPU\n");
1671
1672 idleCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
1673 numCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
1674
1675 schedule(tickEvent, nextCycle());
1676}
1677
1678template <class Impl>
1679void
1680FullO3CPU<Impl>::wakeup()
1681{
1682 if (this->thread[0]->status() != ThreadContext::Suspended)
1683 return;
1684
1685 this->wakeCPU();
1686
1687 DPRINTF(Quiesce, "Suspended Processor woken\n");
1688 this->threadContexts[0]->activate();
1689}
1690
1691template <class Impl>
1692ThreadID
1693FullO3CPU<Impl>::getFreeTid()
1694{
1695 for (ThreadID tid = 0; tid < numThreads; tid++) {
1696 if (!tids[tid]) {
1697 tids[tid] = true;
1698 return tid;
1699 }
1700 }
1701
1702 return InvalidThreadID;
1703}
1704
1705template <class Impl>
1706void
1707FullO3CPU<Impl>::doContextSwitch()
1708{
1709 if (contextSwitch) {
1710
1711 //ADD CODE TO DEACTIVE THREAD HERE (???)
1712
1713 ThreadID size = cpuWaitList.size();
1714 for (ThreadID tid = 0; tid < size; tid++) {
1715 activateWhenReady(tid);
1716 }
1717
1718 if (cpuWaitList.size() == 0)
1719 contextSwitch = true;
1720 }
1721}
1722
1723template <class Impl>
1724void
1725FullO3CPU<Impl>::updateThreadPriority()
1726{
1727 if (activeThreads.size() > 1) {
1728 //DEFAULT TO ROUND ROBIN SCHEME
1729 //e.g. Move highest priority to end of thread list
1730 list<ThreadID>::iterator list_begin = activeThreads.begin();
1731
1732 unsigned high_thread = *list_begin;
1733
1734 activeThreads.erase(list_begin);
1735
1736 activeThreads.push_back(high_thread);
1737 }
1738}
1739
1740// Forward declaration of FullO3CPU.
1741template class FullO3CPU<O3CPUImpl>;
581void
582FullO3CPU<Impl>::tick()
583{
584 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
585
586 ++numCycles;
587
588// activity = false;
589
590 //Tick each of the stages
591 fetch.tick();
592
593 decode.tick();
594
595 rename.tick();
596
597 iew.tick();
598
599 commit.tick();
600
601 if (!FullSystem)
602 doContextSwitch();
603
604 // Now advance the time buffers
605 timeBuffer.advance();
606
607 fetchQueue.advance();
608 decodeQueue.advance();
609 renameQueue.advance();
610 iewQueue.advance();
611
612 activityRec.advance();
613
614 if (removeInstsThisCycle) {
615 cleanUpRemovedInsts();
616 }
617
618 if (!tickEvent.scheduled()) {
619 if (_status == SwitchedOut ||
620 getState() == SimObject::Drained) {
621 DPRINTF(O3CPU, "Switched out!\n");
622 // increment stat
623 lastRunningCycle = curTick();
624 } else if (!activityRec.active() || _status == Idle) {
625 DPRINTF(O3CPU, "Idle!\n");
626 lastRunningCycle = curTick();
627 timesIdled++;
628 } else {
629 schedule(tickEvent, nextCycle(curTick() + ticks(1)));
630 DPRINTF(O3CPU, "Scheduling next tick!\n");
631 }
632 }
633
634 if (!FullSystem)
635 updateThreadPriority();
636}
637
638template <class Impl>
639void
640FullO3CPU<Impl>::init()
641{
642 BaseCPU::init();
643
644 // Set inSyscall so that the CPU doesn't squash when initially
645 // setting up registers.
646 for (ThreadID tid = 0; tid < numThreads; ++tid)
647 thread[tid]->inSyscall = true;
648
649 // this CPU could still be unconnected if we are restoring from a
650 // checkpoint and this CPU is to be switched in, thus we can only
651 // do this here if the instruction port is actually connected, if
652 // not we have to do it as part of takeOverFrom
653 if (icachePort.isConnected())
654 fetch.setIcache();
655
656 if (FullSystem) {
657 for (ThreadID tid = 0; tid < numThreads; tid++) {
658 ThreadContext *src_tc = threadContexts[tid];
659 TheISA::initCPU(src_tc, src_tc->contextId());
660 // Initialise the ThreadContext's memory proxies
661 thread[tid]->initMemProxies(thread[tid]->getTC());
662 }
663 }
664
665 // Clear inSyscall.
666 for (int tid = 0; tid < numThreads; ++tid)
667 thread[tid]->inSyscall = false;
668
669 // Initialize stages.
670 fetch.initStage();
671 iew.initStage();
672 rename.initStage();
673 commit.initStage();
674
675 commit.setThreads(thread);
676}
677
678template <class Impl>
679void
680FullO3CPU<Impl>::activateThread(ThreadID tid)
681{
682 list<ThreadID>::iterator isActive =
683 std::find(activeThreads.begin(), activeThreads.end(), tid);
684
685 DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid);
686
687 if (isActive == activeThreads.end()) {
688 DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n",
689 tid);
690
691 activeThreads.push_back(tid);
692 }
693}
694
695template <class Impl>
696void
697FullO3CPU<Impl>::deactivateThread(ThreadID tid)
698{
699 //Remove From Active List, if Active
700 list<ThreadID>::iterator thread_it =
701 std::find(activeThreads.begin(), activeThreads.end(), tid);
702
703 DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid);
704
705 if (thread_it != activeThreads.end()) {
706 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
707 tid);
708 activeThreads.erase(thread_it);
709 }
710}
711
712template <class Impl>
713Counter
714FullO3CPU<Impl>::totalInsts() const
715{
716 Counter total(0);
717
718 ThreadID size = thread.size();
719 for (ThreadID i = 0; i < size; i++)
720 total += thread[i]->numInst;
721
722 return total;
723}
724
725template <class Impl>
726Counter
727FullO3CPU<Impl>::totalOps() const
728{
729 Counter total(0);
730
731 ThreadID size = thread.size();
732 for (ThreadID i = 0; i < size; i++)
733 total += thread[i]->numOp;
734
735 return total;
736}
737
738template <class Impl>
739void
740FullO3CPU<Impl>::activateContext(ThreadID tid, int delay)
741{
742 // Needs to set each stage to running as well.
743 if (delay){
744 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate "
745 "on cycle %d\n", tid, curTick() + ticks(delay));
746 scheduleActivateThreadEvent(tid, delay);
747 } else {
748 activateThread(tid);
749 }
750
751 if (lastActivatedCycle < curTick()) {
752 scheduleTickEvent(delay);
753
754 // Be sure to signal that there's some activity so the CPU doesn't
755 // deschedule itself.
756 activityRec.activity();
757 fetch.wakeFromQuiesce();
758
759 quiesceCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
760
761 lastActivatedCycle = curTick();
762
763 _status = Running;
764 }
765}
766
767template <class Impl>
768bool
769FullO3CPU<Impl>::scheduleDeallocateContext(ThreadID tid, bool remove,
770 int delay)
771{
772 // Schedule removal of thread data from CPU
773 if (delay){
774 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate "
775 "on cycle %d\n", tid, curTick() + ticks(delay));
776 scheduleDeallocateContextEvent(tid, remove, delay);
777 return false;
778 } else {
779 deactivateThread(tid);
780 if (remove)
781 removeThread(tid);
782 return true;
783 }
784}
785
786template <class Impl>
787void
788FullO3CPU<Impl>::suspendContext(ThreadID tid)
789{
790 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
791 bool deallocated = scheduleDeallocateContext(tid, false, 1);
792 // If this was the last thread then unschedule the tick event.
793 if ((activeThreads.size() == 1 && !deallocated) ||
794 activeThreads.size() == 0)
795 unscheduleTickEvent();
796
797 DPRINTF(Quiesce, "Suspending Context\n");
798 lastRunningCycle = curTick();
799 _status = Idle;
800}
801
802template <class Impl>
803void
804FullO3CPU<Impl>::haltContext(ThreadID tid)
805{
806 //For now, this is the same as deallocate
807 DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
808 scheduleDeallocateContext(tid, true, 1);
809}
810
811template <class Impl>
812void
813FullO3CPU<Impl>::insertThread(ThreadID tid)
814{
815 DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
816 // Will change now that the PC and thread state is internal to the CPU
817 // and not in the ThreadContext.
818 ThreadContext *src_tc;
819 if (FullSystem)
820 src_tc = system->threadContexts[tid];
821 else
822 src_tc = tcBase(tid);
823
824 //Bind Int Regs to Rename Map
825 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
826 PhysRegIndex phys_reg = freeList.getIntReg();
827
828 renameMap[tid].setEntry(ireg,phys_reg);
829 scoreboard.setReg(phys_reg);
830 }
831
832 //Bind Float Regs to Rename Map
833 for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
834 PhysRegIndex phys_reg = freeList.getFloatReg();
835
836 renameMap[tid].setEntry(freg,phys_reg);
837 scoreboard.setReg(phys_reg);
838 }
839
840 //Copy Thread Data Into RegFile
841 //this->copyFromTC(tid);
842
843 //Set PC/NPC/NNPC
844 pcState(src_tc->pcState(), tid);
845
846 src_tc->setStatus(ThreadContext::Active);
847
848 activateContext(tid,1);
849
850 //Reset ROB/IQ/LSQ Entries
851 commit.rob->resetEntries();
852 iew.resetEntries();
853}
854
855template <class Impl>
856void
857FullO3CPU<Impl>::removeThread(ThreadID tid)
858{
859 DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
860
861 // Copy Thread Data From RegFile
862 // If thread is suspended, it might be re-allocated
863 // this->copyToTC(tid);
864
865
866 // @todo: 2-27-2008: Fix how we free up rename mappings
867 // here to alleviate the case for double-freeing registers
868 // in SMT workloads.
869
870 // Unbind Int Regs from Rename Map
871 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
872 PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
873
874 scoreboard.unsetReg(phys_reg);
875 freeList.addReg(phys_reg);
876 }
877
878 // Unbind Float Regs from Rename Map
879 for (int freg = TheISA::NumIntRegs; freg < TheISA::NumFloatRegs; freg++) {
880 PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
881
882 scoreboard.unsetReg(phys_reg);
883 freeList.addReg(phys_reg);
884 }
885
886 // Squash Throughout Pipeline
887 DynInstPtr inst = commit.rob->readHeadInst(tid);
888 InstSeqNum squash_seq_num = inst->seqNum;
889 fetch.squash(0, squash_seq_num, inst, tid);
890 decode.squash(tid);
891 rename.squash(squash_seq_num, tid);
892 iew.squash(tid);
893 iew.ldstQueue.squash(squash_seq_num, tid);
894 commit.rob->squash(squash_seq_num, tid);
895
896
897 assert(iew.instQueue.getCount(tid) == 0);
898 assert(iew.ldstQueue.getCount(tid) == 0);
899
900 // Reset ROB/IQ/LSQ Entries
901
902 // Commented out for now. This should be possible to do by
903 // telling all the pipeline stages to drain first, and then
904 // checking until the drain completes. Once the pipeline is
905 // drained, call resetEntries(). - 10-09-06 ktlim
906/*
907 if (activeThreads.size() >= 1) {
908 commit.rob->resetEntries();
909 iew.resetEntries();
910 }
911*/
912}
913
914
915template <class Impl>
916void
917FullO3CPU<Impl>::activateWhenReady(ThreadID tid)
918{
919 DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming"
920 "(e.g. PhysRegs/ROB/IQ/LSQ) \n",
921 tid);
922
923 bool ready = true;
924
925 if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) {
926 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
927 "Phys. Int. Regs.\n",
928 tid);
929 ready = false;
930 } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) {
931 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
932 "Phys. Float. Regs.\n",
933 tid);
934 ready = false;
935 } else if (commit.rob->numFreeEntries() >=
936 commit.rob->entryAmount(activeThreads.size() + 1)) {
937 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
938 "ROB entries.\n",
939 tid);
940 ready = false;
941 } else if (iew.instQueue.numFreeEntries() >=
942 iew.instQueue.entryAmount(activeThreads.size() + 1)) {
943 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
944 "IQ entries.\n",
945 tid);
946 ready = false;
947 } else if (iew.ldstQueue.numFreeEntries() >=
948 iew.ldstQueue.entryAmount(activeThreads.size() + 1)) {
949 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
950 "LSQ entries.\n",
951 tid);
952 ready = false;
953 }
954
955 if (ready) {
956 insertThread(tid);
957
958 contextSwitch = false;
959
960 cpuWaitList.remove(tid);
961 } else {
962 suspendContext(tid);
963
964 //blocks fetch
965 contextSwitch = true;
966
967 //@todo: dont always add to waitlist
968 //do waitlist
969 cpuWaitList.push_back(tid);
970 }
971}
972
973template <class Impl>
974Fault
975FullO3CPU<Impl>::hwrei(ThreadID tid)
976{
977#if THE_ISA == ALPHA_ISA
978 // Need to clear the lock flag upon returning from an interrupt.
979 this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
980
981 this->thread[tid]->kernelStats->hwrei();
982
983 // FIXME: XXX check for interrupts? XXX
984#endif
985 return NoFault;
986}
987
988template <class Impl>
989bool
990FullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid)
991{
992#if THE_ISA == ALPHA_ISA
993 if (this->thread[tid]->kernelStats)
994 this->thread[tid]->kernelStats->callpal(palFunc,
995 this->threadContexts[tid]);
996
997 switch (palFunc) {
998 case PAL::halt:
999 halt();
1000 if (--System::numSystemsRunning == 0)
1001 exitSimLoop("all cpus halted");
1002 break;
1003
1004 case PAL::bpt:
1005 case PAL::bugchk:
1006 if (this->system->breakpoint())
1007 return false;
1008 break;
1009 }
1010#endif
1011 return true;
1012}
1013
1014template <class Impl>
1015Fault
1016FullO3CPU<Impl>::getInterrupts()
1017{
1018 // Check if there are any outstanding interrupts
1019 return this->interrupts->getInterrupt(this->threadContexts[0]);
1020}
1021
1022template <class Impl>
1023void
1024FullO3CPU<Impl>::processInterrupts(Fault interrupt)
1025{
1026 // Check for interrupts here. For now can copy the code that
1027 // exists within isa_fullsys_traits.hh. Also assume that thread 0
1028 // is the one that handles the interrupts.
1029 // @todo: Possibly consolidate the interrupt checking code.
1030 // @todo: Allow other threads to handle interrupts.
1031
1032 assert(interrupt != NoFault);
1033 this->interrupts->updateIntrInfo(this->threadContexts[0]);
1034
1035 DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
1036 this->trap(interrupt, 0, NULL);
1037}
1038
1039template <class Impl>
1040void
1041FullO3CPU<Impl>::trap(Fault fault, ThreadID tid, StaticInstPtr inst)
1042{
1043 // Pass the thread's TC into the invoke method.
1044 fault->invoke(this->threadContexts[tid], inst);
1045}
1046
1047template <class Impl>
1048void
1049FullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid)
1050{
1051 DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid);
1052
1053 DPRINTF(Activity,"Activity: syscall() called.\n");
1054
1055 // Temporarily increase this by one to account for the syscall
1056 // instruction.
1057 ++(this->thread[tid]->funcExeInst);
1058
1059 // Execute the actual syscall.
1060 this->thread[tid]->syscall(callnum);
1061
1062 // Decrease funcExeInst by one as the normal commit will handle
1063 // incrementing it.
1064 --(this->thread[tid]->funcExeInst);
1065}
1066
1067template <class Impl>
1068void
1069FullO3CPU<Impl>::serialize(std::ostream &os)
1070{
1071 SimObject::State so_state = SimObject::getState();
1072 SERIALIZE_ENUM(so_state);
1073 BaseCPU::serialize(os);
1074 nameOut(os, csprintf("%s.tickEvent", name()));
1075 tickEvent.serialize(os);
1076
1077 // Use SimpleThread's ability to checkpoint to make it easier to
1078 // write out the registers. Also make this static so it doesn't
1079 // get instantiated multiple times (causes a panic in statistics).
1080 static SimpleThread temp;
1081
1082 ThreadID size = thread.size();
1083 for (ThreadID i = 0; i < size; i++) {
1084 nameOut(os, csprintf("%s.xc.%i", name(), i));
1085 temp.copyTC(thread[i]->getTC());
1086 temp.serialize(os);
1087 }
1088}
1089
1090template <class Impl>
1091void
1092FullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string &section)
1093{
1094 SimObject::State so_state;
1095 UNSERIALIZE_ENUM(so_state);
1096 BaseCPU::unserialize(cp, section);
1097 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
1098
1099 // Use SimpleThread's ability to checkpoint to make it easier to
1100 // read in the registers. Also make this static so it doesn't
1101 // get instantiated multiple times (causes a panic in statistics).
1102 static SimpleThread temp;
1103
1104 ThreadID size = thread.size();
1105 for (ThreadID i = 0; i < size; i++) {
1106 temp.copyTC(thread[i]->getTC());
1107 temp.unserialize(cp, csprintf("%s.xc.%i", section, i));
1108 thread[i]->getTC()->copyArchRegs(temp.getTC());
1109 }
1110}
1111
1112template <class Impl>
1113unsigned int
1114FullO3CPU<Impl>::drain(Event *drain_event)
1115{
1116 DPRINTF(O3CPU, "Switching out\n");
1117
1118 // If the CPU isn't doing anything, then return immediately.
1119 if (_status == Idle || _status == SwitchedOut) {
1120 return 0;
1121 }
1122
1123 drainCount = 0;
1124 fetch.drain();
1125 decode.drain();
1126 rename.drain();
1127 iew.drain();
1128 commit.drain();
1129
1130 // Wake the CPU and record activity so everything can drain out if
1131 // the CPU was not able to immediately drain.
1132 if (getState() != SimObject::Drained) {
1133 // A bit of a hack...set the drainEvent after all the drain()
1134 // calls have been made, that way if all of the stages drain
1135 // immediately, the signalDrained() function knows not to call
1136 // process on the drain event.
1137 drainEvent = drain_event;
1138
1139 wakeCPU();
1140 activityRec.activity();
1141
1142 return 1;
1143 } else {
1144 return 0;
1145 }
1146}
1147
1148template <class Impl>
1149void
1150FullO3CPU<Impl>::resume()
1151{
1152 fetch.resume();
1153 decode.resume();
1154 rename.resume();
1155 iew.resume();
1156 commit.resume();
1157
1158 changeState(SimObject::Running);
1159
1160 if (_status == SwitchedOut || _status == Idle)
1161 return;
1162
1163 assert(system->getMemoryMode() == Enums::timing);
1164
1165 if (!tickEvent.scheduled())
1166 schedule(tickEvent, nextCycle());
1167 _status = Running;
1168}
1169
1170template <class Impl>
1171void
1172FullO3CPU<Impl>::signalDrained()
1173{
1174 if (++drainCount == NumStages) {
1175 if (tickEvent.scheduled())
1176 tickEvent.squash();
1177
1178 changeState(SimObject::Drained);
1179
1180 BaseCPU::switchOut();
1181
1182 if (drainEvent) {
1183 drainEvent->process();
1184 drainEvent = NULL;
1185 }
1186 }
1187 assert(drainCount <= 5);
1188}
1189
1190template <class Impl>
1191void
1192FullO3CPU<Impl>::switchOut()
1193{
1194 fetch.switchOut();
1195 rename.switchOut();
1196 iew.switchOut();
1197 commit.switchOut();
1198 instList.clear();
1199 while (!removeList.empty()) {
1200 removeList.pop();
1201 }
1202
1203 _status = SwitchedOut;
1204#if USE_CHECKER
1205 if (checker)
1206 checker->switchOut();
1207#endif
1208 if (tickEvent.scheduled())
1209 tickEvent.squash();
1210}
1211
1212template <class Impl>
1213void
1214FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
1215{
1216 // Flush out any old data from the time buffers.
1217 for (int i = 0; i < timeBuffer.getSize(); ++i) {
1218 timeBuffer.advance();
1219 fetchQueue.advance();
1220 decodeQueue.advance();
1221 renameQueue.advance();
1222 iewQueue.advance();
1223 }
1224
1225 activityRec.reset();
1226
1227 BaseCPU::takeOverFrom(oldCPU);
1228
1229 fetch.takeOverFrom();
1230 decode.takeOverFrom();
1231 rename.takeOverFrom();
1232 iew.takeOverFrom();
1233 commit.takeOverFrom();
1234
1235 assert(!tickEvent.scheduled() || tickEvent.squashed());
1236
1237 // @todo: Figure out how to properly select the tid to put onto
1238 // the active threads list.
1239 ThreadID tid = 0;
1240
1241 list<ThreadID>::iterator isActive =
1242 std::find(activeThreads.begin(), activeThreads.end(), tid);
1243
1244 if (isActive == activeThreads.end()) {
1245 //May Need to Re-code this if the delay variable is the delay
1246 //needed for thread to activate
1247 DPRINTF(O3CPU, "Adding Thread %i to active threads list\n",
1248 tid);
1249
1250 activeThreads.push_back(tid);
1251 }
1252
1253 // Set all statuses to active, schedule the CPU's tick event.
1254 // @todo: Fix up statuses so this is handled properly
1255 ThreadID size = threadContexts.size();
1256 for (ThreadID i = 0; i < size; ++i) {
1257 ThreadContext *tc = threadContexts[i];
1258 if (tc->status() == ThreadContext::Active && _status != Running) {
1259 _status = Running;
1260 reschedule(tickEvent, nextCycle(), true);
1261 }
1262 }
1263 if (!tickEvent.scheduled())
1264 schedule(tickEvent, nextCycle());
1265
1266 lastRunningCycle = curTick();
1267}
1268
1269template <class Impl>
1270TheISA::MiscReg
1271FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid)
1272{
1273 return this->isa[tid].readMiscRegNoEffect(misc_reg);
1274}
1275
1276template <class Impl>
1277TheISA::MiscReg
1278FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
1279{
1280 miscRegfileReads++;
1281 return this->isa[tid].readMiscReg(misc_reg, tcBase(tid));
1282}
1283
1284template <class Impl>
1285void
1286FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
1287 const TheISA::MiscReg &val, ThreadID tid)
1288{
1289 this->isa[tid].setMiscRegNoEffect(misc_reg, val);
1290}
1291
1292template <class Impl>
1293void
1294FullO3CPU<Impl>::setMiscReg(int misc_reg,
1295 const TheISA::MiscReg &val, ThreadID tid)
1296{
1297 miscRegfileWrites++;
1298 this->isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
1299}
1300
1301template <class Impl>
1302uint64_t
1303FullO3CPU<Impl>::readIntReg(int reg_idx)
1304{
1305 intRegfileReads++;
1306 return regFile.readIntReg(reg_idx);
1307}
1308
1309template <class Impl>
1310FloatReg
1311FullO3CPU<Impl>::readFloatReg(int reg_idx)
1312{
1313 fpRegfileReads++;
1314 return regFile.readFloatReg(reg_idx);
1315}
1316
1317template <class Impl>
1318FloatRegBits
1319FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
1320{
1321 fpRegfileReads++;
1322 return regFile.readFloatRegBits(reg_idx);
1323}
1324
1325template <class Impl>
1326void
1327FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
1328{
1329 intRegfileWrites++;
1330 regFile.setIntReg(reg_idx, val);
1331}
1332
1333template <class Impl>
1334void
1335FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
1336{
1337 fpRegfileWrites++;
1338 regFile.setFloatReg(reg_idx, val);
1339}
1340
1341template <class Impl>
1342void
1343FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
1344{
1345 fpRegfileWrites++;
1346 regFile.setFloatRegBits(reg_idx, val);
1347}
1348
1349template <class Impl>
1350uint64_t
1351FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1352{
1353 intRegfileReads++;
1354 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1355
1356 return regFile.readIntReg(phys_reg);
1357}
1358
1359template <class Impl>
1360float
1361FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
1362{
1363 fpRegfileReads++;
1364 int idx = reg_idx + TheISA::NumIntRegs;
1365 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1366
1367 return regFile.readFloatReg(phys_reg);
1368}
1369
1370template <class Impl>
1371uint64_t
1372FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid)
1373{
1374 fpRegfileReads++;
1375 int idx = reg_idx + TheISA::NumIntRegs;
1376 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1377
1378 return regFile.readFloatRegBits(phys_reg);
1379}
1380
1381template <class Impl>
1382void
1383FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
1384{
1385 intRegfileWrites++;
1386 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1387
1388 regFile.setIntReg(phys_reg, val);
1389}
1390
1391template <class Impl>
1392void
1393FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid)
1394{
1395 fpRegfileWrites++;
1396 int idx = reg_idx + TheISA::NumIntRegs;
1397 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1398
1399 regFile.setFloatReg(phys_reg, val);
1400}
1401
1402template <class Impl>
1403void
1404FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid)
1405{
1406 fpRegfileWrites++;
1407 int idx = reg_idx + TheISA::NumIntRegs;
1408 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1409
1410 regFile.setFloatRegBits(phys_reg, val);
1411}
1412
1413template <class Impl>
1414TheISA::PCState
1415FullO3CPU<Impl>::pcState(ThreadID tid)
1416{
1417 return commit.pcState(tid);
1418}
1419
1420template <class Impl>
1421void
1422FullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid)
1423{
1424 commit.pcState(val, tid);
1425}
1426
1427template <class Impl>
1428Addr
1429FullO3CPU<Impl>::instAddr(ThreadID tid)
1430{
1431 return commit.instAddr(tid);
1432}
1433
1434template <class Impl>
1435Addr
1436FullO3CPU<Impl>::nextInstAddr(ThreadID tid)
1437{
1438 return commit.nextInstAddr(tid);
1439}
1440
1441template <class Impl>
1442MicroPC
1443FullO3CPU<Impl>::microPC(ThreadID tid)
1444{
1445 return commit.microPC(tid);
1446}
1447
1448template <class Impl>
1449void
1450FullO3CPU<Impl>::squashFromTC(ThreadID tid)
1451{
1452 this->thread[tid]->inSyscall = true;
1453 this->commit.generateTCEvent(tid);
1454}
1455
1456template <class Impl>
1457typename FullO3CPU<Impl>::ListIt
1458FullO3CPU<Impl>::addInst(DynInstPtr &inst)
1459{
1460 instList.push_back(inst);
1461
1462 return --(instList.end());
1463}
1464
1465template <class Impl>
1466void
1467FullO3CPU<Impl>::instDone(ThreadID tid, DynInstPtr &inst)
1468{
1469 // Keep an instruction count.
1470 if (!inst->isMicroop() || inst->isLastMicroop()) {
1471 thread[tid]->numInst++;
1472 thread[tid]->numInsts++;
1473 committedInsts[tid]++;
1474 totalCommittedInsts++;
1475 }
1476 thread[tid]->numOp++;
1477 thread[tid]->numOps++;
1478 committedOps[tid]++;
1479
1480 system->totalNumInsts++;
1481 // Check for instruction-count-based events.
1482 comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1483 system->instEventQueue.serviceEvents(system->totalNumInsts);
1484}
1485
1486template <class Impl>
1487void
1488FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
1489{
1490 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s "
1491 "[sn:%lli]\n",
1492 inst->threadNumber, inst->pcState(), inst->seqNum);
1493
1494 removeInstsThisCycle = true;
1495
1496 // Remove the front instruction.
1497 removeList.push(inst->getInstListIt());
1498}
1499
1500template <class Impl>
1501void
1502FullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid)
1503{
1504 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1505 " list.\n", tid);
1506
1507 ListIt end_it;
1508
1509 bool rob_empty = false;
1510
1511 if (instList.empty()) {
1512 return;
1513 } else if (rob.isEmpty(/*tid*/)) {
1514 DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1515 end_it = instList.begin();
1516 rob_empty = true;
1517 } else {
1518 end_it = (rob.readTailInst(tid))->getInstListIt();
1519 DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1520 }
1521
1522 removeInstsThisCycle = true;
1523
1524 ListIt inst_it = instList.end();
1525
1526 inst_it--;
1527
1528 // Walk through the instruction list, removing any instructions
1529 // that were inserted after the given instruction iterator, end_it.
1530 while (inst_it != end_it) {
1531 assert(!instList.empty());
1532
1533 squashInstIt(inst_it, tid);
1534
1535 inst_it--;
1536 }
1537
1538 // If the ROB was empty, then we actually need to remove the first
1539 // instruction as well.
1540 if (rob_empty) {
1541 squashInstIt(inst_it, tid);
1542 }
1543}
1544
1545template <class Impl>
1546void
1547FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1548{
1549 assert(!instList.empty());
1550
1551 removeInstsThisCycle = true;
1552
1553 ListIt inst_iter = instList.end();
1554
1555 inst_iter--;
1556
1557 DPRINTF(O3CPU, "Deleting instructions from instruction "
1558 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1559 tid, seq_num, (*inst_iter)->seqNum);
1560
1561 while ((*inst_iter)->seqNum > seq_num) {
1562
1563 bool break_loop = (inst_iter == instList.begin());
1564
1565 squashInstIt(inst_iter, tid);
1566
1567 inst_iter--;
1568
1569 if (break_loop)
1570 break;
1571 }
1572}
1573
1574template <class Impl>
1575inline void
1576FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid)
1577{
1578 if ((*instIt)->threadNumber == tid) {
1579 DPRINTF(O3CPU, "Squashing instruction, "
1580 "[tid:%i] [sn:%lli] PC %s\n",
1581 (*instIt)->threadNumber,
1582 (*instIt)->seqNum,
1583 (*instIt)->pcState());
1584
1585 // Mark it as squashed.
1586 (*instIt)->setSquashed();
1587
1588 // @todo: Formulate a consistent method for deleting
1589 // instructions from the instruction list
1590 // Remove the instruction from the list.
1591 removeList.push(instIt);
1592 }
1593}
1594
1595template <class Impl>
1596void
1597FullO3CPU<Impl>::cleanUpRemovedInsts()
1598{
1599 while (!removeList.empty()) {
1600 DPRINTF(O3CPU, "Removing instruction, "
1601 "[tid:%i] [sn:%lli] PC %s\n",
1602 (*removeList.front())->threadNumber,
1603 (*removeList.front())->seqNum,
1604 (*removeList.front())->pcState());
1605
1606 instList.erase(removeList.front());
1607
1608 removeList.pop();
1609 }
1610
1611 removeInstsThisCycle = false;
1612}
1613/*
1614template <class Impl>
1615void
1616FullO3CPU<Impl>::removeAllInsts()
1617{
1618 instList.clear();
1619}
1620*/
1621template <class Impl>
1622void
1623FullO3CPU<Impl>::dumpInsts()
1624{
1625 int num = 0;
1626
1627 ListIt inst_list_it = instList.begin();
1628
1629 cprintf("Dumping Instruction List\n");
1630
1631 while (inst_list_it != instList.end()) {
1632 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1633 "Squashed:%i\n\n",
1634 num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber,
1635 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1636 (*inst_list_it)->isSquashed());
1637 inst_list_it++;
1638 ++num;
1639 }
1640}
1641/*
1642template <class Impl>
1643void
1644FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
1645{
1646 iew.wakeDependents(inst);
1647}
1648*/
1649template <class Impl>
1650void
1651FullO3CPU<Impl>::wakeCPU()
1652{
1653 if (activityRec.active() || tickEvent.scheduled()) {
1654 DPRINTF(Activity, "CPU already running.\n");
1655 return;
1656 }
1657
1658 DPRINTF(Activity, "Waking up CPU\n");
1659
1660 idleCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
1661 numCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
1662
1663 schedule(tickEvent, nextCycle());
1664}
1665
1666template <class Impl>
1667void
1668FullO3CPU<Impl>::wakeup()
1669{
1670 if (this->thread[0]->status() != ThreadContext::Suspended)
1671 return;
1672
1673 this->wakeCPU();
1674
1675 DPRINTF(Quiesce, "Suspended Processor woken\n");
1676 this->threadContexts[0]->activate();
1677}
1678
1679template <class Impl>
1680ThreadID
1681FullO3CPU<Impl>::getFreeTid()
1682{
1683 for (ThreadID tid = 0; tid < numThreads; tid++) {
1684 if (!tids[tid]) {
1685 tids[tid] = true;
1686 return tid;
1687 }
1688 }
1689
1690 return InvalidThreadID;
1691}
1692
1693template <class Impl>
1694void
1695FullO3CPU<Impl>::doContextSwitch()
1696{
1697 if (contextSwitch) {
1698
1699 //ADD CODE TO DEACTIVE THREAD HERE (???)
1700
1701 ThreadID size = cpuWaitList.size();
1702 for (ThreadID tid = 0; tid < size; tid++) {
1703 activateWhenReady(tid);
1704 }
1705
1706 if (cpuWaitList.size() == 0)
1707 contextSwitch = true;
1708 }
1709}
1710
1711template <class Impl>
1712void
1713FullO3CPU<Impl>::updateThreadPriority()
1714{
1715 if (activeThreads.size() > 1) {
1716 //DEFAULT TO ROUND ROBIN SCHEME
1717 //e.g. Move highest priority to end of thread list
1718 list<ThreadID>::iterator list_begin = activeThreads.begin();
1719
1720 unsigned high_thread = *list_begin;
1721
1722 activeThreads.erase(list_begin);
1723
1724 activeThreads.push_back(high_thread);
1725 }
1726}
1727
1728// Forward declaration of FullO3CPU.
1729template class FullO3CPU<O3CPUImpl>;