1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * Copyright (c) 2011 Regents of the University of California
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Kevin Lim
30 * Korey Sewell
31 * Rick Strong
32 */
33
| 1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * Copyright (c) 2011 Regents of the University of California
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Kevin Lim
30 * Korey Sewell
31 * Rick Strong
32 */
33
|
| 34#include "arch/kernel_stats.hh"
|
34#include "config/full_system.hh"
35#include "config/the_isa.hh"
36#include "config/use_checker.hh"
37#include "cpu/o3/cpu.hh"
38#include "cpu/o3/isa_specific.hh"
39#include "cpu/o3/thread_context.hh"
40#include "cpu/activity.hh"
| 35#include "config/full_system.hh"
36#include "config/the_isa.hh"
37#include "config/use_checker.hh"
38#include "cpu/o3/cpu.hh"
39#include "cpu/o3/isa_specific.hh"
40#include "cpu/o3/thread_context.hh"
41#include "cpu/activity.hh"
|
| 42#include "cpu/quiesce_event.hh"
|
41#include "cpu/simple_thread.hh"
42#include "cpu/thread_context.hh"
43#include "debug/Activity.hh"
44#include "debug/O3CPU.hh"
45#include "debug/Quiesce.hh"
46#include "enums/MemoryMode.hh"
47#include "sim/core.hh"
| 43#include "cpu/simple_thread.hh"
44#include "cpu/thread_context.hh"
45#include "debug/Activity.hh"
46#include "debug/O3CPU.hh"
47#include "debug/Quiesce.hh"
48#include "enums/MemoryMode.hh"
49#include "sim/core.hh"
|
| 50#include "sim/process.hh"
|
48#include "sim/stat_control.hh"
49#include "sim/system.hh"
50
| 51#include "sim/stat_control.hh"
52#include "sim/system.hh"
53
|
51#if FULL_SYSTEM
52#include "cpu/quiesce_event.hh"
53#else
54#include "sim/process.hh"
55#endif
56
| |
57#if USE_CHECKER
58#include "cpu/checker/cpu.hh"
59#endif
60
61#if THE_ISA == ALPHA_ISA
62#include "arch/alpha/osfpal.hh"
63#include "debug/Activity.hh"
64#endif
65
66class BaseCPUParams;
67
68using namespace TheISA;
69using namespace std;
70
71BaseO3CPU::BaseO3CPU(BaseCPUParams *params)
72 : BaseCPU(params)
73{
74}
75
76void
77BaseO3CPU::regStats()
78{
79 BaseCPU::regStats();
80}
81
82template <class Impl>
83FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
84 : Event(CPU_Tick_Pri), cpu(c)
85{
86}
87
88template <class Impl>
89void
90FullO3CPU<Impl>::TickEvent::process()
91{
92 cpu->tick();
93}
94
95template <class Impl>
96const char *
97FullO3CPU<Impl>::TickEvent::description() const
98{
99 return "FullO3CPU tick";
100}
101
102template <class Impl>
103FullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent()
104 : Event(CPU_Switch_Pri)
105{
106}
107
108template <class Impl>
109void
110FullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num,
111 FullO3CPU<Impl> *thread_cpu)
112{
113 tid = thread_num;
114 cpu = thread_cpu;
115}
116
117template <class Impl>
118void
119FullO3CPU<Impl>::ActivateThreadEvent::process()
120{
121 cpu->activateThread(tid);
122}
123
124template <class Impl>
125const char *
126FullO3CPU<Impl>::ActivateThreadEvent::description() const
127{
128 return "FullO3CPU \"Activate Thread\"";
129}
130
131template <class Impl>
132FullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent()
133 : Event(CPU_Tick_Pri), tid(0), remove(false), cpu(NULL)
134{
135}
136
137template <class Impl>
138void
139FullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num,
140 FullO3CPU<Impl> *thread_cpu)
141{
142 tid = thread_num;
143 cpu = thread_cpu;
144 remove = false;
145}
146
147template <class Impl>
148void
149FullO3CPU<Impl>::DeallocateContextEvent::process()
150{
151 cpu->deactivateThread(tid);
152 if (remove)
153 cpu->removeThread(tid);
154}
155
156template <class Impl>
157const char *
158FullO3CPU<Impl>::DeallocateContextEvent::description() const
159{
160 return "FullO3CPU \"Deallocate Context\"";
161}
162
163template <class Impl>
164FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
165 : BaseO3CPU(params),
166 itb(params->itb),
167 dtb(params->dtb),
168 tickEvent(this),
169#ifndef NDEBUG
170 instcount(0),
171#endif
172 removeInstsThisCycle(false),
173 fetch(this, params),
174 decode(this, params),
175 rename(this, params),
176 iew(this, params),
177 commit(this, params),
178
179 regFile(this, params->numPhysIntRegs,
180 params->numPhysFloatRegs),
181
182 freeList(params->numThreads,
183 TheISA::NumIntRegs, params->numPhysIntRegs,
184 TheISA::NumFloatRegs, params->numPhysFloatRegs),
185
186 rob(this,
187 params->numROBEntries, params->squashWidth,
188 params->smtROBPolicy, params->smtROBThreshold,
189 params->numThreads),
190
191 scoreboard(params->numThreads,
192 TheISA::NumIntRegs, params->numPhysIntRegs,
193 TheISA::NumFloatRegs, params->numPhysFloatRegs,
194 TheISA::NumMiscRegs * numThreads,
195 TheISA::ZeroReg),
196
197 timeBuffer(params->backComSize, params->forwardComSize),
198 fetchQueue(params->backComSize, params->forwardComSize),
199 decodeQueue(params->backComSize, params->forwardComSize),
200 renameQueue(params->backComSize, params->forwardComSize),
201 iewQueue(params->backComSize, params->forwardComSize),
202 activityRec(name(), NumStages,
203 params->backComSize + params->forwardComSize,
204 params->activity),
205
206 globalSeqNum(1),
207 system(params->system),
208 drainCount(0),
209 deferRegistration(params->defer_registration)
210{
211 if (!deferRegistration) {
212 _status = Running;
213 } else {
214 _status = Idle;
215 }
216
217#if USE_CHECKER
218 if (params->checker) {
219 BaseCPU *temp_checker = params->checker;
220 checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
221#if FULL_SYSTEM
222 checker->setSystem(params->system);
223#endif
224 } else {
225 checker = NULL;
226 }
227#endif // USE_CHECKER
228
229#if !FULL_SYSTEM
230 thread.resize(numThreads);
231 tids.resize(numThreads);
232#endif
233
234 // The stages also need their CPU pointer setup. However this
235 // must be done at the upper level CPU because they have pointers
236 // to the upper level CPU, and not this FullO3CPU.
237
238 // Set up Pointers to the activeThreads list for each stage
239 fetch.setActiveThreads(&activeThreads);
240 decode.setActiveThreads(&activeThreads);
241 rename.setActiveThreads(&activeThreads);
242 iew.setActiveThreads(&activeThreads);
243 commit.setActiveThreads(&activeThreads);
244
245 // Give each of the stages the time buffer they will use.
246 fetch.setTimeBuffer(&timeBuffer);
247 decode.setTimeBuffer(&timeBuffer);
248 rename.setTimeBuffer(&timeBuffer);
249 iew.setTimeBuffer(&timeBuffer);
250 commit.setTimeBuffer(&timeBuffer);
251
252 // Also setup each of the stages' queues.
253 fetch.setFetchQueue(&fetchQueue);
254 decode.setFetchQueue(&fetchQueue);
255 commit.setFetchQueue(&fetchQueue);
256 decode.setDecodeQueue(&decodeQueue);
257 rename.setDecodeQueue(&decodeQueue);
258 rename.setRenameQueue(&renameQueue);
259 iew.setRenameQueue(&renameQueue);
260 iew.setIEWQueue(&iewQueue);
261 commit.setIEWQueue(&iewQueue);
262 commit.setRenameQueue(&renameQueue);
263
264 commit.setIEWStage(&iew);
265 rename.setIEWStage(&iew);
266 rename.setCommitStage(&commit);
267
268#if !FULL_SYSTEM
269 ThreadID active_threads = params->workload.size();
270
271 if (active_threads > Impl::MaxThreads) {
272 panic("Workload Size too large. Increase the 'MaxThreads'"
273 "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or "
274 "edit your workload size.");
275 }
276#else
277 ThreadID active_threads = 1;
278#endif
279
280 //Make Sure That this a Valid Architeture
281 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs);
282 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
283
284 rename.setScoreboard(&scoreboard);
285 iew.setScoreboard(&scoreboard);
286
287 // Setup the rename map for whichever stages need it.
288 PhysRegIndex lreg_idx = 0;
289 PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs
290
291 for (ThreadID tid = 0; tid < numThreads; tid++) {
292 bool bindRegs = (tid <= active_threads - 1);
293
294 commitRenameMap[tid].init(TheISA::NumIntRegs,
295 params->numPhysIntRegs,
296 lreg_idx, //Index for Logical. Regs
297
298 TheISA::NumFloatRegs,
299 params->numPhysFloatRegs,
300 freg_idx, //Index for Float Regs
301
302 TheISA::NumMiscRegs,
303
304 TheISA::ZeroReg,
305 TheISA::ZeroReg,
306
307 tid,
308 false);
309
310 renameMap[tid].init(TheISA::NumIntRegs,
311 params->numPhysIntRegs,
312 lreg_idx, //Index for Logical. Regs
313
314 TheISA::NumFloatRegs,
315 params->numPhysFloatRegs,
316 freg_idx, //Index for Float Regs
317
318 TheISA::NumMiscRegs,
319
320 TheISA::ZeroReg,
321 TheISA::ZeroReg,
322
323 tid,
324 bindRegs);
325
326 activateThreadEvent[tid].init(tid, this);
327 deallocateContextEvent[tid].init(tid, this);
328 }
329
330 rename.setRenameMap(renameMap);
331 commit.setRenameMap(commitRenameMap);
332
333 // Give renameMap & rename stage access to the freeList;
334 for (ThreadID tid = 0; tid < numThreads; tid++)
335 renameMap[tid].setFreeList(&freeList);
336 rename.setFreeList(&freeList);
337
338 // Setup the ROB for whichever stages need it.
339 commit.setROB(&rob);
340
341 lastRunningCycle = curTick();
342
343 lastActivatedCycle = -1;
344#if 0
345 // Give renameMap & rename stage access to the freeList;
346 for (ThreadID tid = 0; tid < numThreads; tid++)
347 globalSeqNum[tid] = 1;
348#endif
349
350 contextSwitch = false;
351 DPRINTF(O3CPU, "Creating O3CPU object.\n");
352
353 // Setup any thread state.
354 this->thread.resize(this->numThreads);
355
356 for (ThreadID tid = 0; tid < this->numThreads; ++tid) {
357#if FULL_SYSTEM
358 // SMT is not supported in FS mode yet.
359 assert(this->numThreads == 1);
360 this->thread[tid] = new Thread(this, 0, NULL);
361#else
362 if (tid < params->workload.size()) {
363 DPRINTF(O3CPU, "Workload[%i] process is %#x",
364 tid, this->thread[tid]);
365 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
366 (typename Impl::O3CPU *)(this),
367 tid, params->workload[tid]);
368
369 //usedTids[tid] = true;
370 //threadMap[tid] = tid;
371 } else {
372 //Allocate Empty thread so M5 can use later
373 //when scheduling threads to CPU
374 Process* dummy_proc = NULL;
375
376 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
377 (typename Impl::O3CPU *)(this),
378 tid, dummy_proc);
379 //usedTids[tid] = false;
380 }
381#endif // !FULL_SYSTEM
382
383 ThreadContext *tc;
384
385 // Setup the TC that will serve as the interface to the threads/CPU.
386 O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>;
387
388 tc = o3_tc;
389
390 // If we're using a checker, then the TC should be the
391 // CheckerThreadContext.
392#if USE_CHECKER
393 if (params->checker) {
394 tc = new CheckerThreadContext<O3ThreadContext<Impl> >(
395 o3_tc, this->checker);
396 }
397#endif
398
399 o3_tc->cpu = (typename Impl::O3CPU *)(this);
400 assert(o3_tc->cpu);
401 o3_tc->thread = this->thread[tid];
402
403#if FULL_SYSTEM
404 // Setup quiesce event.
405 this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
406#endif
407 // Give the thread the TC.
408 this->thread[tid]->tc = tc;
409
410 // Add the TC to the CPU's list of TC's.
411 this->threadContexts.push_back(tc);
412 }
413
414 for (ThreadID tid = 0; tid < this->numThreads; tid++)
415 this->thread[tid]->setFuncExeInst(0);
416
417 lockAddr = 0;
418 lockFlag = false;
419}
420
421template <class Impl>
422FullO3CPU<Impl>::~FullO3CPU()
423{
424}
425
426template <class Impl>
427void
428FullO3CPU<Impl>::regStats()
429{
430 BaseO3CPU::regStats();
431
432 // Register any of the O3CPU's stats here.
433 timesIdled
434 .name(name() + ".timesIdled")
435 .desc("Number of times that the entire CPU went into an idle state and"
436 " unscheduled itself")
437 .prereq(timesIdled);
438
439 idleCycles
440 .name(name() + ".idleCycles")
441 .desc("Total number of cycles that the CPU has spent unscheduled due "
442 "to idling")
443 .prereq(idleCycles);
444
445 // Number of Instructions simulated
446 // --------------------------------
447 // Should probably be in Base CPU but need templated
448 // MaxThreads so put in here instead
449 committedInsts
450 .init(numThreads)
451 .name(name() + ".committedInsts")
452 .desc("Number of Instructions Simulated");
453
454 totalCommittedInsts
455 .name(name() + ".committedInsts_total")
456 .desc("Number of Instructions Simulated");
457
458 cpi
459 .name(name() + ".cpi")
460 .desc("CPI: Cycles Per Instruction")
461 .precision(6);
462 cpi = numCycles / committedInsts;
463
464 totalCpi
465 .name(name() + ".cpi_total")
466 .desc("CPI: Total CPI of All Threads")
467 .precision(6);
468 totalCpi = numCycles / totalCommittedInsts;
469
470 ipc
471 .name(name() + ".ipc")
472 .desc("IPC: Instructions Per Cycle")
473 .precision(6);
474 ipc = committedInsts / numCycles;
475
476 totalIpc
477 .name(name() + ".ipc_total")
478 .desc("IPC: Total IPC of All Threads")
479 .precision(6);
480 totalIpc = totalCommittedInsts / numCycles;
481
482 this->fetch.regStats();
483 this->decode.regStats();
484 this->rename.regStats();
485 this->iew.regStats();
486 this->commit.regStats();
487 this->rob.regStats();
488
489 intRegfileReads
490 .name(name() + ".int_regfile_reads")
491 .desc("number of integer regfile reads")
492 .prereq(intRegfileReads);
493
494 intRegfileWrites
495 .name(name() + ".int_regfile_writes")
496 .desc("number of integer regfile writes")
497 .prereq(intRegfileWrites);
498
499 fpRegfileReads
500 .name(name() + ".fp_regfile_reads")
501 .desc("number of floating regfile reads")
502 .prereq(fpRegfileReads);
503
504 fpRegfileWrites
505 .name(name() + ".fp_regfile_writes")
506 .desc("number of floating regfile writes")
507 .prereq(fpRegfileWrites);
508
509 miscRegfileReads
510 .name(name() + ".misc_regfile_reads")
511 .desc("number of misc regfile reads")
512 .prereq(miscRegfileReads);
513
514 miscRegfileWrites
515 .name(name() + ".misc_regfile_writes")
516 .desc("number of misc regfile writes")
517 .prereq(miscRegfileWrites);
518}
519
520template <class Impl>
521Port *
522FullO3CPU<Impl>::getPort(const std::string &if_name, int idx)
523{
524 if (if_name == "dcache_port")
525 return iew.getDcachePort();
526 else if (if_name == "icache_port")
527 return fetch.getIcachePort();
528 else
529 panic("No Such Port\n");
530}
531
532template <class Impl>
533void
534FullO3CPU<Impl>::tick()
535{
536 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
537
538 ++numCycles;
539
540// activity = false;
541
542 //Tick each of the stages
543 fetch.tick();
544
545 decode.tick();
546
547 rename.tick();
548
549 iew.tick();
550
551 commit.tick();
552
553#if !FULL_SYSTEM
554 doContextSwitch();
555#endif
556
557 // Now advance the time buffers
558 timeBuffer.advance();
559
560 fetchQueue.advance();
561 decodeQueue.advance();
562 renameQueue.advance();
563 iewQueue.advance();
564
565 activityRec.advance();
566
567 if (removeInstsThisCycle) {
568 cleanUpRemovedInsts();
569 }
570
571 if (!tickEvent.scheduled()) {
572 if (_status == SwitchedOut ||
573 getState() == SimObject::Drained) {
574 DPRINTF(O3CPU, "Switched out!\n");
575 // increment stat
576 lastRunningCycle = curTick();
577 } else if (!activityRec.active() || _status == Idle) {
578 DPRINTF(O3CPU, "Idle!\n");
579 lastRunningCycle = curTick();
580 timesIdled++;
581 } else {
582 schedule(tickEvent, nextCycle(curTick() + ticks(1)));
583 DPRINTF(O3CPU, "Scheduling next tick!\n");
584 }
585 }
586
587#if !FULL_SYSTEM
588 updateThreadPriority();
589#endif
590}
591
592template <class Impl>
593void
594FullO3CPU<Impl>::init()
595{
596 BaseCPU::init();
597
598 // Set inSyscall so that the CPU doesn't squash when initially
599 // setting up registers.
600 for (ThreadID tid = 0; tid < numThreads; ++tid)
601 thread[tid]->inSyscall = true;
602
603#if FULL_SYSTEM
604 for (ThreadID tid = 0; tid < numThreads; tid++) {
605 ThreadContext *src_tc = threadContexts[tid];
606 TheISA::initCPU(src_tc, src_tc->contextId());
607 }
608#endif
609
610 // Clear inSyscall.
611 for (int tid = 0; tid < numThreads; ++tid)
612 thread[tid]->inSyscall = false;
613
614 // Initialize stages.
615 fetch.initStage();
616 iew.initStage();
617 rename.initStage();
618 commit.initStage();
619
620 commit.setThreads(thread);
621}
622
623template <class Impl>
624void
625FullO3CPU<Impl>::activateThread(ThreadID tid)
626{
627 list<ThreadID>::iterator isActive =
628 std::find(activeThreads.begin(), activeThreads.end(), tid);
629
630 DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid);
631
632 if (isActive == activeThreads.end()) {
633 DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n",
634 tid);
635
636 activeThreads.push_back(tid);
637 }
638}
639
640template <class Impl>
641void
642FullO3CPU<Impl>::deactivateThread(ThreadID tid)
643{
644 //Remove From Active List, if Active
645 list<ThreadID>::iterator thread_it =
646 std::find(activeThreads.begin(), activeThreads.end(), tid);
647
648 DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid);
649
650 if (thread_it != activeThreads.end()) {
651 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
652 tid);
653 activeThreads.erase(thread_it);
654 }
655}
656
657template <class Impl>
658Counter
659FullO3CPU<Impl>::totalInstructions() const
660{
661 Counter total(0);
662
663 ThreadID size = thread.size();
664 for (ThreadID i = 0; i < size; i++)
665 total += thread[i]->numInst;
666
667 return total;
668}
669
670template <class Impl>
671void
672FullO3CPU<Impl>::activateContext(ThreadID tid, int delay)
673{
674 // Needs to set each stage to running as well.
675 if (delay){
676 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate "
677 "on cycle %d\n", tid, curTick() + ticks(delay));
678 scheduleActivateThreadEvent(tid, delay);
679 } else {
680 activateThread(tid);
681 }
682
683 if (lastActivatedCycle < curTick()) {
684 scheduleTickEvent(delay);
685
686 // Be sure to signal that there's some activity so the CPU doesn't
687 // deschedule itself.
688 activityRec.activity();
689 fetch.wakeFromQuiesce();
690
691 lastActivatedCycle = curTick();
692
693 _status = Running;
694 }
695}
696
697template <class Impl>
698bool
699FullO3CPU<Impl>::deallocateContext(ThreadID tid, bool remove, int delay)
700{
701 // Schedule removal of thread data from CPU
702 if (delay){
703 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate "
704 "on cycle %d\n", tid, curTick() + ticks(delay));
705 scheduleDeallocateContextEvent(tid, remove, delay);
706 return false;
707 } else {
708 deactivateThread(tid);
709 if (remove)
710 removeThread(tid);
711 return true;
712 }
713}
714
715template <class Impl>
716void
717FullO3CPU<Impl>::suspendContext(ThreadID tid)
718{
719 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
720 bool deallocated = deallocateContext(tid, false, 1);
721 // If this was the last thread then unschedule the tick event.
722 if ((activeThreads.size() == 1 && !deallocated) ||
723 activeThreads.size() == 0)
724 unscheduleTickEvent();
725 _status = Idle;
726}
727
728template <class Impl>
729void
730FullO3CPU<Impl>::haltContext(ThreadID tid)
731{
732 //For now, this is the same as deallocate
733 DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
734 deallocateContext(tid, true, 1);
735}
736
737template <class Impl>
738void
739FullO3CPU<Impl>::insertThread(ThreadID tid)
740{
741 DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
742 // Will change now that the PC and thread state is internal to the CPU
743 // and not in the ThreadContext.
744#if FULL_SYSTEM
745 ThreadContext *src_tc = system->threadContexts[tid];
746#else
747 ThreadContext *src_tc = tcBase(tid);
748#endif
749
750 //Bind Int Regs to Rename Map
751 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
752 PhysRegIndex phys_reg = freeList.getIntReg();
753
754 renameMap[tid].setEntry(ireg,phys_reg);
755 scoreboard.setReg(phys_reg);
756 }
757
758 //Bind Float Regs to Rename Map
759 for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
760 PhysRegIndex phys_reg = freeList.getFloatReg();
761
762 renameMap[tid].setEntry(freg,phys_reg);
763 scoreboard.setReg(phys_reg);
764 }
765
766 //Copy Thread Data Into RegFile
767 //this->copyFromTC(tid);
768
769 //Set PC/NPC/NNPC
770 pcState(src_tc->pcState(), tid);
771
772 src_tc->setStatus(ThreadContext::Active);
773
774 activateContext(tid,1);
775
776 //Reset ROB/IQ/LSQ Entries
777 commit.rob->resetEntries();
778 iew.resetEntries();
779}
780
781template <class Impl>
782void
783FullO3CPU<Impl>::removeThread(ThreadID tid)
784{
785 DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
786
787 // Copy Thread Data From RegFile
788 // If thread is suspended, it might be re-allocated
789 // this->copyToTC(tid);
790
791
792 // @todo: 2-27-2008: Fix how we free up rename mappings
793 // here to alleviate the case for double-freeing registers
794 // in SMT workloads.
795
796 // Unbind Int Regs from Rename Map
797 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
798 PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
799
800 scoreboard.unsetReg(phys_reg);
801 freeList.addReg(phys_reg);
802 }
803
804 // Unbind Float Regs from Rename Map
805 for (int freg = TheISA::NumIntRegs; freg < TheISA::NumFloatRegs; freg++) {
806 PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
807
808 scoreboard.unsetReg(phys_reg);
809 freeList.addReg(phys_reg);
810 }
811
812 // Squash Throughout Pipeline
813 DynInstPtr inst = commit.rob->readHeadInst(tid);
814 InstSeqNum squash_seq_num = inst->seqNum;
815 fetch.squash(0, squash_seq_num, inst, tid);
816 decode.squash(tid);
817 rename.squash(squash_seq_num, tid);
818 iew.squash(tid);
819 iew.ldstQueue.squash(squash_seq_num, tid);
820 commit.rob->squash(squash_seq_num, tid);
821
822
823 assert(iew.instQueue.getCount(tid) == 0);
824 assert(iew.ldstQueue.getCount(tid) == 0);
825
826 // Reset ROB/IQ/LSQ Entries
827
828 // Commented out for now. This should be possible to do by
829 // telling all the pipeline stages to drain first, and then
830 // checking until the drain completes. Once the pipeline is
831 // drained, call resetEntries(). - 10-09-06 ktlim
832/*
833 if (activeThreads.size() >= 1) {
834 commit.rob->resetEntries();
835 iew.resetEntries();
836 }
837*/
838}
839
840
841template <class Impl>
842void
843FullO3CPU<Impl>::activateWhenReady(ThreadID tid)
844{
845 DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming"
846 "(e.g. PhysRegs/ROB/IQ/LSQ) \n",
847 tid);
848
849 bool ready = true;
850
851 if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) {
852 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
853 "Phys. Int. Regs.\n",
854 tid);
855 ready = false;
856 } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) {
857 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
858 "Phys. Float. Regs.\n",
859 tid);
860 ready = false;
861 } else if (commit.rob->numFreeEntries() >=
862 commit.rob->entryAmount(activeThreads.size() + 1)) {
863 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
864 "ROB entries.\n",
865 tid);
866 ready = false;
867 } else if (iew.instQueue.numFreeEntries() >=
868 iew.instQueue.entryAmount(activeThreads.size() + 1)) {
869 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
870 "IQ entries.\n",
871 tid);
872 ready = false;
873 } else if (iew.ldstQueue.numFreeEntries() >=
874 iew.ldstQueue.entryAmount(activeThreads.size() + 1)) {
875 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
876 "LSQ entries.\n",
877 tid);
878 ready = false;
879 }
880
881 if (ready) {
882 insertThread(tid);
883
884 contextSwitch = false;
885
886 cpuWaitList.remove(tid);
887 } else {
888 suspendContext(tid);
889
890 //blocks fetch
891 contextSwitch = true;
892
893 //@todo: dont always add to waitlist
894 //do waitlist
895 cpuWaitList.push_back(tid);
896 }
897}
898
| 54#if USE_CHECKER
55#include "cpu/checker/cpu.hh"
56#endif
57
58#if THE_ISA == ALPHA_ISA
59#include "arch/alpha/osfpal.hh"
60#include "debug/Activity.hh"
61#endif
62
63class BaseCPUParams;
64
65using namespace TheISA;
66using namespace std;
67
68BaseO3CPU::BaseO3CPU(BaseCPUParams *params)
69 : BaseCPU(params)
70{
71}
72
73void
74BaseO3CPU::regStats()
75{
76 BaseCPU::regStats();
77}
78
79template <class Impl>
80FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
81 : Event(CPU_Tick_Pri), cpu(c)
82{
83}
84
85template <class Impl>
86void
87FullO3CPU<Impl>::TickEvent::process()
88{
89 cpu->tick();
90}
91
92template <class Impl>
93const char *
94FullO3CPU<Impl>::TickEvent::description() const
95{
96 return "FullO3CPU tick";
97}
98
99template <class Impl>
100FullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent()
101 : Event(CPU_Switch_Pri)
102{
103}
104
105template <class Impl>
106void
107FullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num,
108 FullO3CPU<Impl> *thread_cpu)
109{
110 tid = thread_num;
111 cpu = thread_cpu;
112}
113
114template <class Impl>
115void
116FullO3CPU<Impl>::ActivateThreadEvent::process()
117{
118 cpu->activateThread(tid);
119}
120
121template <class Impl>
122const char *
123FullO3CPU<Impl>::ActivateThreadEvent::description() const
124{
125 return "FullO3CPU \"Activate Thread\"";
126}
127
128template <class Impl>
129FullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent()
130 : Event(CPU_Tick_Pri), tid(0), remove(false), cpu(NULL)
131{
132}
133
134template <class Impl>
135void
136FullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num,
137 FullO3CPU<Impl> *thread_cpu)
138{
139 tid = thread_num;
140 cpu = thread_cpu;
141 remove = false;
142}
143
144template <class Impl>
145void
146FullO3CPU<Impl>::DeallocateContextEvent::process()
147{
148 cpu->deactivateThread(tid);
149 if (remove)
150 cpu->removeThread(tid);
151}
152
153template <class Impl>
154const char *
155FullO3CPU<Impl>::DeallocateContextEvent::description() const
156{
157 return "FullO3CPU \"Deallocate Context\"";
158}
159
160template <class Impl>
161FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
162 : BaseO3CPU(params),
163 itb(params->itb),
164 dtb(params->dtb),
165 tickEvent(this),
166#ifndef NDEBUG
167 instcount(0),
168#endif
169 removeInstsThisCycle(false),
170 fetch(this, params),
171 decode(this, params),
172 rename(this, params),
173 iew(this, params),
174 commit(this, params),
175
176 regFile(this, params->numPhysIntRegs,
177 params->numPhysFloatRegs),
178
179 freeList(params->numThreads,
180 TheISA::NumIntRegs, params->numPhysIntRegs,
181 TheISA::NumFloatRegs, params->numPhysFloatRegs),
182
183 rob(this,
184 params->numROBEntries, params->squashWidth,
185 params->smtROBPolicy, params->smtROBThreshold,
186 params->numThreads),
187
188 scoreboard(params->numThreads,
189 TheISA::NumIntRegs, params->numPhysIntRegs,
190 TheISA::NumFloatRegs, params->numPhysFloatRegs,
191 TheISA::NumMiscRegs * numThreads,
192 TheISA::ZeroReg),
193
194 timeBuffer(params->backComSize, params->forwardComSize),
195 fetchQueue(params->backComSize, params->forwardComSize),
196 decodeQueue(params->backComSize, params->forwardComSize),
197 renameQueue(params->backComSize, params->forwardComSize),
198 iewQueue(params->backComSize, params->forwardComSize),
199 activityRec(name(), NumStages,
200 params->backComSize + params->forwardComSize,
201 params->activity),
202
203 globalSeqNum(1),
204 system(params->system),
205 drainCount(0),
206 deferRegistration(params->defer_registration)
207{
208 if (!deferRegistration) {
209 _status = Running;
210 } else {
211 _status = Idle;
212 }
213
214#if USE_CHECKER
215 if (params->checker) {
216 BaseCPU *temp_checker = params->checker;
217 checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
218#if FULL_SYSTEM
219 checker->setSystem(params->system);
220#endif
221 } else {
222 checker = NULL;
223 }
224#endif // USE_CHECKER
225
226#if !FULL_SYSTEM
227 thread.resize(numThreads);
228 tids.resize(numThreads);
229#endif
230
231 // The stages also need their CPU pointer setup. However this
232 // must be done at the upper level CPU because they have pointers
233 // to the upper level CPU, and not this FullO3CPU.
234
235 // Set up Pointers to the activeThreads list for each stage
236 fetch.setActiveThreads(&activeThreads);
237 decode.setActiveThreads(&activeThreads);
238 rename.setActiveThreads(&activeThreads);
239 iew.setActiveThreads(&activeThreads);
240 commit.setActiveThreads(&activeThreads);
241
242 // Give each of the stages the time buffer they will use.
243 fetch.setTimeBuffer(&timeBuffer);
244 decode.setTimeBuffer(&timeBuffer);
245 rename.setTimeBuffer(&timeBuffer);
246 iew.setTimeBuffer(&timeBuffer);
247 commit.setTimeBuffer(&timeBuffer);
248
249 // Also setup each of the stages' queues.
250 fetch.setFetchQueue(&fetchQueue);
251 decode.setFetchQueue(&fetchQueue);
252 commit.setFetchQueue(&fetchQueue);
253 decode.setDecodeQueue(&decodeQueue);
254 rename.setDecodeQueue(&decodeQueue);
255 rename.setRenameQueue(&renameQueue);
256 iew.setRenameQueue(&renameQueue);
257 iew.setIEWQueue(&iewQueue);
258 commit.setIEWQueue(&iewQueue);
259 commit.setRenameQueue(&renameQueue);
260
261 commit.setIEWStage(&iew);
262 rename.setIEWStage(&iew);
263 rename.setCommitStage(&commit);
264
265#if !FULL_SYSTEM
266 ThreadID active_threads = params->workload.size();
267
268 if (active_threads > Impl::MaxThreads) {
269 panic("Workload Size too large. Increase the 'MaxThreads'"
270 "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or "
271 "edit your workload size.");
272 }
273#else
274 ThreadID active_threads = 1;
275#endif
276
277 //Make Sure That this a Valid Architeture
278 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs);
279 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
280
281 rename.setScoreboard(&scoreboard);
282 iew.setScoreboard(&scoreboard);
283
284 // Setup the rename map for whichever stages need it.
285 PhysRegIndex lreg_idx = 0;
286 PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs
287
288 for (ThreadID tid = 0; tid < numThreads; tid++) {
289 bool bindRegs = (tid <= active_threads - 1);
290
291 commitRenameMap[tid].init(TheISA::NumIntRegs,
292 params->numPhysIntRegs,
293 lreg_idx, //Index for Logical. Regs
294
295 TheISA::NumFloatRegs,
296 params->numPhysFloatRegs,
297 freg_idx, //Index for Float Regs
298
299 TheISA::NumMiscRegs,
300
301 TheISA::ZeroReg,
302 TheISA::ZeroReg,
303
304 tid,
305 false);
306
307 renameMap[tid].init(TheISA::NumIntRegs,
308 params->numPhysIntRegs,
309 lreg_idx, //Index for Logical. Regs
310
311 TheISA::NumFloatRegs,
312 params->numPhysFloatRegs,
313 freg_idx, //Index for Float Regs
314
315 TheISA::NumMiscRegs,
316
317 TheISA::ZeroReg,
318 TheISA::ZeroReg,
319
320 tid,
321 bindRegs);
322
323 activateThreadEvent[tid].init(tid, this);
324 deallocateContextEvent[tid].init(tid, this);
325 }
326
327 rename.setRenameMap(renameMap);
328 commit.setRenameMap(commitRenameMap);
329
330 // Give renameMap & rename stage access to the freeList;
331 for (ThreadID tid = 0; tid < numThreads; tid++)
332 renameMap[tid].setFreeList(&freeList);
333 rename.setFreeList(&freeList);
334
335 // Setup the ROB for whichever stages need it.
336 commit.setROB(&rob);
337
338 lastRunningCycle = curTick();
339
340 lastActivatedCycle = -1;
341#if 0
342 // Give renameMap & rename stage access to the freeList;
343 for (ThreadID tid = 0; tid < numThreads; tid++)
344 globalSeqNum[tid] = 1;
345#endif
346
347 contextSwitch = false;
348 DPRINTF(O3CPU, "Creating O3CPU object.\n");
349
350 // Setup any thread state.
351 this->thread.resize(this->numThreads);
352
353 for (ThreadID tid = 0; tid < this->numThreads; ++tid) {
354#if FULL_SYSTEM
355 // SMT is not supported in FS mode yet.
356 assert(this->numThreads == 1);
357 this->thread[tid] = new Thread(this, 0, NULL);
358#else
359 if (tid < params->workload.size()) {
360 DPRINTF(O3CPU, "Workload[%i] process is %#x",
361 tid, this->thread[tid]);
362 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
363 (typename Impl::O3CPU *)(this),
364 tid, params->workload[tid]);
365
366 //usedTids[tid] = true;
367 //threadMap[tid] = tid;
368 } else {
369 //Allocate Empty thread so M5 can use later
370 //when scheduling threads to CPU
371 Process* dummy_proc = NULL;
372
373 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
374 (typename Impl::O3CPU *)(this),
375 tid, dummy_proc);
376 //usedTids[tid] = false;
377 }
378#endif // !FULL_SYSTEM
379
380 ThreadContext *tc;
381
382 // Setup the TC that will serve as the interface to the threads/CPU.
383 O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>;
384
385 tc = o3_tc;
386
387 // If we're using a checker, then the TC should be the
388 // CheckerThreadContext.
389#if USE_CHECKER
390 if (params->checker) {
391 tc = new CheckerThreadContext<O3ThreadContext<Impl> >(
392 o3_tc, this->checker);
393 }
394#endif
395
396 o3_tc->cpu = (typename Impl::O3CPU *)(this);
397 assert(o3_tc->cpu);
398 o3_tc->thread = this->thread[tid];
399
400#if FULL_SYSTEM
401 // Setup quiesce event.
402 this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
403#endif
404 // Give the thread the TC.
405 this->thread[tid]->tc = tc;
406
407 // Add the TC to the CPU's list of TC's.
408 this->threadContexts.push_back(tc);
409 }
410
411 for (ThreadID tid = 0; tid < this->numThreads; tid++)
412 this->thread[tid]->setFuncExeInst(0);
413
414 lockAddr = 0;
415 lockFlag = false;
416}
417
418template <class Impl>
419FullO3CPU<Impl>::~FullO3CPU()
420{
421}
422
423template <class Impl>
424void
425FullO3CPU<Impl>::regStats()
426{
427 BaseO3CPU::regStats();
428
429 // Register any of the O3CPU's stats here.
430 timesIdled
431 .name(name() + ".timesIdled")
432 .desc("Number of times that the entire CPU went into an idle state and"
433 " unscheduled itself")
434 .prereq(timesIdled);
435
436 idleCycles
437 .name(name() + ".idleCycles")
438 .desc("Total number of cycles that the CPU has spent unscheduled due "
439 "to idling")
440 .prereq(idleCycles);
441
442 // Number of Instructions simulated
443 // --------------------------------
444 // Should probably be in Base CPU but need templated
445 // MaxThreads so put in here instead
446 committedInsts
447 .init(numThreads)
448 .name(name() + ".committedInsts")
449 .desc("Number of Instructions Simulated");
450
451 totalCommittedInsts
452 .name(name() + ".committedInsts_total")
453 .desc("Number of Instructions Simulated");
454
455 cpi
456 .name(name() + ".cpi")
457 .desc("CPI: Cycles Per Instruction")
458 .precision(6);
459 cpi = numCycles / committedInsts;
460
461 totalCpi
462 .name(name() + ".cpi_total")
463 .desc("CPI: Total CPI of All Threads")
464 .precision(6);
465 totalCpi = numCycles / totalCommittedInsts;
466
467 ipc
468 .name(name() + ".ipc")
469 .desc("IPC: Instructions Per Cycle")
470 .precision(6);
471 ipc = committedInsts / numCycles;
472
473 totalIpc
474 .name(name() + ".ipc_total")
475 .desc("IPC: Total IPC of All Threads")
476 .precision(6);
477 totalIpc = totalCommittedInsts / numCycles;
478
479 this->fetch.regStats();
480 this->decode.regStats();
481 this->rename.regStats();
482 this->iew.regStats();
483 this->commit.regStats();
484 this->rob.regStats();
485
486 intRegfileReads
487 .name(name() + ".int_regfile_reads")
488 .desc("number of integer regfile reads")
489 .prereq(intRegfileReads);
490
491 intRegfileWrites
492 .name(name() + ".int_regfile_writes")
493 .desc("number of integer regfile writes")
494 .prereq(intRegfileWrites);
495
496 fpRegfileReads
497 .name(name() + ".fp_regfile_reads")
498 .desc("number of floating regfile reads")
499 .prereq(fpRegfileReads);
500
501 fpRegfileWrites
502 .name(name() + ".fp_regfile_writes")
503 .desc("number of floating regfile writes")
504 .prereq(fpRegfileWrites);
505
506 miscRegfileReads
507 .name(name() + ".misc_regfile_reads")
508 .desc("number of misc regfile reads")
509 .prereq(miscRegfileReads);
510
511 miscRegfileWrites
512 .name(name() + ".misc_regfile_writes")
513 .desc("number of misc regfile writes")
514 .prereq(miscRegfileWrites);
515}
516
517template <class Impl>
518Port *
519FullO3CPU<Impl>::getPort(const std::string &if_name, int idx)
520{
521 if (if_name == "dcache_port")
522 return iew.getDcachePort();
523 else if (if_name == "icache_port")
524 return fetch.getIcachePort();
525 else
526 panic("No Such Port\n");
527}
528
529template <class Impl>
530void
531FullO3CPU<Impl>::tick()
532{
533 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
534
535 ++numCycles;
536
537// activity = false;
538
539 //Tick each of the stages
540 fetch.tick();
541
542 decode.tick();
543
544 rename.tick();
545
546 iew.tick();
547
548 commit.tick();
549
550#if !FULL_SYSTEM
551 doContextSwitch();
552#endif
553
554 // Now advance the time buffers
555 timeBuffer.advance();
556
557 fetchQueue.advance();
558 decodeQueue.advance();
559 renameQueue.advance();
560 iewQueue.advance();
561
562 activityRec.advance();
563
564 if (removeInstsThisCycle) {
565 cleanUpRemovedInsts();
566 }
567
568 if (!tickEvent.scheduled()) {
569 if (_status == SwitchedOut ||
570 getState() == SimObject::Drained) {
571 DPRINTF(O3CPU, "Switched out!\n");
572 // increment stat
573 lastRunningCycle = curTick();
574 } else if (!activityRec.active() || _status == Idle) {
575 DPRINTF(O3CPU, "Idle!\n");
576 lastRunningCycle = curTick();
577 timesIdled++;
578 } else {
579 schedule(tickEvent, nextCycle(curTick() + ticks(1)));
580 DPRINTF(O3CPU, "Scheduling next tick!\n");
581 }
582 }
583
584#if !FULL_SYSTEM
585 updateThreadPriority();
586#endif
587}
588
589template <class Impl>
590void
591FullO3CPU<Impl>::init()
592{
593 BaseCPU::init();
594
595 // Set inSyscall so that the CPU doesn't squash when initially
596 // setting up registers.
597 for (ThreadID tid = 0; tid < numThreads; ++tid)
598 thread[tid]->inSyscall = true;
599
600#if FULL_SYSTEM
601 for (ThreadID tid = 0; tid < numThreads; tid++) {
602 ThreadContext *src_tc = threadContexts[tid];
603 TheISA::initCPU(src_tc, src_tc->contextId());
604 }
605#endif
606
607 // Clear inSyscall.
608 for (int tid = 0; tid < numThreads; ++tid)
609 thread[tid]->inSyscall = false;
610
611 // Initialize stages.
612 fetch.initStage();
613 iew.initStage();
614 rename.initStage();
615 commit.initStage();
616
617 commit.setThreads(thread);
618}
619
620template <class Impl>
621void
622FullO3CPU<Impl>::activateThread(ThreadID tid)
623{
624 list<ThreadID>::iterator isActive =
625 std::find(activeThreads.begin(), activeThreads.end(), tid);
626
627 DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid);
628
629 if (isActive == activeThreads.end()) {
630 DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n",
631 tid);
632
633 activeThreads.push_back(tid);
634 }
635}
636
637template <class Impl>
638void
639FullO3CPU<Impl>::deactivateThread(ThreadID tid)
640{
641 //Remove From Active List, if Active
642 list<ThreadID>::iterator thread_it =
643 std::find(activeThreads.begin(), activeThreads.end(), tid);
644
645 DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid);
646
647 if (thread_it != activeThreads.end()) {
648 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
649 tid);
650 activeThreads.erase(thread_it);
651 }
652}
653
654template <class Impl>
655Counter
656FullO3CPU<Impl>::totalInstructions() const
657{
658 Counter total(0);
659
660 ThreadID size = thread.size();
661 for (ThreadID i = 0; i < size; i++)
662 total += thread[i]->numInst;
663
664 return total;
665}
666
667template <class Impl>
668void
669FullO3CPU<Impl>::activateContext(ThreadID tid, int delay)
670{
671 // Needs to set each stage to running as well.
672 if (delay){
673 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate "
674 "on cycle %d\n", tid, curTick() + ticks(delay));
675 scheduleActivateThreadEvent(tid, delay);
676 } else {
677 activateThread(tid);
678 }
679
680 if (lastActivatedCycle < curTick()) {
681 scheduleTickEvent(delay);
682
683 // Be sure to signal that there's some activity so the CPU doesn't
684 // deschedule itself.
685 activityRec.activity();
686 fetch.wakeFromQuiesce();
687
688 lastActivatedCycle = curTick();
689
690 _status = Running;
691 }
692}
693
694template <class Impl>
695bool
696FullO3CPU<Impl>::deallocateContext(ThreadID tid, bool remove, int delay)
697{
698 // Schedule removal of thread data from CPU
699 if (delay){
700 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate "
701 "on cycle %d\n", tid, curTick() + ticks(delay));
702 scheduleDeallocateContextEvent(tid, remove, delay);
703 return false;
704 } else {
705 deactivateThread(tid);
706 if (remove)
707 removeThread(tid);
708 return true;
709 }
710}
711
712template <class Impl>
713void
714FullO3CPU<Impl>::suspendContext(ThreadID tid)
715{
716 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
717 bool deallocated = deallocateContext(tid, false, 1);
718 // If this was the last thread then unschedule the tick event.
719 if ((activeThreads.size() == 1 && !deallocated) ||
720 activeThreads.size() == 0)
721 unscheduleTickEvent();
722 _status = Idle;
723}
724
725template <class Impl>
726void
727FullO3CPU<Impl>::haltContext(ThreadID tid)
728{
729 //For now, this is the same as deallocate
730 DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
731 deallocateContext(tid, true, 1);
732}
733
734template <class Impl>
735void
736FullO3CPU<Impl>::insertThread(ThreadID tid)
737{
738 DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
739 // Will change now that the PC and thread state is internal to the CPU
740 // and not in the ThreadContext.
741#if FULL_SYSTEM
742 ThreadContext *src_tc = system->threadContexts[tid];
743#else
744 ThreadContext *src_tc = tcBase(tid);
745#endif
746
747 //Bind Int Regs to Rename Map
748 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
749 PhysRegIndex phys_reg = freeList.getIntReg();
750
751 renameMap[tid].setEntry(ireg,phys_reg);
752 scoreboard.setReg(phys_reg);
753 }
754
755 //Bind Float Regs to Rename Map
756 for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
757 PhysRegIndex phys_reg = freeList.getFloatReg();
758
759 renameMap[tid].setEntry(freg,phys_reg);
760 scoreboard.setReg(phys_reg);
761 }
762
763 //Copy Thread Data Into RegFile
764 //this->copyFromTC(tid);
765
766 //Set PC/NPC/NNPC
767 pcState(src_tc->pcState(), tid);
768
769 src_tc->setStatus(ThreadContext::Active);
770
771 activateContext(tid,1);
772
773 //Reset ROB/IQ/LSQ Entries
774 commit.rob->resetEntries();
775 iew.resetEntries();
776}
777
778template <class Impl>
779void
780FullO3CPU<Impl>::removeThread(ThreadID tid)
781{
782 DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
783
784 // Copy Thread Data From RegFile
785 // If thread is suspended, it might be re-allocated
786 // this->copyToTC(tid);
787
788
789 // @todo: 2-27-2008: Fix how we free up rename mappings
790 // here to alleviate the case for double-freeing registers
791 // in SMT workloads.
792
793 // Unbind Int Regs from Rename Map
794 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
795 PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
796
797 scoreboard.unsetReg(phys_reg);
798 freeList.addReg(phys_reg);
799 }
800
801 // Unbind Float Regs from Rename Map
802 for (int freg = TheISA::NumIntRegs; freg < TheISA::NumFloatRegs; freg++) {
803 PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
804
805 scoreboard.unsetReg(phys_reg);
806 freeList.addReg(phys_reg);
807 }
808
809 // Squash Throughout Pipeline
810 DynInstPtr inst = commit.rob->readHeadInst(tid);
811 InstSeqNum squash_seq_num = inst->seqNum;
812 fetch.squash(0, squash_seq_num, inst, tid);
813 decode.squash(tid);
814 rename.squash(squash_seq_num, tid);
815 iew.squash(tid);
816 iew.ldstQueue.squash(squash_seq_num, tid);
817 commit.rob->squash(squash_seq_num, tid);
818
819
820 assert(iew.instQueue.getCount(tid) == 0);
821 assert(iew.ldstQueue.getCount(tid) == 0);
822
823 // Reset ROB/IQ/LSQ Entries
824
825 // Commented out for now. This should be possible to do by
826 // telling all the pipeline stages to drain first, and then
827 // checking until the drain completes. Once the pipeline is
828 // drained, call resetEntries(). - 10-09-06 ktlim
829/*
830 if (activeThreads.size() >= 1) {
831 commit.rob->resetEntries();
832 iew.resetEntries();
833 }
834*/
835}
836
837
838template <class Impl>
839void
840FullO3CPU<Impl>::activateWhenReady(ThreadID tid)
841{
842 DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming"
843 "(e.g. PhysRegs/ROB/IQ/LSQ) \n",
844 tid);
845
846 bool ready = true;
847
848 if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) {
849 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
850 "Phys. Int. Regs.\n",
851 tid);
852 ready = false;
853 } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) {
854 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
855 "Phys. Float. Regs.\n",
856 tid);
857 ready = false;
858 } else if (commit.rob->numFreeEntries() >=
859 commit.rob->entryAmount(activeThreads.size() + 1)) {
860 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
861 "ROB entries.\n",
862 tid);
863 ready = false;
864 } else if (iew.instQueue.numFreeEntries() >=
865 iew.instQueue.entryAmount(activeThreads.size() + 1)) {
866 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
867 "IQ entries.\n",
868 tid);
869 ready = false;
870 } else if (iew.ldstQueue.numFreeEntries() >=
871 iew.ldstQueue.entryAmount(activeThreads.size() + 1)) {
872 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
873 "LSQ entries.\n",
874 tid);
875 ready = false;
876 }
877
878 if (ready) {
879 insertThread(tid);
880
881 contextSwitch = false;
882
883 cpuWaitList.remove(tid);
884 } else {
885 suspendContext(tid);
886
887 //blocks fetch
888 contextSwitch = true;
889
890 //@todo: dont always add to waitlist
891 //do waitlist
892 cpuWaitList.push_back(tid);
893 }
894}
895
|
899#if FULL_SYSTEM
| |
900template <class Impl>
901Fault
902FullO3CPU<Impl>::hwrei(ThreadID tid)
903{
904#if THE_ISA == ALPHA_ISA
905 // Need to clear the lock flag upon returning from an interrupt.
906 this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
907
908 this->thread[tid]->kernelStats->hwrei();
909
910 // FIXME: XXX check for interrupts? XXX
911#endif
912 return NoFault;
913}
914
915template <class Impl>
916bool
917FullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid)
918{
919#if THE_ISA == ALPHA_ISA
920 if (this->thread[tid]->kernelStats)
921 this->thread[tid]->kernelStats->callpal(palFunc,
922 this->threadContexts[tid]);
923
924 switch (palFunc) {
925 case PAL::halt:
926 halt();
927 if (--System::numSystemsRunning == 0)
928 exitSimLoop("all cpus halted");
929 break;
930
931 case PAL::bpt:
932 case PAL::bugchk:
933 if (this->system->breakpoint())
934 return false;
935 break;
936 }
937#endif
938 return true;
939}
940
941template <class Impl>
942Fault
943FullO3CPU<Impl>::getInterrupts()
944{
945 // Check if there are any outstanding interrupts
946 return this->interrupts->getInterrupt(this->threadContexts[0]);
947}
948
949template <class Impl>
950void
951FullO3CPU<Impl>::processInterrupts(Fault interrupt)
952{
953 // Check for interrupts here. For now can copy the code that
954 // exists within isa_fullsys_traits.hh. Also assume that thread 0
955 // is the one that handles the interrupts.
956 // @todo: Possibly consolidate the interrupt checking code.
957 // @todo: Allow other threads to handle interrupts.
958
959 assert(interrupt != NoFault);
960 this->interrupts->updateIntrInfo(this->threadContexts[0]);
961
962 DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
963 this->trap(interrupt, 0, NULL);
964}
965
966template <class Impl>
967void
968FullO3CPU<Impl>::updateMemPorts()
969{
970 // Update all ThreadContext's memory ports (Functional/Virtual
971 // Ports)
972 ThreadID size = thread.size();
973 for (ThreadID i = 0; i < size; ++i)
974 thread[i]->connectMemPorts(thread[i]->getTC());
975}
| 896template <class Impl>
897Fault
898FullO3CPU<Impl>::hwrei(ThreadID tid)
899{
900#if THE_ISA == ALPHA_ISA
901 // Need to clear the lock flag upon returning from an interrupt.
902 this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
903
904 this->thread[tid]->kernelStats->hwrei();
905
906 // FIXME: XXX check for interrupts? XXX
907#endif
908 return NoFault;
909}
910
911template <class Impl>
912bool
913FullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid)
914{
915#if THE_ISA == ALPHA_ISA
916 if (this->thread[tid]->kernelStats)
917 this->thread[tid]->kernelStats->callpal(palFunc,
918 this->threadContexts[tid]);
919
920 switch (palFunc) {
921 case PAL::halt:
922 halt();
923 if (--System::numSystemsRunning == 0)
924 exitSimLoop("all cpus halted");
925 break;
926
927 case PAL::bpt:
928 case PAL::bugchk:
929 if (this->system->breakpoint())
930 return false;
931 break;
932 }
933#endif
934 return true;
935}
936
937template <class Impl>
938Fault
939FullO3CPU<Impl>::getInterrupts()
940{
941 // Check if there are any outstanding interrupts
942 return this->interrupts->getInterrupt(this->threadContexts[0]);
943}
944
945template <class Impl>
946void
947FullO3CPU<Impl>::processInterrupts(Fault interrupt)
948{
949 // Check for interrupts here. For now can copy the code that
950 // exists within isa_fullsys_traits.hh. Also assume that thread 0
951 // is the one that handles the interrupts.
952 // @todo: Possibly consolidate the interrupt checking code.
953 // @todo: Allow other threads to handle interrupts.
954
955 assert(interrupt != NoFault);
956 this->interrupts->updateIntrInfo(this->threadContexts[0]);
957
958 DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
959 this->trap(interrupt, 0, NULL);
960}
961
962template <class Impl>
963void
964FullO3CPU<Impl>::updateMemPorts()
965{
966 // Update all ThreadContext's memory ports (Functional/Virtual
967 // Ports)
968 ThreadID size = thread.size();
969 for (ThreadID i = 0; i < size; ++i)
970 thread[i]->connectMemPorts(thread[i]->getTC());
971}
|
976#endif
| |
977
978template <class Impl>
979void
980FullO3CPU<Impl>::trap(Fault fault, ThreadID tid, StaticInstPtr inst)
981{
982 // Pass the thread's TC into the invoke method.
983 fault->invoke(this->threadContexts[tid], inst);
984}
985
986template <class Impl>
987void
988FullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid)
989{
990 DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid);
991
992 DPRINTF(Activity,"Activity: syscall() called.\n");
993
994 // Temporarily increase this by one to account for the syscall
995 // instruction.
996 ++(this->thread[tid]->funcExeInst);
997
998 // Execute the actual syscall.
999 this->thread[tid]->syscall(callnum);
1000
1001 // Decrease funcExeInst by one as the normal commit will handle
1002 // incrementing it.
1003 --(this->thread[tid]->funcExeInst);
1004}
1005
1006template <class Impl>
1007void
1008FullO3CPU<Impl>::serialize(std::ostream &os)
1009{
1010 SimObject::State so_state = SimObject::getState();
1011 SERIALIZE_ENUM(so_state);
1012 BaseCPU::serialize(os);
1013 nameOut(os, csprintf("%s.tickEvent", name()));
1014 tickEvent.serialize(os);
1015
1016 // Use SimpleThread's ability to checkpoint to make it easier to
1017 // write out the registers. Also make this static so it doesn't
1018 // get instantiated multiple times (causes a panic in statistics).
1019 static SimpleThread temp;
1020
1021 ThreadID size = thread.size();
1022 for (ThreadID i = 0; i < size; i++) {
1023 nameOut(os, csprintf("%s.xc.%i", name(), i));
1024 temp.copyTC(thread[i]->getTC());
1025 temp.serialize(os);
1026 }
1027}
1028
1029template <class Impl>
1030void
1031FullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion)
1032{
1033 SimObject::State so_state;
1034 UNSERIALIZE_ENUM(so_state);
1035 BaseCPU::unserialize(cp, section);
1036 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
1037
1038 // Use SimpleThread's ability to checkpoint to make it easier to
1039 // read in the registers. Also make this static so it doesn't
1040 // get instantiated multiple times (causes a panic in statistics).
1041 static SimpleThread temp;
1042
1043 ThreadID size = thread.size();
1044 for (ThreadID i = 0; i < size; i++) {
1045 temp.copyTC(thread[i]->getTC());
1046 temp.unserialize(cp, csprintf("%s.xc.%i", section, i));
1047 thread[i]->getTC()->copyArchRegs(temp.getTC());
1048 }
1049}
1050
1051template <class Impl>
1052unsigned int
1053FullO3CPU<Impl>::drain(Event *drain_event)
1054{
1055 DPRINTF(O3CPU, "Switching out\n");
1056
1057 // If the CPU isn't doing anything, then return immediately.
1058 if (_status == Idle || _status == SwitchedOut) {
1059 return 0;
1060 }
1061
1062 drainCount = 0;
1063 fetch.drain();
1064 decode.drain();
1065 rename.drain();
1066 iew.drain();
1067 commit.drain();
1068
1069 // Wake the CPU and record activity so everything can drain out if
1070 // the CPU was not able to immediately drain.
1071 if (getState() != SimObject::Drained) {
1072 // A bit of a hack...set the drainEvent after all the drain()
1073 // calls have been made, that way if all of the stages drain
1074 // immediately, the signalDrained() function knows not to call
1075 // process on the drain event.
1076 drainEvent = drain_event;
1077
1078 wakeCPU();
1079 activityRec.activity();
1080
1081 return 1;
1082 } else {
1083 return 0;
1084 }
1085}
1086
1087template <class Impl>
1088void
1089FullO3CPU<Impl>::resume()
1090{
1091 fetch.resume();
1092 decode.resume();
1093 rename.resume();
1094 iew.resume();
1095 commit.resume();
1096
1097 changeState(SimObject::Running);
1098
1099 if (_status == SwitchedOut || _status == Idle)
1100 return;
1101
1102 assert(system->getMemoryMode() == Enums::timing);
1103
1104 if (!tickEvent.scheduled())
1105 schedule(tickEvent, nextCycle());
1106 _status = Running;
1107}
1108
1109template <class Impl>
1110void
1111FullO3CPU<Impl>::signalDrained()
1112{
1113 if (++drainCount == NumStages) {
1114 if (tickEvent.scheduled())
1115 tickEvent.squash();
1116
1117 changeState(SimObject::Drained);
1118
1119 BaseCPU::switchOut();
1120
1121 if (drainEvent) {
1122 drainEvent->process();
1123 drainEvent = NULL;
1124 }
1125 }
1126 assert(drainCount <= 5);
1127}
1128
1129template <class Impl>
1130void
1131FullO3CPU<Impl>::switchOut()
1132{
1133 fetch.switchOut();
1134 rename.switchOut();
1135 iew.switchOut();
1136 commit.switchOut();
1137 instList.clear();
1138 while (!removeList.empty()) {
1139 removeList.pop();
1140 }
1141
1142 _status = SwitchedOut;
1143#if USE_CHECKER
1144 if (checker)
1145 checker->switchOut();
1146#endif
1147 if (tickEvent.scheduled())
1148 tickEvent.squash();
1149}
1150
1151template <class Impl>
1152void
1153FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
1154{
1155 // Flush out any old data from the time buffers.
1156 for (int i = 0; i < timeBuffer.getSize(); ++i) {
1157 timeBuffer.advance();
1158 fetchQueue.advance();
1159 decodeQueue.advance();
1160 renameQueue.advance();
1161 iewQueue.advance();
1162 }
1163
1164 activityRec.reset();
1165
1166 BaseCPU::takeOverFrom(oldCPU, fetch.getIcachePort(), iew.getDcachePort());
1167
1168 fetch.takeOverFrom();
1169 decode.takeOverFrom();
1170 rename.takeOverFrom();
1171 iew.takeOverFrom();
1172 commit.takeOverFrom();
1173
1174 assert(!tickEvent.scheduled() || tickEvent.squashed());
1175
1176 // @todo: Figure out how to properly select the tid to put onto
1177 // the active threads list.
1178 ThreadID tid = 0;
1179
1180 list<ThreadID>::iterator isActive =
1181 std::find(activeThreads.begin(), activeThreads.end(), tid);
1182
1183 if (isActive == activeThreads.end()) {
1184 //May Need to Re-code this if the delay variable is the delay
1185 //needed for thread to activate
1186 DPRINTF(O3CPU, "Adding Thread %i to active threads list\n",
1187 tid);
1188
1189 activeThreads.push_back(tid);
1190 }
1191
1192 // Set all statuses to active, schedule the CPU's tick event.
1193 // @todo: Fix up statuses so this is handled properly
1194 ThreadID size = threadContexts.size();
1195 for (ThreadID i = 0; i < size; ++i) {
1196 ThreadContext *tc = threadContexts[i];
1197 if (tc->status() == ThreadContext::Active && _status != Running) {
1198 _status = Running;
1199 reschedule(tickEvent, nextCycle(), true);
1200 }
1201 }
1202 if (!tickEvent.scheduled())
1203 schedule(tickEvent, nextCycle());
1204}
1205
1206template <class Impl>
1207TheISA::MiscReg
1208FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid)
1209{
1210 return this->isa[tid].readMiscRegNoEffect(misc_reg);
1211}
1212
1213template <class Impl>
1214TheISA::MiscReg
1215FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
1216{
1217 miscRegfileReads++;
1218 return this->isa[tid].readMiscReg(misc_reg, tcBase(tid));
1219}
1220
1221template <class Impl>
1222void
1223FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
1224 const TheISA::MiscReg &val, ThreadID tid)
1225{
1226 this->isa[tid].setMiscRegNoEffect(misc_reg, val);
1227}
1228
1229template <class Impl>
1230void
1231FullO3CPU<Impl>::setMiscReg(int misc_reg,
1232 const TheISA::MiscReg &val, ThreadID tid)
1233{
1234 miscRegfileWrites++;
1235 this->isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
1236}
1237
1238template <class Impl>
1239uint64_t
1240FullO3CPU<Impl>::readIntReg(int reg_idx)
1241{
1242 intRegfileReads++;
1243 return regFile.readIntReg(reg_idx);
1244}
1245
1246template <class Impl>
1247FloatReg
1248FullO3CPU<Impl>::readFloatReg(int reg_idx)
1249{
1250 fpRegfileReads++;
1251 return regFile.readFloatReg(reg_idx);
1252}
1253
1254template <class Impl>
1255FloatRegBits
1256FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
1257{
1258 fpRegfileReads++;
1259 return regFile.readFloatRegBits(reg_idx);
1260}
1261
1262template <class Impl>
1263void
1264FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
1265{
1266 intRegfileWrites++;
1267 regFile.setIntReg(reg_idx, val);
1268}
1269
1270template <class Impl>
1271void
1272FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
1273{
1274 fpRegfileWrites++;
1275 regFile.setFloatReg(reg_idx, val);
1276}
1277
1278template <class Impl>
1279void
1280FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
1281{
1282 fpRegfileWrites++;
1283 regFile.setFloatRegBits(reg_idx, val);
1284}
1285
1286template <class Impl>
1287uint64_t
1288FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1289{
1290 intRegfileReads++;
1291 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1292
1293 return regFile.readIntReg(phys_reg);
1294}
1295
1296template <class Impl>
1297float
1298FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
1299{
1300 fpRegfileReads++;
1301 int idx = reg_idx + TheISA::NumIntRegs;
1302 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1303
1304 return regFile.readFloatReg(phys_reg);
1305}
1306
1307template <class Impl>
1308uint64_t
1309FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid)
1310{
1311 fpRegfileReads++;
1312 int idx = reg_idx + TheISA::NumIntRegs;
1313 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1314
1315 return regFile.readFloatRegBits(phys_reg);
1316}
1317
1318template <class Impl>
1319void
1320FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
1321{
1322 intRegfileWrites++;
1323 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1324
1325 regFile.setIntReg(phys_reg, val);
1326}
1327
1328template <class Impl>
1329void
1330FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid)
1331{
1332 fpRegfileWrites++;
1333 int idx = reg_idx + TheISA::NumIntRegs;
1334 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1335
1336 regFile.setFloatReg(phys_reg, val);
1337}
1338
1339template <class Impl>
1340void
1341FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid)
1342{
1343 fpRegfileWrites++;
1344 int idx = reg_idx + TheISA::NumIntRegs;
1345 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1346
1347 regFile.setFloatRegBits(phys_reg, val);
1348}
1349
1350template <class Impl>
1351TheISA::PCState
1352FullO3CPU<Impl>::pcState(ThreadID tid)
1353{
1354 return commit.pcState(tid);
1355}
1356
1357template <class Impl>
1358void
1359FullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid)
1360{
1361 commit.pcState(val, tid);
1362}
1363
1364template <class Impl>
1365Addr
1366FullO3CPU<Impl>::instAddr(ThreadID tid)
1367{
1368 return commit.instAddr(tid);
1369}
1370
1371template <class Impl>
1372Addr
1373FullO3CPU<Impl>::nextInstAddr(ThreadID tid)
1374{
1375 return commit.nextInstAddr(tid);
1376}
1377
1378template <class Impl>
1379MicroPC
1380FullO3CPU<Impl>::microPC(ThreadID tid)
1381{
1382 return commit.microPC(tid);
1383}
1384
1385template <class Impl>
1386void
1387FullO3CPU<Impl>::squashFromTC(ThreadID tid)
1388{
1389 this->thread[tid]->inSyscall = true;
1390 this->commit.generateTCEvent(tid);
1391}
1392
1393template <class Impl>
1394typename FullO3CPU<Impl>::ListIt
1395FullO3CPU<Impl>::addInst(DynInstPtr &inst)
1396{
1397 instList.push_back(inst);
1398
1399 return --(instList.end());
1400}
1401
1402template <class Impl>
1403void
1404FullO3CPU<Impl>::instDone(ThreadID tid)
1405{
1406 // Keep an instruction count.
1407 thread[tid]->numInst++;
1408 thread[tid]->numInsts++;
1409 committedInsts[tid]++;
1410 totalCommittedInsts++;
1411 system->totalNumInsts++;
1412 // Check for instruction-count-based events.
1413 comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1414 system->instEventQueue.serviceEvents(system->totalNumInsts);
1415}
1416
1417template <class Impl>
1418void
1419FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
1420{
1421 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s "
1422 "[sn:%lli]\n",
1423 inst->threadNumber, inst->pcState(), inst->seqNum);
1424
1425 removeInstsThisCycle = true;
1426
1427 // Remove the front instruction.
1428 removeList.push(inst->getInstListIt());
1429}
1430
1431template <class Impl>
1432void
1433FullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid)
1434{
1435 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1436 " list.\n", tid);
1437
1438 ListIt end_it;
1439
1440 bool rob_empty = false;
1441
1442 if (instList.empty()) {
1443 return;
1444 } else if (rob.isEmpty(/*tid*/)) {
1445 DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1446 end_it = instList.begin();
1447 rob_empty = true;
1448 } else {
1449 end_it = (rob.readTailInst(tid))->getInstListIt();
1450 DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1451 }
1452
1453 removeInstsThisCycle = true;
1454
1455 ListIt inst_it = instList.end();
1456
1457 inst_it--;
1458
1459 // Walk through the instruction list, removing any instructions
1460 // that were inserted after the given instruction iterator, end_it.
1461 while (inst_it != end_it) {
1462 assert(!instList.empty());
1463
1464 squashInstIt(inst_it, tid);
1465
1466 inst_it--;
1467 }
1468
1469 // If the ROB was empty, then we actually need to remove the first
1470 // instruction as well.
1471 if (rob_empty) {
1472 squashInstIt(inst_it, tid);
1473 }
1474}
1475
1476template <class Impl>
1477void
1478FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1479{
1480 assert(!instList.empty());
1481
1482 removeInstsThisCycle = true;
1483
1484 ListIt inst_iter = instList.end();
1485
1486 inst_iter--;
1487
1488 DPRINTF(O3CPU, "Deleting instructions from instruction "
1489 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1490 tid, seq_num, (*inst_iter)->seqNum);
1491
1492 while ((*inst_iter)->seqNum > seq_num) {
1493
1494 bool break_loop = (inst_iter == instList.begin());
1495
1496 squashInstIt(inst_iter, tid);
1497
1498 inst_iter--;
1499
1500 if (break_loop)
1501 break;
1502 }
1503}
1504
1505template <class Impl>
1506inline void
1507FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid)
1508{
1509 if ((*instIt)->threadNumber == tid) {
1510 DPRINTF(O3CPU, "Squashing instruction, "
1511 "[tid:%i] [sn:%lli] PC %s\n",
1512 (*instIt)->threadNumber,
1513 (*instIt)->seqNum,
1514 (*instIt)->pcState());
1515
1516 // Mark it as squashed.
1517 (*instIt)->setSquashed();
1518
1519 // @todo: Formulate a consistent method for deleting
1520 // instructions from the instruction list
1521 // Remove the instruction from the list.
1522 removeList.push(instIt);
1523 }
1524}
1525
1526template <class Impl>
1527void
1528FullO3CPU<Impl>::cleanUpRemovedInsts()
1529{
1530 while (!removeList.empty()) {
1531 DPRINTF(O3CPU, "Removing instruction, "
1532 "[tid:%i] [sn:%lli] PC %s\n",
1533 (*removeList.front())->threadNumber,
1534 (*removeList.front())->seqNum,
1535 (*removeList.front())->pcState());
1536
1537 instList.erase(removeList.front());
1538
1539 removeList.pop();
1540 }
1541
1542 removeInstsThisCycle = false;
1543}
1544/*
1545template <class Impl>
1546void
1547FullO3CPU<Impl>::removeAllInsts()
1548{
1549 instList.clear();
1550}
1551*/
1552template <class Impl>
1553void
1554FullO3CPU<Impl>::dumpInsts()
1555{
1556 int num = 0;
1557
1558 ListIt inst_list_it = instList.begin();
1559
1560 cprintf("Dumping Instruction List\n");
1561
1562 while (inst_list_it != instList.end()) {
1563 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1564 "Squashed:%i\n\n",
1565 num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber,
1566 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1567 (*inst_list_it)->isSquashed());
1568 inst_list_it++;
1569 ++num;
1570 }
1571}
1572/*
1573template <class Impl>
1574void
1575FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
1576{
1577 iew.wakeDependents(inst);
1578}
1579*/
1580template <class Impl>
1581void
1582FullO3CPU<Impl>::wakeCPU()
1583{
1584 if (activityRec.active() || tickEvent.scheduled()) {
1585 DPRINTF(Activity, "CPU already running.\n");
1586 return;
1587 }
1588
1589 DPRINTF(Activity, "Waking up CPU\n");
1590
1591 idleCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
1592 numCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
1593
1594 schedule(tickEvent, nextCycle());
1595}
1596
| 972
973template <class Impl>
974void
975FullO3CPU<Impl>::trap(Fault fault, ThreadID tid, StaticInstPtr inst)
976{
977 // Pass the thread's TC into the invoke method.
978 fault->invoke(this->threadContexts[tid], inst);
979}
980
981template <class Impl>
982void
983FullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid)
984{
985 DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid);
986
987 DPRINTF(Activity,"Activity: syscall() called.\n");
988
989 // Temporarily increase this by one to account for the syscall
990 // instruction.
991 ++(this->thread[tid]->funcExeInst);
992
993 // Execute the actual syscall.
994 this->thread[tid]->syscall(callnum);
995
996 // Decrease funcExeInst by one as the normal commit will handle
997 // incrementing it.
998 --(this->thread[tid]->funcExeInst);
999}
1000
1001template <class Impl>
1002void
1003FullO3CPU<Impl>::serialize(std::ostream &os)
1004{
1005 SimObject::State so_state = SimObject::getState();
1006 SERIALIZE_ENUM(so_state);
1007 BaseCPU::serialize(os);
1008 nameOut(os, csprintf("%s.tickEvent", name()));
1009 tickEvent.serialize(os);
1010
1011 // Use SimpleThread's ability to checkpoint to make it easier to
1012 // write out the registers. Also make this static so it doesn't
1013 // get instantiated multiple times (causes a panic in statistics).
1014 static SimpleThread temp;
1015
1016 ThreadID size = thread.size();
1017 for (ThreadID i = 0; i < size; i++) {
1018 nameOut(os, csprintf("%s.xc.%i", name(), i));
1019 temp.copyTC(thread[i]->getTC());
1020 temp.serialize(os);
1021 }
1022}
1023
1024template <class Impl>
1025void
1026FullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion)
1027{
1028 SimObject::State so_state;
1029 UNSERIALIZE_ENUM(so_state);
1030 BaseCPU::unserialize(cp, section);
1031 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
1032
1033 // Use SimpleThread's ability to checkpoint to make it easier to
1034 // read in the registers. Also make this static so it doesn't
1035 // get instantiated multiple times (causes a panic in statistics).
1036 static SimpleThread temp;
1037
1038 ThreadID size = thread.size();
1039 for (ThreadID i = 0; i < size; i++) {
1040 temp.copyTC(thread[i]->getTC());
1041 temp.unserialize(cp, csprintf("%s.xc.%i", section, i));
1042 thread[i]->getTC()->copyArchRegs(temp.getTC());
1043 }
1044}
1045
1046template <class Impl>
1047unsigned int
1048FullO3CPU<Impl>::drain(Event *drain_event)
1049{
1050 DPRINTF(O3CPU, "Switching out\n");
1051
1052 // If the CPU isn't doing anything, then return immediately.
1053 if (_status == Idle || _status == SwitchedOut) {
1054 return 0;
1055 }
1056
1057 drainCount = 0;
1058 fetch.drain();
1059 decode.drain();
1060 rename.drain();
1061 iew.drain();
1062 commit.drain();
1063
1064 // Wake the CPU and record activity so everything can drain out if
1065 // the CPU was not able to immediately drain.
1066 if (getState() != SimObject::Drained) {
1067 // A bit of a hack...set the drainEvent after all the drain()
1068 // calls have been made, that way if all of the stages drain
1069 // immediately, the signalDrained() function knows not to call
1070 // process on the drain event.
1071 drainEvent = drain_event;
1072
1073 wakeCPU();
1074 activityRec.activity();
1075
1076 return 1;
1077 } else {
1078 return 0;
1079 }
1080}
1081
1082template <class Impl>
1083void
1084FullO3CPU<Impl>::resume()
1085{
1086 fetch.resume();
1087 decode.resume();
1088 rename.resume();
1089 iew.resume();
1090 commit.resume();
1091
1092 changeState(SimObject::Running);
1093
1094 if (_status == SwitchedOut || _status == Idle)
1095 return;
1096
1097 assert(system->getMemoryMode() == Enums::timing);
1098
1099 if (!tickEvent.scheduled())
1100 schedule(tickEvent, nextCycle());
1101 _status = Running;
1102}
1103
1104template <class Impl>
1105void
1106FullO3CPU<Impl>::signalDrained()
1107{
1108 if (++drainCount == NumStages) {
1109 if (tickEvent.scheduled())
1110 tickEvent.squash();
1111
1112 changeState(SimObject::Drained);
1113
1114 BaseCPU::switchOut();
1115
1116 if (drainEvent) {
1117 drainEvent->process();
1118 drainEvent = NULL;
1119 }
1120 }
1121 assert(drainCount <= 5);
1122}
1123
1124template <class Impl>
1125void
1126FullO3CPU<Impl>::switchOut()
1127{
1128 fetch.switchOut();
1129 rename.switchOut();
1130 iew.switchOut();
1131 commit.switchOut();
1132 instList.clear();
1133 while (!removeList.empty()) {
1134 removeList.pop();
1135 }
1136
1137 _status = SwitchedOut;
1138#if USE_CHECKER
1139 if (checker)
1140 checker->switchOut();
1141#endif
1142 if (tickEvent.scheduled())
1143 tickEvent.squash();
1144}
1145
1146template <class Impl>
1147void
1148FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
1149{
1150 // Flush out any old data from the time buffers.
1151 for (int i = 0; i < timeBuffer.getSize(); ++i) {
1152 timeBuffer.advance();
1153 fetchQueue.advance();
1154 decodeQueue.advance();
1155 renameQueue.advance();
1156 iewQueue.advance();
1157 }
1158
1159 activityRec.reset();
1160
1161 BaseCPU::takeOverFrom(oldCPU, fetch.getIcachePort(), iew.getDcachePort());
1162
1163 fetch.takeOverFrom();
1164 decode.takeOverFrom();
1165 rename.takeOverFrom();
1166 iew.takeOverFrom();
1167 commit.takeOverFrom();
1168
1169 assert(!tickEvent.scheduled() || tickEvent.squashed());
1170
1171 // @todo: Figure out how to properly select the tid to put onto
1172 // the active threads list.
1173 ThreadID tid = 0;
1174
1175 list<ThreadID>::iterator isActive =
1176 std::find(activeThreads.begin(), activeThreads.end(), tid);
1177
1178 if (isActive == activeThreads.end()) {
1179 //May Need to Re-code this if the delay variable is the delay
1180 //needed for thread to activate
1181 DPRINTF(O3CPU, "Adding Thread %i to active threads list\n",
1182 tid);
1183
1184 activeThreads.push_back(tid);
1185 }
1186
1187 // Set all statuses to active, schedule the CPU's tick event.
1188 // @todo: Fix up statuses so this is handled properly
1189 ThreadID size = threadContexts.size();
1190 for (ThreadID i = 0; i < size; ++i) {
1191 ThreadContext *tc = threadContexts[i];
1192 if (tc->status() == ThreadContext::Active && _status != Running) {
1193 _status = Running;
1194 reschedule(tickEvent, nextCycle(), true);
1195 }
1196 }
1197 if (!tickEvent.scheduled())
1198 schedule(tickEvent, nextCycle());
1199}
1200
1201template <class Impl>
1202TheISA::MiscReg
1203FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid)
1204{
1205 return this->isa[tid].readMiscRegNoEffect(misc_reg);
1206}
1207
1208template <class Impl>
1209TheISA::MiscReg
1210FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
1211{
1212 miscRegfileReads++;
1213 return this->isa[tid].readMiscReg(misc_reg, tcBase(tid));
1214}
1215
1216template <class Impl>
1217void
1218FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
1219 const TheISA::MiscReg &val, ThreadID tid)
1220{
1221 this->isa[tid].setMiscRegNoEffect(misc_reg, val);
1222}
1223
1224template <class Impl>
1225void
1226FullO3CPU<Impl>::setMiscReg(int misc_reg,
1227 const TheISA::MiscReg &val, ThreadID tid)
1228{
1229 miscRegfileWrites++;
1230 this->isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
1231}
1232
1233template <class Impl>
1234uint64_t
1235FullO3CPU<Impl>::readIntReg(int reg_idx)
1236{
1237 intRegfileReads++;
1238 return regFile.readIntReg(reg_idx);
1239}
1240
1241template <class Impl>
1242FloatReg
1243FullO3CPU<Impl>::readFloatReg(int reg_idx)
1244{
1245 fpRegfileReads++;
1246 return regFile.readFloatReg(reg_idx);
1247}
1248
1249template <class Impl>
1250FloatRegBits
1251FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
1252{
1253 fpRegfileReads++;
1254 return regFile.readFloatRegBits(reg_idx);
1255}
1256
1257template <class Impl>
1258void
1259FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
1260{
1261 intRegfileWrites++;
1262 regFile.setIntReg(reg_idx, val);
1263}
1264
1265template <class Impl>
1266void
1267FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
1268{
1269 fpRegfileWrites++;
1270 regFile.setFloatReg(reg_idx, val);
1271}
1272
1273template <class Impl>
1274void
1275FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
1276{
1277 fpRegfileWrites++;
1278 regFile.setFloatRegBits(reg_idx, val);
1279}
1280
1281template <class Impl>
1282uint64_t
1283FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1284{
1285 intRegfileReads++;
1286 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1287
1288 return regFile.readIntReg(phys_reg);
1289}
1290
1291template <class Impl>
1292float
1293FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
1294{
1295 fpRegfileReads++;
1296 int idx = reg_idx + TheISA::NumIntRegs;
1297 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1298
1299 return regFile.readFloatReg(phys_reg);
1300}
1301
1302template <class Impl>
1303uint64_t
1304FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid)
1305{
1306 fpRegfileReads++;
1307 int idx = reg_idx + TheISA::NumIntRegs;
1308 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1309
1310 return regFile.readFloatRegBits(phys_reg);
1311}
1312
1313template <class Impl>
1314void
1315FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
1316{
1317 intRegfileWrites++;
1318 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1319
1320 regFile.setIntReg(phys_reg, val);
1321}
1322
1323template <class Impl>
1324void
1325FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid)
1326{
1327 fpRegfileWrites++;
1328 int idx = reg_idx + TheISA::NumIntRegs;
1329 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1330
1331 regFile.setFloatReg(phys_reg, val);
1332}
1333
1334template <class Impl>
1335void
1336FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid)
1337{
1338 fpRegfileWrites++;
1339 int idx = reg_idx + TheISA::NumIntRegs;
1340 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1341
1342 regFile.setFloatRegBits(phys_reg, val);
1343}
1344
1345template <class Impl>
1346TheISA::PCState
1347FullO3CPU<Impl>::pcState(ThreadID tid)
1348{
1349 return commit.pcState(tid);
1350}
1351
1352template <class Impl>
1353void
1354FullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid)
1355{
1356 commit.pcState(val, tid);
1357}
1358
1359template <class Impl>
1360Addr
1361FullO3CPU<Impl>::instAddr(ThreadID tid)
1362{
1363 return commit.instAddr(tid);
1364}
1365
1366template <class Impl>
1367Addr
1368FullO3CPU<Impl>::nextInstAddr(ThreadID tid)
1369{
1370 return commit.nextInstAddr(tid);
1371}
1372
1373template <class Impl>
1374MicroPC
1375FullO3CPU<Impl>::microPC(ThreadID tid)
1376{
1377 return commit.microPC(tid);
1378}
1379
1380template <class Impl>
1381void
1382FullO3CPU<Impl>::squashFromTC(ThreadID tid)
1383{
1384 this->thread[tid]->inSyscall = true;
1385 this->commit.generateTCEvent(tid);
1386}
1387
1388template <class Impl>
1389typename FullO3CPU<Impl>::ListIt
1390FullO3CPU<Impl>::addInst(DynInstPtr &inst)
1391{
1392 instList.push_back(inst);
1393
1394 return --(instList.end());
1395}
1396
1397template <class Impl>
1398void
1399FullO3CPU<Impl>::instDone(ThreadID tid)
1400{
1401 // Keep an instruction count.
1402 thread[tid]->numInst++;
1403 thread[tid]->numInsts++;
1404 committedInsts[tid]++;
1405 totalCommittedInsts++;
1406 system->totalNumInsts++;
1407 // Check for instruction-count-based events.
1408 comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1409 system->instEventQueue.serviceEvents(system->totalNumInsts);
1410}
1411
1412template <class Impl>
1413void
1414FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
1415{
1416 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s "
1417 "[sn:%lli]\n",
1418 inst->threadNumber, inst->pcState(), inst->seqNum);
1419
1420 removeInstsThisCycle = true;
1421
1422 // Remove the front instruction.
1423 removeList.push(inst->getInstListIt());
1424}
1425
1426template <class Impl>
1427void
1428FullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid)
1429{
1430 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1431 " list.\n", tid);
1432
1433 ListIt end_it;
1434
1435 bool rob_empty = false;
1436
1437 if (instList.empty()) {
1438 return;
1439 } else if (rob.isEmpty(/*tid*/)) {
1440 DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1441 end_it = instList.begin();
1442 rob_empty = true;
1443 } else {
1444 end_it = (rob.readTailInst(tid))->getInstListIt();
1445 DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1446 }
1447
1448 removeInstsThisCycle = true;
1449
1450 ListIt inst_it = instList.end();
1451
1452 inst_it--;
1453
1454 // Walk through the instruction list, removing any instructions
1455 // that were inserted after the given instruction iterator, end_it.
1456 while (inst_it != end_it) {
1457 assert(!instList.empty());
1458
1459 squashInstIt(inst_it, tid);
1460
1461 inst_it--;
1462 }
1463
1464 // If the ROB was empty, then we actually need to remove the first
1465 // instruction as well.
1466 if (rob_empty) {
1467 squashInstIt(inst_it, tid);
1468 }
1469}
1470
1471template <class Impl>
1472void
1473FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1474{
1475 assert(!instList.empty());
1476
1477 removeInstsThisCycle = true;
1478
1479 ListIt inst_iter = instList.end();
1480
1481 inst_iter--;
1482
1483 DPRINTF(O3CPU, "Deleting instructions from instruction "
1484 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1485 tid, seq_num, (*inst_iter)->seqNum);
1486
1487 while ((*inst_iter)->seqNum > seq_num) {
1488
1489 bool break_loop = (inst_iter == instList.begin());
1490
1491 squashInstIt(inst_iter, tid);
1492
1493 inst_iter--;
1494
1495 if (break_loop)
1496 break;
1497 }
1498}
1499
1500template <class Impl>
1501inline void
1502FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid)
1503{
1504 if ((*instIt)->threadNumber == tid) {
1505 DPRINTF(O3CPU, "Squashing instruction, "
1506 "[tid:%i] [sn:%lli] PC %s\n",
1507 (*instIt)->threadNumber,
1508 (*instIt)->seqNum,
1509 (*instIt)->pcState());
1510
1511 // Mark it as squashed.
1512 (*instIt)->setSquashed();
1513
1514 // @todo: Formulate a consistent method for deleting
1515 // instructions from the instruction list
1516 // Remove the instruction from the list.
1517 removeList.push(instIt);
1518 }
1519}
1520
1521template <class Impl>
1522void
1523FullO3CPU<Impl>::cleanUpRemovedInsts()
1524{
1525 while (!removeList.empty()) {
1526 DPRINTF(O3CPU, "Removing instruction, "
1527 "[tid:%i] [sn:%lli] PC %s\n",
1528 (*removeList.front())->threadNumber,
1529 (*removeList.front())->seqNum,
1530 (*removeList.front())->pcState());
1531
1532 instList.erase(removeList.front());
1533
1534 removeList.pop();
1535 }
1536
1537 removeInstsThisCycle = false;
1538}
1539/*
1540template <class Impl>
1541void
1542FullO3CPU<Impl>::removeAllInsts()
1543{
1544 instList.clear();
1545}
1546*/
1547template <class Impl>
1548void
1549FullO3CPU<Impl>::dumpInsts()
1550{
1551 int num = 0;
1552
1553 ListIt inst_list_it = instList.begin();
1554
1555 cprintf("Dumping Instruction List\n");
1556
1557 while (inst_list_it != instList.end()) {
1558 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1559 "Squashed:%i\n\n",
1560 num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber,
1561 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1562 (*inst_list_it)->isSquashed());
1563 inst_list_it++;
1564 ++num;
1565 }
1566}
1567/*
1568template <class Impl>
1569void
1570FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
1571{
1572 iew.wakeDependents(inst);
1573}
1574*/
1575template <class Impl>
1576void
1577FullO3CPU<Impl>::wakeCPU()
1578{
1579 if (activityRec.active() || tickEvent.scheduled()) {
1580 DPRINTF(Activity, "CPU already running.\n");
1581 return;
1582 }
1583
1584 DPRINTF(Activity, "Waking up CPU\n");
1585
1586 idleCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
1587 numCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
1588
1589 schedule(tickEvent, nextCycle());
1590}
1591
|
1597#if FULL_SYSTEM
| |
1598template <class Impl>
1599void
1600FullO3CPU<Impl>::wakeup()
1601{
1602 if (this->thread[0]->status() != ThreadContext::Suspended)
1603 return;
1604
1605 this->wakeCPU();
1606
1607 DPRINTF(Quiesce, "Suspended Processor woken\n");
1608 this->threadContexts[0]->activate();
1609}
| 1592template <class Impl>
1593void
1594FullO3CPU<Impl>::wakeup()
1595{
1596 if (this->thread[0]->status() != ThreadContext::Suspended)
1597 return;
1598
1599 this->wakeCPU();
1600
1601 DPRINTF(Quiesce, "Suspended Processor woken\n");
1602 this->threadContexts[0]->activate();
1603}
|
1610#endif
| |
1611
1612template <class Impl>
1613ThreadID
1614FullO3CPU<Impl>::getFreeTid()
1615{
1616 for (ThreadID tid = 0; tid < numThreads; tid++) {
1617 if (!tids[tid]) {
1618 tids[tid] = true;
1619 return tid;
1620 }
1621 }
1622
1623 return InvalidThreadID;
1624}
1625
1626template <class Impl>
1627void
1628FullO3CPU<Impl>::doContextSwitch()
1629{
1630 if (contextSwitch) {
1631
1632 //ADD CODE TO DEACTIVE THREAD HERE (???)
1633
1634 ThreadID size = cpuWaitList.size();
1635 for (ThreadID tid = 0; tid < size; tid++) {
1636 activateWhenReady(tid);
1637 }
1638
1639 if (cpuWaitList.size() == 0)
1640 contextSwitch = true;
1641 }
1642}
1643
1644template <class Impl>
1645void
1646FullO3CPU<Impl>::updateThreadPriority()
1647{
1648 if (activeThreads.size() > 1) {
1649 //DEFAULT TO ROUND ROBIN SCHEME
1650 //e.g. Move highest priority to end of thread list
1651 list<ThreadID>::iterator list_begin = activeThreads.begin();
1652 list<ThreadID>::iterator list_end = activeThreads.end();
1653
1654 unsigned high_thread = *list_begin;
1655
1656 activeThreads.erase(list_begin);
1657
1658 activeThreads.push_back(high_thread);
1659 }
1660}
1661
1662// Forward declaration of FullO3CPU.
1663template class FullO3CPU<O3CPUImpl>;
| 1604
1605template <class Impl>
1606ThreadID
1607FullO3CPU<Impl>::getFreeTid()
1608{
1609 for (ThreadID tid = 0; tid < numThreads; tid++) {
1610 if (!tids[tid]) {
1611 tids[tid] = true;
1612 return tid;
1613 }
1614 }
1615
1616 return InvalidThreadID;
1617}
1618
1619template <class Impl>
1620void
1621FullO3CPU<Impl>::doContextSwitch()
1622{
1623 if (contextSwitch) {
1624
1625 //ADD CODE TO DEACTIVE THREAD HERE (???)
1626
1627 ThreadID size = cpuWaitList.size();
1628 for (ThreadID tid = 0; tid < size; tid++) {
1629 activateWhenReady(tid);
1630 }
1631
1632 if (cpuWaitList.size() == 0)
1633 contextSwitch = true;
1634 }
1635}
1636
1637template <class Impl>
1638void
1639FullO3CPU<Impl>::updateThreadPriority()
1640{
1641 if (activeThreads.size() > 1) {
1642 //DEFAULT TO ROUND ROBIN SCHEME
1643 //e.g. Move highest priority to end of thread list
1644 list<ThreadID>::iterator list_begin = activeThreads.begin();
1645 list<ThreadID>::iterator list_end = activeThreads.end();
1646
1647 unsigned high_thread = *list_begin;
1648
1649 activeThreads.erase(list_begin);
1650
1651 activeThreads.push_back(high_thread);
1652 }
1653}
1654
1655// Forward declaration of FullO3CPU.
1656template class FullO3CPU<O3CPUImpl>;
|