1/*
| 1/*
|
| 2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
|
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * Copyright (c) 2011 Regents of the University of California
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Kevin Lim
30 * Korey Sewell
31 * Rick Strong
32 */
33
34#include "config/full_system.hh"
35#include "config/the_isa.hh"
36#include "config/use_checker.hh"
37#include "cpu/o3/cpu.hh"
38#include "cpu/o3/isa_specific.hh"
39#include "cpu/o3/thread_context.hh"
40#include "cpu/activity.hh"
41#include "cpu/simple_thread.hh"
42#include "cpu/thread_context.hh"
43#include "debug/Activity.hh"
44#include "debug/O3CPU.hh"
45#include "debug/Quiesce.hh"
46#include "enums/MemoryMode.hh"
47#include "sim/core.hh"
48#include "sim/stat_control.hh"
49#include "sim/system.hh"
50
51#if FULL_SYSTEM
52#include "cpu/quiesce_event.hh"
53#else
54#include "sim/process.hh"
55#endif
56
57#if USE_CHECKER
58#include "cpu/checker/cpu.hh"
59#endif
60
61#if THE_ISA == ALPHA_ISA
62#include "arch/alpha/osfpal.hh"
63#include "debug/Activity.hh"
64#endif
65
66class BaseCPUParams;
67
68using namespace TheISA;
69using namespace std;
70
71BaseO3CPU::BaseO3CPU(BaseCPUParams *params)
72 : BaseCPU(params)
73{
74}
75
76void
77BaseO3CPU::regStats()
78{
79 BaseCPU::regStats();
80}
81
| 14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 * Korey Sewell
43 * Rick Strong
44 */
45
46#include "config/full_system.hh"
47#include "config/the_isa.hh"
48#include "config/use_checker.hh"
49#include "cpu/o3/cpu.hh"
50#include "cpu/o3/isa_specific.hh"
51#include "cpu/o3/thread_context.hh"
52#include "cpu/activity.hh"
53#include "cpu/simple_thread.hh"
54#include "cpu/thread_context.hh"
55#include "debug/Activity.hh"
56#include "debug/O3CPU.hh"
57#include "debug/Quiesce.hh"
58#include "enums/MemoryMode.hh"
59#include "sim/core.hh"
60#include "sim/stat_control.hh"
61#include "sim/system.hh"
62
63#if FULL_SYSTEM
64#include "cpu/quiesce_event.hh"
65#else
66#include "sim/process.hh"
67#endif
68
69#if USE_CHECKER
70#include "cpu/checker/cpu.hh"
71#endif
72
73#if THE_ISA == ALPHA_ISA
74#include "arch/alpha/osfpal.hh"
75#include "debug/Activity.hh"
76#endif
77
78class BaseCPUParams;
79
80using namespace TheISA;
81using namespace std;
82
83BaseO3CPU::BaseO3CPU(BaseCPUParams *params)
84 : BaseCPU(params)
85{
86}
87
88void
89BaseO3CPU::regStats()
90{
91 BaseCPU::regStats();
92}
93
|
| 94template<class Impl>
95bool
96FullO3CPU<Impl>::IcachePort::recvTiming(PacketPtr pkt)
97{
98 DPRINTF(O3CPU, "Fetch unit received timing\n");
99 if (pkt->isResponse()) {
100 // We shouldn't ever get a block in ownership state
101 assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted()));
102
103 fetch->processCacheCompletion(pkt);
104 }
105 //else Snooped a coherence request, just return
106 return true;
107}
108
109template<class Impl>
110void
111FullO3CPU<Impl>::IcachePort::recvRetry()
112{
113 fetch->recvRetry();
114}
115
|
82template <class Impl>
| 116template <class Impl>
|
| 117bool
118FullO3CPU<Impl>::DcachePort::recvTiming(PacketPtr pkt)
119{
120 return lsq->recvTiming(pkt);
121}
122
123template <class Impl>
124void
125FullO3CPU<Impl>::DcachePort::recvRetry()
126{
127 lsq->recvRetry();
128}
129
130template <class Impl>
|
83FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
84 : Event(CPU_Tick_Pri), cpu(c)
85{
86}
87
88template <class Impl>
89void
90FullO3CPU<Impl>::TickEvent::process()
91{
92 cpu->tick();
93}
94
95template <class Impl>
96const char *
97FullO3CPU<Impl>::TickEvent::description() const
98{
99 return "FullO3CPU tick";
100}
101
102template <class Impl>
103FullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent()
104 : Event(CPU_Switch_Pri)
105{
106}
107
108template <class Impl>
109void
110FullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num,
111 FullO3CPU<Impl> *thread_cpu)
112{
113 tid = thread_num;
114 cpu = thread_cpu;
115}
116
117template <class Impl>
118void
119FullO3CPU<Impl>::ActivateThreadEvent::process()
120{
121 cpu->activateThread(tid);
122}
123
124template <class Impl>
125const char *
126FullO3CPU<Impl>::ActivateThreadEvent::description() const
127{
128 return "FullO3CPU \"Activate Thread\"";
129}
130
131template <class Impl>
132FullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent()
133 : Event(CPU_Tick_Pri), tid(0), remove(false), cpu(NULL)
134{
135}
136
137template <class Impl>
138void
139FullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num,
140 FullO3CPU<Impl> *thread_cpu)
141{
142 tid = thread_num;
143 cpu = thread_cpu;
144 remove = false;
145}
146
147template <class Impl>
148void
149FullO3CPU<Impl>::DeallocateContextEvent::process()
150{
151 cpu->deactivateThread(tid);
152 if (remove)
153 cpu->removeThread(tid);
154}
155
156template <class Impl>
157const char *
158FullO3CPU<Impl>::DeallocateContextEvent::description() const
159{
160 return "FullO3CPU \"Deallocate Context\"";
161}
162
163template <class Impl>
164FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
165 : BaseO3CPU(params),
166 itb(params->itb),
167 dtb(params->dtb),
168 tickEvent(this),
169#ifndef NDEBUG
170 instcount(0),
171#endif
172 removeInstsThisCycle(false),
173 fetch(this, params),
174 decode(this, params),
175 rename(this, params),
176 iew(this, params),
177 commit(this, params),
178
179 regFile(this, params->numPhysIntRegs,
180 params->numPhysFloatRegs),
181
182 freeList(params->numThreads,
183 TheISA::NumIntRegs, params->numPhysIntRegs,
184 TheISA::NumFloatRegs, params->numPhysFloatRegs),
185
186 rob(this,
187 params->numROBEntries, params->squashWidth,
188 params->smtROBPolicy, params->smtROBThreshold,
189 params->numThreads),
190
191 scoreboard(params->numThreads,
192 TheISA::NumIntRegs, params->numPhysIntRegs,
193 TheISA::NumFloatRegs, params->numPhysFloatRegs,
194 TheISA::NumMiscRegs * numThreads,
195 TheISA::ZeroReg),
196
| 131FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
132 : Event(CPU_Tick_Pri), cpu(c)
133{
134}
135
136template <class Impl>
137void
138FullO3CPU<Impl>::TickEvent::process()
139{
140 cpu->tick();
141}
142
143template <class Impl>
144const char *
145FullO3CPU<Impl>::TickEvent::description() const
146{
147 return "FullO3CPU tick";
148}
149
150template <class Impl>
151FullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent()
152 : Event(CPU_Switch_Pri)
153{
154}
155
156template <class Impl>
157void
158FullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num,
159 FullO3CPU<Impl> *thread_cpu)
160{
161 tid = thread_num;
162 cpu = thread_cpu;
163}
164
165template <class Impl>
166void
167FullO3CPU<Impl>::ActivateThreadEvent::process()
168{
169 cpu->activateThread(tid);
170}
171
172template <class Impl>
173const char *
174FullO3CPU<Impl>::ActivateThreadEvent::description() const
175{
176 return "FullO3CPU \"Activate Thread\"";
177}
178
179template <class Impl>
180FullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent()
181 : Event(CPU_Tick_Pri), tid(0), remove(false), cpu(NULL)
182{
183}
184
185template <class Impl>
186void
187FullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num,
188 FullO3CPU<Impl> *thread_cpu)
189{
190 tid = thread_num;
191 cpu = thread_cpu;
192 remove = false;
193}
194
195template <class Impl>
196void
197FullO3CPU<Impl>::DeallocateContextEvent::process()
198{
199 cpu->deactivateThread(tid);
200 if (remove)
201 cpu->removeThread(tid);
202}
203
204template <class Impl>
205const char *
206FullO3CPU<Impl>::DeallocateContextEvent::description() const
207{
208 return "FullO3CPU \"Deallocate Context\"";
209}
210
211template <class Impl>
212FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
213 : BaseO3CPU(params),
214 itb(params->itb),
215 dtb(params->dtb),
216 tickEvent(this),
217#ifndef NDEBUG
218 instcount(0),
219#endif
220 removeInstsThisCycle(false),
221 fetch(this, params),
222 decode(this, params),
223 rename(this, params),
224 iew(this, params),
225 commit(this, params),
226
227 regFile(this, params->numPhysIntRegs,
228 params->numPhysFloatRegs),
229
230 freeList(params->numThreads,
231 TheISA::NumIntRegs, params->numPhysIntRegs,
232 TheISA::NumFloatRegs, params->numPhysFloatRegs),
233
234 rob(this,
235 params->numROBEntries, params->squashWidth,
236 params->smtROBPolicy, params->smtROBThreshold,
237 params->numThreads),
238
239 scoreboard(params->numThreads,
240 TheISA::NumIntRegs, params->numPhysIntRegs,
241 TheISA::NumFloatRegs, params->numPhysFloatRegs,
242 TheISA::NumMiscRegs * numThreads,
243 TheISA::ZeroReg),
244
|
| 245 icachePort(&fetch, this),
246 dcachePort(&iew.ldstQueue, this),
247
|
197 timeBuffer(params->backComSize, params->forwardComSize),
198 fetchQueue(params->backComSize, params->forwardComSize),
199 decodeQueue(params->backComSize, params->forwardComSize),
200 renameQueue(params->backComSize, params->forwardComSize),
201 iewQueue(params->backComSize, params->forwardComSize),
202 activityRec(name(), NumStages,
203 params->backComSize + params->forwardComSize,
204 params->activity),
205
206 globalSeqNum(1),
207 system(params->system),
208 drainCount(0),
209 deferRegistration(params->defer_registration)
210{
211 if (!deferRegistration) {
212 _status = Running;
213 } else {
214 _status = Idle;
215 }
216
217#if USE_CHECKER
218 if (params->checker) {
219 BaseCPU *temp_checker = params->checker;
220 checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
| 248 timeBuffer(params->backComSize, params->forwardComSize),
249 fetchQueue(params->backComSize, params->forwardComSize),
250 decodeQueue(params->backComSize, params->forwardComSize),
251 renameQueue(params->backComSize, params->forwardComSize),
252 iewQueue(params->backComSize, params->forwardComSize),
253 activityRec(name(), NumStages,
254 params->backComSize + params->forwardComSize,
255 params->activity),
256
257 globalSeqNum(1),
258 system(params->system),
259 drainCount(0),
260 deferRegistration(params->defer_registration)
261{
262 if (!deferRegistration) {
263 _status = Running;
264 } else {
265 _status = Idle;
266 }
267
268#if USE_CHECKER
269 if (params->checker) {
270 BaseCPU *temp_checker = params->checker;
271 checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
|
| 272 checker->setIcachePort(&icachePort);
|
221#if FULL_SYSTEM
222 checker->setSystem(params->system);
223#endif
224 } else {
225 checker = NULL;
226 }
227#endif // USE_CHECKER
228
229#if !FULL_SYSTEM
230 thread.resize(numThreads);
231 tids.resize(numThreads);
232#endif
233
234 // The stages also need their CPU pointer setup. However this
235 // must be done at the upper level CPU because they have pointers
236 // to the upper level CPU, and not this FullO3CPU.
237
238 // Set up Pointers to the activeThreads list for each stage
239 fetch.setActiveThreads(&activeThreads);
240 decode.setActiveThreads(&activeThreads);
241 rename.setActiveThreads(&activeThreads);
242 iew.setActiveThreads(&activeThreads);
243 commit.setActiveThreads(&activeThreads);
244
245 // Give each of the stages the time buffer they will use.
246 fetch.setTimeBuffer(&timeBuffer);
247 decode.setTimeBuffer(&timeBuffer);
248 rename.setTimeBuffer(&timeBuffer);
249 iew.setTimeBuffer(&timeBuffer);
250 commit.setTimeBuffer(&timeBuffer);
251
252 // Also setup each of the stages' queues.
253 fetch.setFetchQueue(&fetchQueue);
254 decode.setFetchQueue(&fetchQueue);
255 commit.setFetchQueue(&fetchQueue);
256 decode.setDecodeQueue(&decodeQueue);
257 rename.setDecodeQueue(&decodeQueue);
258 rename.setRenameQueue(&renameQueue);
259 iew.setRenameQueue(&renameQueue);
260 iew.setIEWQueue(&iewQueue);
261 commit.setIEWQueue(&iewQueue);
262 commit.setRenameQueue(&renameQueue);
263
264 commit.setIEWStage(&iew);
265 rename.setIEWStage(&iew);
266 rename.setCommitStage(&commit);
267
268#if !FULL_SYSTEM
269 ThreadID active_threads = params->workload.size();
270
271 if (active_threads > Impl::MaxThreads) {
272 panic("Workload Size too large. Increase the 'MaxThreads'"
273 "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or "
274 "edit your workload size.");
275 }
276#else
277 ThreadID active_threads = 1;
278#endif
279
280 //Make Sure That this a Valid Architeture
281 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs);
282 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
283
284 rename.setScoreboard(&scoreboard);
285 iew.setScoreboard(&scoreboard);
286
287 // Setup the rename map for whichever stages need it.
288 PhysRegIndex lreg_idx = 0;
289 PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs
290
291 for (ThreadID tid = 0; tid < numThreads; tid++) {
292 bool bindRegs = (tid <= active_threads - 1);
293
294 commitRenameMap[tid].init(TheISA::NumIntRegs,
295 params->numPhysIntRegs,
296 lreg_idx, //Index for Logical. Regs
297
298 TheISA::NumFloatRegs,
299 params->numPhysFloatRegs,
300 freg_idx, //Index for Float Regs
301
302 TheISA::NumMiscRegs,
303
304 TheISA::ZeroReg,
305 TheISA::ZeroReg,
306
307 tid,
308 false);
309
310 renameMap[tid].init(TheISA::NumIntRegs,
311 params->numPhysIntRegs,
312 lreg_idx, //Index for Logical. Regs
313
314 TheISA::NumFloatRegs,
315 params->numPhysFloatRegs,
316 freg_idx, //Index for Float Regs
317
318 TheISA::NumMiscRegs,
319
320 TheISA::ZeroReg,
321 TheISA::ZeroReg,
322
323 tid,
324 bindRegs);
325
326 activateThreadEvent[tid].init(tid, this);
327 deallocateContextEvent[tid].init(tid, this);
328 }
329
330 rename.setRenameMap(renameMap);
331 commit.setRenameMap(commitRenameMap);
332
333 // Give renameMap & rename stage access to the freeList;
334 for (ThreadID tid = 0; tid < numThreads; tid++)
335 renameMap[tid].setFreeList(&freeList);
336 rename.setFreeList(&freeList);
337
338 // Setup the ROB for whichever stages need it.
339 commit.setROB(&rob);
340
341 lastRunningCycle = curTick();
342
343 lastActivatedCycle = -1;
344#if 0
345 // Give renameMap & rename stage access to the freeList;
346 for (ThreadID tid = 0; tid < numThreads; tid++)
347 globalSeqNum[tid] = 1;
348#endif
349
350 contextSwitch = false;
351 DPRINTF(O3CPU, "Creating O3CPU object.\n");
352
353 // Setup any thread state.
354 this->thread.resize(this->numThreads);
355
356 for (ThreadID tid = 0; tid < this->numThreads; ++tid) {
357#if FULL_SYSTEM
358 // SMT is not supported in FS mode yet.
359 assert(this->numThreads == 1);
360 this->thread[tid] = new Thread(this, 0);
361#else
362 if (tid < params->workload.size()) {
363 DPRINTF(O3CPU, "Workload[%i] process is %#x",
364 tid, this->thread[tid]);
365 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
366 (typename Impl::O3CPU *)(this),
367 tid, params->workload[tid]);
368
369 //usedTids[tid] = true;
370 //threadMap[tid] = tid;
371 } else {
372 //Allocate Empty thread so M5 can use later
373 //when scheduling threads to CPU
374 Process* dummy_proc = NULL;
375
376 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
377 (typename Impl::O3CPU *)(this),
378 tid, dummy_proc);
379 //usedTids[tid] = false;
380 }
381#endif // !FULL_SYSTEM
382
383 ThreadContext *tc;
384
385 // Setup the TC that will serve as the interface to the threads/CPU.
386 O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>;
387
388 tc = o3_tc;
389
390 // If we're using a checker, then the TC should be the
391 // CheckerThreadContext.
392#if USE_CHECKER
393 if (params->checker) {
394 tc = new CheckerThreadContext<O3ThreadContext<Impl> >(
395 o3_tc, this->checker);
396 }
397#endif
398
399 o3_tc->cpu = (typename Impl::O3CPU *)(this);
400 assert(o3_tc->cpu);
401 o3_tc->thread = this->thread[tid];
402
403#if FULL_SYSTEM
404 // Setup quiesce event.
405 this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
406#endif
407 // Give the thread the TC.
408 this->thread[tid]->tc = tc;
409
410 // Add the TC to the CPU's list of TC's.
411 this->threadContexts.push_back(tc);
412 }
413
414 for (ThreadID tid = 0; tid < this->numThreads; tid++)
415 this->thread[tid]->setFuncExeInst(0);
416
417 lockAddr = 0;
418 lockFlag = false;
419}
420
421template <class Impl>
422FullO3CPU<Impl>::~FullO3CPU()
423{
424}
425
426template <class Impl>
427void
428FullO3CPU<Impl>::regStats()
429{
430 BaseO3CPU::regStats();
431
432 // Register any of the O3CPU's stats here.
433 timesIdled
434 .name(name() + ".timesIdled")
435 .desc("Number of times that the entire CPU went into an idle state and"
436 " unscheduled itself")
437 .prereq(timesIdled);
438
439 idleCycles
440 .name(name() + ".idleCycles")
441 .desc("Total number of cycles that the CPU has spent unscheduled due "
442 "to idling")
443 .prereq(idleCycles);
444
445 quiesceCycles
446 .name(name() + ".quiesceCycles")
447 .desc("Total number of cycles that CPU has spent quiesced or waiting "
448 "for an interrupt")
449 .prereq(quiesceCycles);
450
451 // Number of Instructions simulated
452 // --------------------------------
453 // Should probably be in Base CPU but need templated
454 // MaxThreads so put in here instead
455 committedInsts
456 .init(numThreads)
457 .name(name() + ".committedInsts")
458 .desc("Number of Instructions Simulated");
459
460 totalCommittedInsts
461 .name(name() + ".committedInsts_total")
462 .desc("Number of Instructions Simulated");
463
464 cpi
465 .name(name() + ".cpi")
466 .desc("CPI: Cycles Per Instruction")
467 .precision(6);
468 cpi = numCycles / committedInsts;
469
470 totalCpi
471 .name(name() + ".cpi_total")
472 .desc("CPI: Total CPI of All Threads")
473 .precision(6);
474 totalCpi = numCycles / totalCommittedInsts;
475
476 ipc
477 .name(name() + ".ipc")
478 .desc("IPC: Instructions Per Cycle")
479 .precision(6);
480 ipc = committedInsts / numCycles;
481
482 totalIpc
483 .name(name() + ".ipc_total")
484 .desc("IPC: Total IPC of All Threads")
485 .precision(6);
486 totalIpc = totalCommittedInsts / numCycles;
487
488 this->fetch.regStats();
489 this->decode.regStats();
490 this->rename.regStats();
491 this->iew.regStats();
492 this->commit.regStats();
493 this->rob.regStats();
494
495 intRegfileReads
496 .name(name() + ".int_regfile_reads")
497 .desc("number of integer regfile reads")
498 .prereq(intRegfileReads);
499
500 intRegfileWrites
501 .name(name() + ".int_regfile_writes")
502 .desc("number of integer regfile writes")
503 .prereq(intRegfileWrites);
504
505 fpRegfileReads
506 .name(name() + ".fp_regfile_reads")
507 .desc("number of floating regfile reads")
508 .prereq(fpRegfileReads);
509
510 fpRegfileWrites
511 .name(name() + ".fp_regfile_writes")
512 .desc("number of floating regfile writes")
513 .prereq(fpRegfileWrites);
514
515 miscRegfileReads
516 .name(name() + ".misc_regfile_reads")
517 .desc("number of misc regfile reads")
518 .prereq(miscRegfileReads);
519
520 miscRegfileWrites
521 .name(name() + ".misc_regfile_writes")
522 .desc("number of misc regfile writes")
523 .prereq(miscRegfileWrites);
524}
525
526template <class Impl>
527Port *
528FullO3CPU<Impl>::getPort(const std::string &if_name, int idx)
529{
530 if (if_name == "dcache_port")
| 273#if FULL_SYSTEM
274 checker->setSystem(params->system);
275#endif
276 } else {
277 checker = NULL;
278 }
279#endif // USE_CHECKER
280
281#if !FULL_SYSTEM
282 thread.resize(numThreads);
283 tids.resize(numThreads);
284#endif
285
286 // The stages also need their CPU pointer setup. However this
287 // must be done at the upper level CPU because they have pointers
288 // to the upper level CPU, and not this FullO3CPU.
289
290 // Set up Pointers to the activeThreads list for each stage
291 fetch.setActiveThreads(&activeThreads);
292 decode.setActiveThreads(&activeThreads);
293 rename.setActiveThreads(&activeThreads);
294 iew.setActiveThreads(&activeThreads);
295 commit.setActiveThreads(&activeThreads);
296
297 // Give each of the stages the time buffer they will use.
298 fetch.setTimeBuffer(&timeBuffer);
299 decode.setTimeBuffer(&timeBuffer);
300 rename.setTimeBuffer(&timeBuffer);
301 iew.setTimeBuffer(&timeBuffer);
302 commit.setTimeBuffer(&timeBuffer);
303
304 // Also setup each of the stages' queues.
305 fetch.setFetchQueue(&fetchQueue);
306 decode.setFetchQueue(&fetchQueue);
307 commit.setFetchQueue(&fetchQueue);
308 decode.setDecodeQueue(&decodeQueue);
309 rename.setDecodeQueue(&decodeQueue);
310 rename.setRenameQueue(&renameQueue);
311 iew.setRenameQueue(&renameQueue);
312 iew.setIEWQueue(&iewQueue);
313 commit.setIEWQueue(&iewQueue);
314 commit.setRenameQueue(&renameQueue);
315
316 commit.setIEWStage(&iew);
317 rename.setIEWStage(&iew);
318 rename.setCommitStage(&commit);
319
320#if !FULL_SYSTEM
321 ThreadID active_threads = params->workload.size();
322
323 if (active_threads > Impl::MaxThreads) {
324 panic("Workload Size too large. Increase the 'MaxThreads'"
325 "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or "
326 "edit your workload size.");
327 }
328#else
329 ThreadID active_threads = 1;
330#endif
331
332 //Make Sure That this a Valid Architeture
333 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs);
334 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
335
336 rename.setScoreboard(&scoreboard);
337 iew.setScoreboard(&scoreboard);
338
339 // Setup the rename map for whichever stages need it.
340 PhysRegIndex lreg_idx = 0;
341 PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs
342
343 for (ThreadID tid = 0; tid < numThreads; tid++) {
344 bool bindRegs = (tid <= active_threads - 1);
345
346 commitRenameMap[tid].init(TheISA::NumIntRegs,
347 params->numPhysIntRegs,
348 lreg_idx, //Index for Logical. Regs
349
350 TheISA::NumFloatRegs,
351 params->numPhysFloatRegs,
352 freg_idx, //Index for Float Regs
353
354 TheISA::NumMiscRegs,
355
356 TheISA::ZeroReg,
357 TheISA::ZeroReg,
358
359 tid,
360 false);
361
362 renameMap[tid].init(TheISA::NumIntRegs,
363 params->numPhysIntRegs,
364 lreg_idx, //Index for Logical. Regs
365
366 TheISA::NumFloatRegs,
367 params->numPhysFloatRegs,
368 freg_idx, //Index for Float Regs
369
370 TheISA::NumMiscRegs,
371
372 TheISA::ZeroReg,
373 TheISA::ZeroReg,
374
375 tid,
376 bindRegs);
377
378 activateThreadEvent[tid].init(tid, this);
379 deallocateContextEvent[tid].init(tid, this);
380 }
381
382 rename.setRenameMap(renameMap);
383 commit.setRenameMap(commitRenameMap);
384
385 // Give renameMap & rename stage access to the freeList;
386 for (ThreadID tid = 0; tid < numThreads; tid++)
387 renameMap[tid].setFreeList(&freeList);
388 rename.setFreeList(&freeList);
389
390 // Setup the ROB for whichever stages need it.
391 commit.setROB(&rob);
392
393 lastRunningCycle = curTick();
394
395 lastActivatedCycle = -1;
396#if 0
397 // Give renameMap & rename stage access to the freeList;
398 for (ThreadID tid = 0; tid < numThreads; tid++)
399 globalSeqNum[tid] = 1;
400#endif
401
402 contextSwitch = false;
403 DPRINTF(O3CPU, "Creating O3CPU object.\n");
404
405 // Setup any thread state.
406 this->thread.resize(this->numThreads);
407
408 for (ThreadID tid = 0; tid < this->numThreads; ++tid) {
409#if FULL_SYSTEM
410 // SMT is not supported in FS mode yet.
411 assert(this->numThreads == 1);
412 this->thread[tid] = new Thread(this, 0);
413#else
414 if (tid < params->workload.size()) {
415 DPRINTF(O3CPU, "Workload[%i] process is %#x",
416 tid, this->thread[tid]);
417 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
418 (typename Impl::O3CPU *)(this),
419 tid, params->workload[tid]);
420
421 //usedTids[tid] = true;
422 //threadMap[tid] = tid;
423 } else {
424 //Allocate Empty thread so M5 can use later
425 //when scheduling threads to CPU
426 Process* dummy_proc = NULL;
427
428 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
429 (typename Impl::O3CPU *)(this),
430 tid, dummy_proc);
431 //usedTids[tid] = false;
432 }
433#endif // !FULL_SYSTEM
434
435 ThreadContext *tc;
436
437 // Setup the TC that will serve as the interface to the threads/CPU.
438 O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>;
439
440 tc = o3_tc;
441
442 // If we're using a checker, then the TC should be the
443 // CheckerThreadContext.
444#if USE_CHECKER
445 if (params->checker) {
446 tc = new CheckerThreadContext<O3ThreadContext<Impl> >(
447 o3_tc, this->checker);
448 }
449#endif
450
451 o3_tc->cpu = (typename Impl::O3CPU *)(this);
452 assert(o3_tc->cpu);
453 o3_tc->thread = this->thread[tid];
454
455#if FULL_SYSTEM
456 // Setup quiesce event.
457 this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
458#endif
459 // Give the thread the TC.
460 this->thread[tid]->tc = tc;
461
462 // Add the TC to the CPU's list of TC's.
463 this->threadContexts.push_back(tc);
464 }
465
466 for (ThreadID tid = 0; tid < this->numThreads; tid++)
467 this->thread[tid]->setFuncExeInst(0);
468
469 lockAddr = 0;
470 lockFlag = false;
471}
472
473template <class Impl>
474FullO3CPU<Impl>::~FullO3CPU()
475{
476}
477
478template <class Impl>
479void
480FullO3CPU<Impl>::regStats()
481{
482 BaseO3CPU::regStats();
483
484 // Register any of the O3CPU's stats here.
485 timesIdled
486 .name(name() + ".timesIdled")
487 .desc("Number of times that the entire CPU went into an idle state and"
488 " unscheduled itself")
489 .prereq(timesIdled);
490
491 idleCycles
492 .name(name() + ".idleCycles")
493 .desc("Total number of cycles that the CPU has spent unscheduled due "
494 "to idling")
495 .prereq(idleCycles);
496
497 quiesceCycles
498 .name(name() + ".quiesceCycles")
499 .desc("Total number of cycles that CPU has spent quiesced or waiting "
500 "for an interrupt")
501 .prereq(quiesceCycles);
502
503 // Number of Instructions simulated
504 // --------------------------------
505 // Should probably be in Base CPU but need templated
506 // MaxThreads so put in here instead
507 committedInsts
508 .init(numThreads)
509 .name(name() + ".committedInsts")
510 .desc("Number of Instructions Simulated");
511
512 totalCommittedInsts
513 .name(name() + ".committedInsts_total")
514 .desc("Number of Instructions Simulated");
515
516 cpi
517 .name(name() + ".cpi")
518 .desc("CPI: Cycles Per Instruction")
519 .precision(6);
520 cpi = numCycles / committedInsts;
521
522 totalCpi
523 .name(name() + ".cpi_total")
524 .desc("CPI: Total CPI of All Threads")
525 .precision(6);
526 totalCpi = numCycles / totalCommittedInsts;
527
528 ipc
529 .name(name() + ".ipc")
530 .desc("IPC: Instructions Per Cycle")
531 .precision(6);
532 ipc = committedInsts / numCycles;
533
534 totalIpc
535 .name(name() + ".ipc_total")
536 .desc("IPC: Total IPC of All Threads")
537 .precision(6);
538 totalIpc = totalCommittedInsts / numCycles;
539
540 this->fetch.regStats();
541 this->decode.regStats();
542 this->rename.regStats();
543 this->iew.regStats();
544 this->commit.regStats();
545 this->rob.regStats();
546
547 intRegfileReads
548 .name(name() + ".int_regfile_reads")
549 .desc("number of integer regfile reads")
550 .prereq(intRegfileReads);
551
552 intRegfileWrites
553 .name(name() + ".int_regfile_writes")
554 .desc("number of integer regfile writes")
555 .prereq(intRegfileWrites);
556
557 fpRegfileReads
558 .name(name() + ".fp_regfile_reads")
559 .desc("number of floating regfile reads")
560 .prereq(fpRegfileReads);
561
562 fpRegfileWrites
563 .name(name() + ".fp_regfile_writes")
564 .desc("number of floating regfile writes")
565 .prereq(fpRegfileWrites);
566
567 miscRegfileReads
568 .name(name() + ".misc_regfile_reads")
569 .desc("number of misc regfile reads")
570 .prereq(miscRegfileReads);
571
572 miscRegfileWrites
573 .name(name() + ".misc_regfile_writes")
574 .desc("number of misc regfile writes")
575 .prereq(miscRegfileWrites);
576}
577
578template <class Impl>
579Port *
580FullO3CPU<Impl>::getPort(const std::string &if_name, int idx)
581{
582 if (if_name == "dcache_port")
|
531 return iew.getDcachePort();
| 583 return &dcachePort;
|
532 else if (if_name == "icache_port")
| 584 else if (if_name == "icache_port")
|
533 return fetch.getIcachePort();
| 585 return &icachePort;
|
534 else
535 panic("No Such Port\n");
536}
537
538template <class Impl>
539void
540FullO3CPU<Impl>::tick()
541{
542 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
543
544 ++numCycles;
545
546// activity = false;
547
548 //Tick each of the stages
549 fetch.tick();
550
551 decode.tick();
552
553 rename.tick();
554
555 iew.tick();
556
557 commit.tick();
558
559#if !FULL_SYSTEM
560 doContextSwitch();
561#endif
562
563 // Now advance the time buffers
564 timeBuffer.advance();
565
566 fetchQueue.advance();
567 decodeQueue.advance();
568 renameQueue.advance();
569 iewQueue.advance();
570
571 activityRec.advance();
572
573 if (removeInstsThisCycle) {
574 cleanUpRemovedInsts();
575 }
576
577 if (!tickEvent.scheduled()) {
578 if (_status == SwitchedOut ||
579 getState() == SimObject::Drained) {
580 DPRINTF(O3CPU, "Switched out!\n");
581 // increment stat
582 lastRunningCycle = curTick();
583 } else if (!activityRec.active() || _status == Idle) {
584 DPRINTF(O3CPU, "Idle!\n");
585 lastRunningCycle = curTick();
586 timesIdled++;
587 } else {
588 schedule(tickEvent, nextCycle(curTick() + ticks(1)));
589 DPRINTF(O3CPU, "Scheduling next tick!\n");
590 }
591 }
592
593#if !FULL_SYSTEM
594 updateThreadPriority();
595#endif
596}
597
598template <class Impl>
599void
600FullO3CPU<Impl>::init()
601{
602 BaseCPU::init();
603
604 // Set inSyscall so that the CPU doesn't squash when initially
605 // setting up registers.
606 for (ThreadID tid = 0; tid < numThreads; ++tid)
607 thread[tid]->inSyscall = true;
608
| 586 else
587 panic("No Such Port\n");
588}
589
590template <class Impl>
591void
592FullO3CPU<Impl>::tick()
593{
594 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
595
596 ++numCycles;
597
598// activity = false;
599
600 //Tick each of the stages
601 fetch.tick();
602
603 decode.tick();
604
605 rename.tick();
606
607 iew.tick();
608
609 commit.tick();
610
611#if !FULL_SYSTEM
612 doContextSwitch();
613#endif
614
615 // Now advance the time buffers
616 timeBuffer.advance();
617
618 fetchQueue.advance();
619 decodeQueue.advance();
620 renameQueue.advance();
621 iewQueue.advance();
622
623 activityRec.advance();
624
625 if (removeInstsThisCycle) {
626 cleanUpRemovedInsts();
627 }
628
629 if (!tickEvent.scheduled()) {
630 if (_status == SwitchedOut ||
631 getState() == SimObject::Drained) {
632 DPRINTF(O3CPU, "Switched out!\n");
633 // increment stat
634 lastRunningCycle = curTick();
635 } else if (!activityRec.active() || _status == Idle) {
636 DPRINTF(O3CPU, "Idle!\n");
637 lastRunningCycle = curTick();
638 timesIdled++;
639 } else {
640 schedule(tickEvent, nextCycle(curTick() + ticks(1)));
641 DPRINTF(O3CPU, "Scheduling next tick!\n");
642 }
643 }
644
645#if !FULL_SYSTEM
646 updateThreadPriority();
647#endif
648}
649
650template <class Impl>
651void
652FullO3CPU<Impl>::init()
653{
654 BaseCPU::init();
655
656 // Set inSyscall so that the CPU doesn't squash when initially
657 // setting up registers.
658 for (ThreadID tid = 0; tid < numThreads; ++tid)
659 thread[tid]->inSyscall = true;
660
|
| 661 // this CPU could still be unconnected if we are restoring from a
662 // checkpoint and this CPU is to be switched in, thus we can only
663 // do this here if the instruction port is actually connected, if
664 // not we have to do it as part of takeOverFrom
665 if (icachePort.isConnected())
666 fetch.setIcache();
667
|
609#if FULL_SYSTEM
610 for (ThreadID tid = 0; tid < numThreads; tid++) {
611 ThreadContext *src_tc = threadContexts[tid];
612 TheISA::initCPU(src_tc, src_tc->contextId());
613 // Initialise the ThreadContext's memory proxies
614 thread[tid]->initMemProxies(thread[tid]->getTC());
615 }
616#endif
617
618 // Clear inSyscall.
619 for (int tid = 0; tid < numThreads; ++tid)
620 thread[tid]->inSyscall = false;
621
622 // Initialize stages.
623 fetch.initStage();
624 iew.initStage();
625 rename.initStage();
626 commit.initStage();
627
628 commit.setThreads(thread);
629}
630
631template <class Impl>
632void
633FullO3CPU<Impl>::activateThread(ThreadID tid)
634{
635 list<ThreadID>::iterator isActive =
636 std::find(activeThreads.begin(), activeThreads.end(), tid);
637
638 DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid);
639
640 if (isActive == activeThreads.end()) {
641 DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n",
642 tid);
643
644 activeThreads.push_back(tid);
645 }
646}
647
648template <class Impl>
649void
650FullO3CPU<Impl>::deactivateThread(ThreadID tid)
651{
652 //Remove From Active List, if Active
653 list<ThreadID>::iterator thread_it =
654 std::find(activeThreads.begin(), activeThreads.end(), tid);
655
656 DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid);
657
658 if (thread_it != activeThreads.end()) {
659 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
660 tid);
661 activeThreads.erase(thread_it);
662 }
663}
664
665template <class Impl>
666Counter
667FullO3CPU<Impl>::totalInstructions() const
668{
669 Counter total(0);
670
671 ThreadID size = thread.size();
672 for (ThreadID i = 0; i < size; i++)
673 total += thread[i]->numInst;
674
675 return total;
676}
677
678template <class Impl>
679void
680FullO3CPU<Impl>::activateContext(ThreadID tid, int delay)
681{
682 // Needs to set each stage to running as well.
683 if (delay){
684 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate "
685 "on cycle %d\n", tid, curTick() + ticks(delay));
686 scheduleActivateThreadEvent(tid, delay);
687 } else {
688 activateThread(tid);
689 }
690
691 if (lastActivatedCycle < curTick()) {
692 scheduleTickEvent(delay);
693
694 // Be sure to signal that there's some activity so the CPU doesn't
695 // deschedule itself.
696 activityRec.activity();
697 fetch.wakeFromQuiesce();
698
699 quiesceCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
700
701 lastActivatedCycle = curTick();
702
703 _status = Running;
704 }
705}
706
707template <class Impl>
708bool
709FullO3CPU<Impl>::deallocateContext(ThreadID tid, bool remove, int delay)
710{
711 // Schedule removal of thread data from CPU
712 if (delay){
713 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate "
714 "on cycle %d\n", tid, curTick() + ticks(delay));
715 scheduleDeallocateContextEvent(tid, remove, delay);
716 return false;
717 } else {
718 deactivateThread(tid);
719 if (remove)
720 removeThread(tid);
721 return true;
722 }
723}
724
725template <class Impl>
726void
727FullO3CPU<Impl>::suspendContext(ThreadID tid)
728{
729 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
730 bool deallocated = deallocateContext(tid, false, 1);
731 // If this was the last thread then unschedule the tick event.
732 if ((activeThreads.size() == 1 && !deallocated) ||
733 activeThreads.size() == 0)
734 unscheduleTickEvent();
735
736 DPRINTF(Quiesce, "Suspending Context\n");
737 lastRunningCycle = curTick();
738 _status = Idle;
739}
740
741template <class Impl>
742void
743FullO3CPU<Impl>::haltContext(ThreadID tid)
744{
745 //For now, this is the same as deallocate
746 DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
747 deallocateContext(tid, true, 1);
748}
749
750template <class Impl>
751void
752FullO3CPU<Impl>::insertThread(ThreadID tid)
753{
754 DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
755 // Will change now that the PC and thread state is internal to the CPU
756 // and not in the ThreadContext.
757#if FULL_SYSTEM
758 ThreadContext *src_tc = system->threadContexts[tid];
759#else
760 ThreadContext *src_tc = tcBase(tid);
761#endif
762
763 //Bind Int Regs to Rename Map
764 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
765 PhysRegIndex phys_reg = freeList.getIntReg();
766
767 renameMap[tid].setEntry(ireg,phys_reg);
768 scoreboard.setReg(phys_reg);
769 }
770
771 //Bind Float Regs to Rename Map
772 for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
773 PhysRegIndex phys_reg = freeList.getFloatReg();
774
775 renameMap[tid].setEntry(freg,phys_reg);
776 scoreboard.setReg(phys_reg);
777 }
778
779 //Copy Thread Data Into RegFile
780 //this->copyFromTC(tid);
781
782 //Set PC/NPC/NNPC
783 pcState(src_tc->pcState(), tid);
784
785 src_tc->setStatus(ThreadContext::Active);
786
787 activateContext(tid,1);
788
789 //Reset ROB/IQ/LSQ Entries
790 commit.rob->resetEntries();
791 iew.resetEntries();
792}
793
794template <class Impl>
795void
796FullO3CPU<Impl>::removeThread(ThreadID tid)
797{
798 DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
799
800 // Copy Thread Data From RegFile
801 // If thread is suspended, it might be re-allocated
802 // this->copyToTC(tid);
803
804
805 // @todo: 2-27-2008: Fix how we free up rename mappings
806 // here to alleviate the case for double-freeing registers
807 // in SMT workloads.
808
809 // Unbind Int Regs from Rename Map
810 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
811 PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
812
813 scoreboard.unsetReg(phys_reg);
814 freeList.addReg(phys_reg);
815 }
816
817 // Unbind Float Regs from Rename Map
818 for (int freg = TheISA::NumIntRegs; freg < TheISA::NumFloatRegs; freg++) {
819 PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
820
821 scoreboard.unsetReg(phys_reg);
822 freeList.addReg(phys_reg);
823 }
824
825 // Squash Throughout Pipeline
826 DynInstPtr inst = commit.rob->readHeadInst(tid);
827 InstSeqNum squash_seq_num = inst->seqNum;
828 fetch.squash(0, squash_seq_num, inst, tid);
829 decode.squash(tid);
830 rename.squash(squash_seq_num, tid);
831 iew.squash(tid);
832 iew.ldstQueue.squash(squash_seq_num, tid);
833 commit.rob->squash(squash_seq_num, tid);
834
835
836 assert(iew.instQueue.getCount(tid) == 0);
837 assert(iew.ldstQueue.getCount(tid) == 0);
838
839 // Reset ROB/IQ/LSQ Entries
840
841 // Commented out for now. This should be possible to do by
842 // telling all the pipeline stages to drain first, and then
843 // checking until the drain completes. Once the pipeline is
844 // drained, call resetEntries(). - 10-09-06 ktlim
845/*
846 if (activeThreads.size() >= 1) {
847 commit.rob->resetEntries();
848 iew.resetEntries();
849 }
850*/
851}
852
853
854template <class Impl>
855void
856FullO3CPU<Impl>::activateWhenReady(ThreadID tid)
857{
858 DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming"
859 "(e.g. PhysRegs/ROB/IQ/LSQ) \n",
860 tid);
861
862 bool ready = true;
863
864 if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) {
865 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
866 "Phys. Int. Regs.\n",
867 tid);
868 ready = false;
869 } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) {
870 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
871 "Phys. Float. Regs.\n",
872 tid);
873 ready = false;
874 } else if (commit.rob->numFreeEntries() >=
875 commit.rob->entryAmount(activeThreads.size() + 1)) {
876 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
877 "ROB entries.\n",
878 tid);
879 ready = false;
880 } else if (iew.instQueue.numFreeEntries() >=
881 iew.instQueue.entryAmount(activeThreads.size() + 1)) {
882 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
883 "IQ entries.\n",
884 tid);
885 ready = false;
886 } else if (iew.ldstQueue.numFreeEntries() >=
887 iew.ldstQueue.entryAmount(activeThreads.size() + 1)) {
888 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
889 "LSQ entries.\n",
890 tid);
891 ready = false;
892 }
893
894 if (ready) {
895 insertThread(tid);
896
897 contextSwitch = false;
898
899 cpuWaitList.remove(tid);
900 } else {
901 suspendContext(tid);
902
903 //blocks fetch
904 contextSwitch = true;
905
906 //@todo: dont always add to waitlist
907 //do waitlist
908 cpuWaitList.push_back(tid);
909 }
910}
911
912#if FULL_SYSTEM
913template <class Impl>
914Fault
915FullO3CPU<Impl>::hwrei(ThreadID tid)
916{
917#if THE_ISA == ALPHA_ISA
918 // Need to clear the lock flag upon returning from an interrupt.
919 this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
920
921 this->thread[tid]->kernelStats->hwrei();
922
923 // FIXME: XXX check for interrupts? XXX
924#endif
925 return NoFault;
926}
927
928template <class Impl>
929bool
930FullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid)
931{
932#if THE_ISA == ALPHA_ISA
933 if (this->thread[tid]->kernelStats)
934 this->thread[tid]->kernelStats->callpal(palFunc,
935 this->threadContexts[tid]);
936
937 switch (palFunc) {
938 case PAL::halt:
939 halt();
940 if (--System::numSystemsRunning == 0)
941 exitSimLoop("all cpus halted");
942 break;
943
944 case PAL::bpt:
945 case PAL::bugchk:
946 if (this->system->breakpoint())
947 return false;
948 break;
949 }
950#endif
951 return true;
952}
953
954template <class Impl>
955Fault
956FullO3CPU<Impl>::getInterrupts()
957{
958 // Check if there are any outstanding interrupts
959 return this->interrupts->getInterrupt(this->threadContexts[0]);
960}
961
962template <class Impl>
963void
964FullO3CPU<Impl>::processInterrupts(Fault interrupt)
965{
966 // Check for interrupts here. For now can copy the code that
967 // exists within isa_fullsys_traits.hh. Also assume that thread 0
968 // is the one that handles the interrupts.
969 // @todo: Possibly consolidate the interrupt checking code.
970 // @todo: Allow other threads to handle interrupts.
971
972 assert(interrupt != NoFault);
973 this->interrupts->updateIntrInfo(this->threadContexts[0]);
974
975 DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
976 this->trap(interrupt, 0, NULL);
977}
978
979#endif
980
981template <class Impl>
982void
983FullO3CPU<Impl>::trap(Fault fault, ThreadID tid, StaticInstPtr inst)
984{
985 // Pass the thread's TC into the invoke method.
986 fault->invoke(this->threadContexts[tid], inst);
987}
988
989#if !FULL_SYSTEM
990
991template <class Impl>
992void
993FullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid)
994{
995 DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid);
996
997 DPRINTF(Activity,"Activity: syscall() called.\n");
998
999 // Temporarily increase this by one to account for the syscall
1000 // instruction.
1001 ++(this->thread[tid]->funcExeInst);
1002
1003 // Execute the actual syscall.
1004 this->thread[tid]->syscall(callnum);
1005
1006 // Decrease funcExeInst by one as the normal commit will handle
1007 // incrementing it.
1008 --(this->thread[tid]->funcExeInst);
1009}
1010
1011#endif
1012
1013template <class Impl>
1014void
1015FullO3CPU<Impl>::serialize(std::ostream &os)
1016{
1017 SimObject::State so_state = SimObject::getState();
1018 SERIALIZE_ENUM(so_state);
1019 BaseCPU::serialize(os);
1020 nameOut(os, csprintf("%s.tickEvent", name()));
1021 tickEvent.serialize(os);
1022
1023 // Use SimpleThread's ability to checkpoint to make it easier to
1024 // write out the registers. Also make this static so it doesn't
1025 // get instantiated multiple times (causes a panic in statistics).
1026 static SimpleThread temp;
1027
1028 ThreadID size = thread.size();
1029 for (ThreadID i = 0; i < size; i++) {
1030 nameOut(os, csprintf("%s.xc.%i", name(), i));
1031 temp.copyTC(thread[i]->getTC());
1032 temp.serialize(os);
1033 }
1034}
1035
1036template <class Impl>
1037void
1038FullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion)
1039{
1040 SimObject::State so_state;
1041 UNSERIALIZE_ENUM(so_state);
1042 BaseCPU::unserialize(cp, section);
1043 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
1044
1045 // Use SimpleThread's ability to checkpoint to make it easier to
1046 // read in the registers. Also make this static so it doesn't
1047 // get instantiated multiple times (causes a panic in statistics).
1048 static SimpleThread temp;
1049
1050 ThreadID size = thread.size();
1051 for (ThreadID i = 0; i < size; i++) {
1052 temp.copyTC(thread[i]->getTC());
1053 temp.unserialize(cp, csprintf("%s.xc.%i", section, i));
1054 thread[i]->getTC()->copyArchRegs(temp.getTC());
1055 }
1056}
1057
1058template <class Impl>
1059unsigned int
1060FullO3CPU<Impl>::drain(Event *drain_event)
1061{
1062 DPRINTF(O3CPU, "Switching out\n");
1063
1064 // If the CPU isn't doing anything, then return immediately.
1065 if (_status == Idle || _status == SwitchedOut) {
1066 return 0;
1067 }
1068
1069 drainCount = 0;
1070 fetch.drain();
1071 decode.drain();
1072 rename.drain();
1073 iew.drain();
1074 commit.drain();
1075
1076 // Wake the CPU and record activity so everything can drain out if
1077 // the CPU was not able to immediately drain.
1078 if (getState() != SimObject::Drained) {
1079 // A bit of a hack...set the drainEvent after all the drain()
1080 // calls have been made, that way if all of the stages drain
1081 // immediately, the signalDrained() function knows not to call
1082 // process on the drain event.
1083 drainEvent = drain_event;
1084
1085 wakeCPU();
1086 activityRec.activity();
1087
1088 return 1;
1089 } else {
1090 return 0;
1091 }
1092}
1093
1094template <class Impl>
1095void
1096FullO3CPU<Impl>::resume()
1097{
1098 fetch.resume();
1099 decode.resume();
1100 rename.resume();
1101 iew.resume();
1102 commit.resume();
1103
1104 changeState(SimObject::Running);
1105
1106 if (_status == SwitchedOut || _status == Idle)
1107 return;
1108
1109 assert(system->getMemoryMode() == Enums::timing);
1110
1111 if (!tickEvent.scheduled())
1112 schedule(tickEvent, nextCycle());
1113 _status = Running;
1114}
1115
1116template <class Impl>
1117void
1118FullO3CPU<Impl>::signalDrained()
1119{
1120 if (++drainCount == NumStages) {
1121 if (tickEvent.scheduled())
1122 tickEvent.squash();
1123
1124 changeState(SimObject::Drained);
1125
1126 BaseCPU::switchOut();
1127
1128 if (drainEvent) {
1129 drainEvent->process();
1130 drainEvent = NULL;
1131 }
1132 }
1133 assert(drainCount <= 5);
1134}
1135
1136template <class Impl>
1137void
1138FullO3CPU<Impl>::switchOut()
1139{
1140 fetch.switchOut();
1141 rename.switchOut();
1142 iew.switchOut();
1143 commit.switchOut();
1144 instList.clear();
1145 while (!removeList.empty()) {
1146 removeList.pop();
1147 }
1148
1149 _status = SwitchedOut;
1150#if USE_CHECKER
1151 if (checker)
1152 checker->switchOut();
1153#endif
1154 if (tickEvent.scheduled())
1155 tickEvent.squash();
1156}
1157
1158template <class Impl>
1159void
1160FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
1161{
1162 // Flush out any old data from the time buffers.
1163 for (int i = 0; i < timeBuffer.getSize(); ++i) {
1164 timeBuffer.advance();
1165 fetchQueue.advance();
1166 decodeQueue.advance();
1167 renameQueue.advance();
1168 iewQueue.advance();
1169 }
1170
1171 activityRec.reset();
1172
| 668#if FULL_SYSTEM
669 for (ThreadID tid = 0; tid < numThreads; tid++) {
670 ThreadContext *src_tc = threadContexts[tid];
671 TheISA::initCPU(src_tc, src_tc->contextId());
672 // Initialise the ThreadContext's memory proxies
673 thread[tid]->initMemProxies(thread[tid]->getTC());
674 }
675#endif
676
677 // Clear inSyscall.
678 for (int tid = 0; tid < numThreads; ++tid)
679 thread[tid]->inSyscall = false;
680
681 // Initialize stages.
682 fetch.initStage();
683 iew.initStage();
684 rename.initStage();
685 commit.initStage();
686
687 commit.setThreads(thread);
688}
689
690template <class Impl>
691void
692FullO3CPU<Impl>::activateThread(ThreadID tid)
693{
694 list<ThreadID>::iterator isActive =
695 std::find(activeThreads.begin(), activeThreads.end(), tid);
696
697 DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid);
698
699 if (isActive == activeThreads.end()) {
700 DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n",
701 tid);
702
703 activeThreads.push_back(tid);
704 }
705}
706
707template <class Impl>
708void
709FullO3CPU<Impl>::deactivateThread(ThreadID tid)
710{
711 //Remove From Active List, if Active
712 list<ThreadID>::iterator thread_it =
713 std::find(activeThreads.begin(), activeThreads.end(), tid);
714
715 DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid);
716
717 if (thread_it != activeThreads.end()) {
718 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
719 tid);
720 activeThreads.erase(thread_it);
721 }
722}
723
724template <class Impl>
725Counter
726FullO3CPU<Impl>::totalInstructions() const
727{
728 Counter total(0);
729
730 ThreadID size = thread.size();
731 for (ThreadID i = 0; i < size; i++)
732 total += thread[i]->numInst;
733
734 return total;
735}
736
737template <class Impl>
738void
739FullO3CPU<Impl>::activateContext(ThreadID tid, int delay)
740{
741 // Needs to set each stage to running as well.
742 if (delay){
743 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate "
744 "on cycle %d\n", tid, curTick() + ticks(delay));
745 scheduleActivateThreadEvent(tid, delay);
746 } else {
747 activateThread(tid);
748 }
749
750 if (lastActivatedCycle < curTick()) {
751 scheduleTickEvent(delay);
752
753 // Be sure to signal that there's some activity so the CPU doesn't
754 // deschedule itself.
755 activityRec.activity();
756 fetch.wakeFromQuiesce();
757
758 quiesceCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
759
760 lastActivatedCycle = curTick();
761
762 _status = Running;
763 }
764}
765
766template <class Impl>
767bool
768FullO3CPU<Impl>::deallocateContext(ThreadID tid, bool remove, int delay)
769{
770 // Schedule removal of thread data from CPU
771 if (delay){
772 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate "
773 "on cycle %d\n", tid, curTick() + ticks(delay));
774 scheduleDeallocateContextEvent(tid, remove, delay);
775 return false;
776 } else {
777 deactivateThread(tid);
778 if (remove)
779 removeThread(tid);
780 return true;
781 }
782}
783
784template <class Impl>
785void
786FullO3CPU<Impl>::suspendContext(ThreadID tid)
787{
788 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
789 bool deallocated = deallocateContext(tid, false, 1);
790 // If this was the last thread then unschedule the tick event.
791 if ((activeThreads.size() == 1 && !deallocated) ||
792 activeThreads.size() == 0)
793 unscheduleTickEvent();
794
795 DPRINTF(Quiesce, "Suspending Context\n");
796 lastRunningCycle = curTick();
797 _status = Idle;
798}
799
800template <class Impl>
801void
802FullO3CPU<Impl>::haltContext(ThreadID tid)
803{
804 //For now, this is the same as deallocate
805 DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
806 deallocateContext(tid, true, 1);
807}
808
809template <class Impl>
810void
811FullO3CPU<Impl>::insertThread(ThreadID tid)
812{
813 DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
814 // Will change now that the PC and thread state is internal to the CPU
815 // and not in the ThreadContext.
816#if FULL_SYSTEM
817 ThreadContext *src_tc = system->threadContexts[tid];
818#else
819 ThreadContext *src_tc = tcBase(tid);
820#endif
821
822 //Bind Int Regs to Rename Map
823 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
824 PhysRegIndex phys_reg = freeList.getIntReg();
825
826 renameMap[tid].setEntry(ireg,phys_reg);
827 scoreboard.setReg(phys_reg);
828 }
829
830 //Bind Float Regs to Rename Map
831 for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
832 PhysRegIndex phys_reg = freeList.getFloatReg();
833
834 renameMap[tid].setEntry(freg,phys_reg);
835 scoreboard.setReg(phys_reg);
836 }
837
838 //Copy Thread Data Into RegFile
839 //this->copyFromTC(tid);
840
841 //Set PC/NPC/NNPC
842 pcState(src_tc->pcState(), tid);
843
844 src_tc->setStatus(ThreadContext::Active);
845
846 activateContext(tid,1);
847
848 //Reset ROB/IQ/LSQ Entries
849 commit.rob->resetEntries();
850 iew.resetEntries();
851}
852
853template <class Impl>
854void
855FullO3CPU<Impl>::removeThread(ThreadID tid)
856{
857 DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
858
859 // Copy Thread Data From RegFile
860 // If thread is suspended, it might be re-allocated
861 // this->copyToTC(tid);
862
863
864 // @todo: 2-27-2008: Fix how we free up rename mappings
865 // here to alleviate the case for double-freeing registers
866 // in SMT workloads.
867
868 // Unbind Int Regs from Rename Map
869 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
870 PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
871
872 scoreboard.unsetReg(phys_reg);
873 freeList.addReg(phys_reg);
874 }
875
876 // Unbind Float Regs from Rename Map
877 for (int freg = TheISA::NumIntRegs; freg < TheISA::NumFloatRegs; freg++) {
878 PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
879
880 scoreboard.unsetReg(phys_reg);
881 freeList.addReg(phys_reg);
882 }
883
884 // Squash Throughout Pipeline
885 DynInstPtr inst = commit.rob->readHeadInst(tid);
886 InstSeqNum squash_seq_num = inst->seqNum;
887 fetch.squash(0, squash_seq_num, inst, tid);
888 decode.squash(tid);
889 rename.squash(squash_seq_num, tid);
890 iew.squash(tid);
891 iew.ldstQueue.squash(squash_seq_num, tid);
892 commit.rob->squash(squash_seq_num, tid);
893
894
895 assert(iew.instQueue.getCount(tid) == 0);
896 assert(iew.ldstQueue.getCount(tid) == 0);
897
898 // Reset ROB/IQ/LSQ Entries
899
900 // Commented out for now. This should be possible to do by
901 // telling all the pipeline stages to drain first, and then
902 // checking until the drain completes. Once the pipeline is
903 // drained, call resetEntries(). - 10-09-06 ktlim
904/*
905 if (activeThreads.size() >= 1) {
906 commit.rob->resetEntries();
907 iew.resetEntries();
908 }
909*/
910}
911
912
913template <class Impl>
914void
915FullO3CPU<Impl>::activateWhenReady(ThreadID tid)
916{
917 DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming"
918 "(e.g. PhysRegs/ROB/IQ/LSQ) \n",
919 tid);
920
921 bool ready = true;
922
923 if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) {
924 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
925 "Phys. Int. Regs.\n",
926 tid);
927 ready = false;
928 } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) {
929 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
930 "Phys. Float. Regs.\n",
931 tid);
932 ready = false;
933 } else if (commit.rob->numFreeEntries() >=
934 commit.rob->entryAmount(activeThreads.size() + 1)) {
935 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
936 "ROB entries.\n",
937 tid);
938 ready = false;
939 } else if (iew.instQueue.numFreeEntries() >=
940 iew.instQueue.entryAmount(activeThreads.size() + 1)) {
941 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
942 "IQ entries.\n",
943 tid);
944 ready = false;
945 } else if (iew.ldstQueue.numFreeEntries() >=
946 iew.ldstQueue.entryAmount(activeThreads.size() + 1)) {
947 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
948 "LSQ entries.\n",
949 tid);
950 ready = false;
951 }
952
953 if (ready) {
954 insertThread(tid);
955
956 contextSwitch = false;
957
958 cpuWaitList.remove(tid);
959 } else {
960 suspendContext(tid);
961
962 //blocks fetch
963 contextSwitch = true;
964
965 //@todo: dont always add to waitlist
966 //do waitlist
967 cpuWaitList.push_back(tid);
968 }
969}
970
971#if FULL_SYSTEM
972template <class Impl>
973Fault
974FullO3CPU<Impl>::hwrei(ThreadID tid)
975{
976#if THE_ISA == ALPHA_ISA
977 // Need to clear the lock flag upon returning from an interrupt.
978 this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
979
980 this->thread[tid]->kernelStats->hwrei();
981
982 // FIXME: XXX check for interrupts? XXX
983#endif
984 return NoFault;
985}
986
987template <class Impl>
988bool
989FullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid)
990{
991#if THE_ISA == ALPHA_ISA
992 if (this->thread[tid]->kernelStats)
993 this->thread[tid]->kernelStats->callpal(palFunc,
994 this->threadContexts[tid]);
995
996 switch (palFunc) {
997 case PAL::halt:
998 halt();
999 if (--System::numSystemsRunning == 0)
1000 exitSimLoop("all cpus halted");
1001 break;
1002
1003 case PAL::bpt:
1004 case PAL::bugchk:
1005 if (this->system->breakpoint())
1006 return false;
1007 break;
1008 }
1009#endif
1010 return true;
1011}
1012
1013template <class Impl>
1014Fault
1015FullO3CPU<Impl>::getInterrupts()
1016{
1017 // Check if there are any outstanding interrupts
1018 return this->interrupts->getInterrupt(this->threadContexts[0]);
1019}
1020
1021template <class Impl>
1022void
1023FullO3CPU<Impl>::processInterrupts(Fault interrupt)
1024{
1025 // Check for interrupts here. For now can copy the code that
1026 // exists within isa_fullsys_traits.hh. Also assume that thread 0
1027 // is the one that handles the interrupts.
1028 // @todo: Possibly consolidate the interrupt checking code.
1029 // @todo: Allow other threads to handle interrupts.
1030
1031 assert(interrupt != NoFault);
1032 this->interrupts->updateIntrInfo(this->threadContexts[0]);
1033
1034 DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
1035 this->trap(interrupt, 0, NULL);
1036}
1037
1038#endif
1039
1040template <class Impl>
1041void
1042FullO3CPU<Impl>::trap(Fault fault, ThreadID tid, StaticInstPtr inst)
1043{
1044 // Pass the thread's TC into the invoke method.
1045 fault->invoke(this->threadContexts[tid], inst);
1046}
1047
1048#if !FULL_SYSTEM
1049
1050template <class Impl>
1051void
1052FullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid)
1053{
1054 DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid);
1055
1056 DPRINTF(Activity,"Activity: syscall() called.\n");
1057
1058 // Temporarily increase this by one to account for the syscall
1059 // instruction.
1060 ++(this->thread[tid]->funcExeInst);
1061
1062 // Execute the actual syscall.
1063 this->thread[tid]->syscall(callnum);
1064
1065 // Decrease funcExeInst by one as the normal commit will handle
1066 // incrementing it.
1067 --(this->thread[tid]->funcExeInst);
1068}
1069
1070#endif
1071
1072template <class Impl>
1073void
1074FullO3CPU<Impl>::serialize(std::ostream &os)
1075{
1076 SimObject::State so_state = SimObject::getState();
1077 SERIALIZE_ENUM(so_state);
1078 BaseCPU::serialize(os);
1079 nameOut(os, csprintf("%s.tickEvent", name()));
1080 tickEvent.serialize(os);
1081
1082 // Use SimpleThread's ability to checkpoint to make it easier to
1083 // write out the registers. Also make this static so it doesn't
1084 // get instantiated multiple times (causes a panic in statistics).
1085 static SimpleThread temp;
1086
1087 ThreadID size = thread.size();
1088 for (ThreadID i = 0; i < size; i++) {
1089 nameOut(os, csprintf("%s.xc.%i", name(), i));
1090 temp.copyTC(thread[i]->getTC());
1091 temp.serialize(os);
1092 }
1093}
1094
1095template <class Impl>
1096void
1097FullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion)
1098{
1099 SimObject::State so_state;
1100 UNSERIALIZE_ENUM(so_state);
1101 BaseCPU::unserialize(cp, section);
1102 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
1103
1104 // Use SimpleThread's ability to checkpoint to make it easier to
1105 // read in the registers. Also make this static so it doesn't
1106 // get instantiated multiple times (causes a panic in statistics).
1107 static SimpleThread temp;
1108
1109 ThreadID size = thread.size();
1110 for (ThreadID i = 0; i < size; i++) {
1111 temp.copyTC(thread[i]->getTC());
1112 temp.unserialize(cp, csprintf("%s.xc.%i", section, i));
1113 thread[i]->getTC()->copyArchRegs(temp.getTC());
1114 }
1115}
1116
1117template <class Impl>
1118unsigned int
1119FullO3CPU<Impl>::drain(Event *drain_event)
1120{
1121 DPRINTF(O3CPU, "Switching out\n");
1122
1123 // If the CPU isn't doing anything, then return immediately.
1124 if (_status == Idle || _status == SwitchedOut) {
1125 return 0;
1126 }
1127
1128 drainCount = 0;
1129 fetch.drain();
1130 decode.drain();
1131 rename.drain();
1132 iew.drain();
1133 commit.drain();
1134
1135 // Wake the CPU and record activity so everything can drain out if
1136 // the CPU was not able to immediately drain.
1137 if (getState() != SimObject::Drained) {
1138 // A bit of a hack...set the drainEvent after all the drain()
1139 // calls have been made, that way if all of the stages drain
1140 // immediately, the signalDrained() function knows not to call
1141 // process on the drain event.
1142 drainEvent = drain_event;
1143
1144 wakeCPU();
1145 activityRec.activity();
1146
1147 return 1;
1148 } else {
1149 return 0;
1150 }
1151}
1152
1153template <class Impl>
1154void
1155FullO3CPU<Impl>::resume()
1156{
1157 fetch.resume();
1158 decode.resume();
1159 rename.resume();
1160 iew.resume();
1161 commit.resume();
1162
1163 changeState(SimObject::Running);
1164
1165 if (_status == SwitchedOut || _status == Idle)
1166 return;
1167
1168 assert(system->getMemoryMode() == Enums::timing);
1169
1170 if (!tickEvent.scheduled())
1171 schedule(tickEvent, nextCycle());
1172 _status = Running;
1173}
1174
1175template <class Impl>
1176void
1177FullO3CPU<Impl>::signalDrained()
1178{
1179 if (++drainCount == NumStages) {
1180 if (tickEvent.scheduled())
1181 tickEvent.squash();
1182
1183 changeState(SimObject::Drained);
1184
1185 BaseCPU::switchOut();
1186
1187 if (drainEvent) {
1188 drainEvent->process();
1189 drainEvent = NULL;
1190 }
1191 }
1192 assert(drainCount <= 5);
1193}
1194
1195template <class Impl>
1196void
1197FullO3CPU<Impl>::switchOut()
1198{
1199 fetch.switchOut();
1200 rename.switchOut();
1201 iew.switchOut();
1202 commit.switchOut();
1203 instList.clear();
1204 while (!removeList.empty()) {
1205 removeList.pop();
1206 }
1207
1208 _status = SwitchedOut;
1209#if USE_CHECKER
1210 if (checker)
1211 checker->switchOut();
1212#endif
1213 if (tickEvent.scheduled())
1214 tickEvent.squash();
1215}
1216
1217template <class Impl>
1218void
1219FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
1220{
1221 // Flush out any old data from the time buffers.
1222 for (int i = 0; i < timeBuffer.getSize(); ++i) {
1223 timeBuffer.advance();
1224 fetchQueue.advance();
1225 decodeQueue.advance();
1226 renameQueue.advance();
1227 iewQueue.advance();
1228 }
1229
1230 activityRec.reset();
1231
|
1173 BaseCPU::takeOverFrom(oldCPU, fetch.getIcachePort(), iew.getDcachePort());
| 1232 BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort);
|
1174
1175 fetch.takeOverFrom();
1176 decode.takeOverFrom();
1177 rename.takeOverFrom();
1178 iew.takeOverFrom();
1179 commit.takeOverFrom();
1180
1181 assert(!tickEvent.scheduled() || tickEvent.squashed());
1182
1183 // @todo: Figure out how to properly select the tid to put onto
1184 // the active threads list.
1185 ThreadID tid = 0;
1186
1187 list<ThreadID>::iterator isActive =
1188 std::find(activeThreads.begin(), activeThreads.end(), tid);
1189
1190 if (isActive == activeThreads.end()) {
1191 //May Need to Re-code this if the delay variable is the delay
1192 //needed for thread to activate
1193 DPRINTF(O3CPU, "Adding Thread %i to active threads list\n",
1194 tid);
1195
1196 activeThreads.push_back(tid);
1197 }
1198
1199 // Set all statuses to active, schedule the CPU's tick event.
1200 // @todo: Fix up statuses so this is handled properly
1201 ThreadID size = threadContexts.size();
1202 for (ThreadID i = 0; i < size; ++i) {
1203 ThreadContext *tc = threadContexts[i];
1204 if (tc->status() == ThreadContext::Active && _status != Running) {
1205 _status = Running;
1206 reschedule(tickEvent, nextCycle(), true);
1207 }
1208 }
1209 if (!tickEvent.scheduled())
1210 schedule(tickEvent, nextCycle());
1211
1212 lastRunningCycle = curTick();
1213}
1214
1215template <class Impl>
1216TheISA::MiscReg
1217FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid)
1218{
1219 return this->isa[tid].readMiscRegNoEffect(misc_reg);
1220}
1221
1222template <class Impl>
1223TheISA::MiscReg
1224FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
1225{
1226 miscRegfileReads++;
1227 return this->isa[tid].readMiscReg(misc_reg, tcBase(tid));
1228}
1229
1230template <class Impl>
1231void
1232FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
1233 const TheISA::MiscReg &val, ThreadID tid)
1234{
1235 this->isa[tid].setMiscRegNoEffect(misc_reg, val);
1236}
1237
1238template <class Impl>
1239void
1240FullO3CPU<Impl>::setMiscReg(int misc_reg,
1241 const TheISA::MiscReg &val, ThreadID tid)
1242{
1243 miscRegfileWrites++;
1244 this->isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
1245}
1246
1247template <class Impl>
1248uint64_t
1249FullO3CPU<Impl>::readIntReg(int reg_idx)
1250{
1251 intRegfileReads++;
1252 return regFile.readIntReg(reg_idx);
1253}
1254
1255template <class Impl>
1256FloatReg
1257FullO3CPU<Impl>::readFloatReg(int reg_idx)
1258{
1259 fpRegfileReads++;
1260 return regFile.readFloatReg(reg_idx);
1261}
1262
1263template <class Impl>
1264FloatRegBits
1265FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
1266{
1267 fpRegfileReads++;
1268 return regFile.readFloatRegBits(reg_idx);
1269}
1270
1271template <class Impl>
1272void
1273FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
1274{
1275 intRegfileWrites++;
1276 regFile.setIntReg(reg_idx, val);
1277}
1278
1279template <class Impl>
1280void
1281FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
1282{
1283 fpRegfileWrites++;
1284 regFile.setFloatReg(reg_idx, val);
1285}
1286
1287template <class Impl>
1288void
1289FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
1290{
1291 fpRegfileWrites++;
1292 regFile.setFloatRegBits(reg_idx, val);
1293}
1294
1295template <class Impl>
1296uint64_t
1297FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1298{
1299 intRegfileReads++;
1300 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1301
1302 return regFile.readIntReg(phys_reg);
1303}
1304
1305template <class Impl>
1306float
1307FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
1308{
1309 fpRegfileReads++;
1310 int idx = reg_idx + TheISA::NumIntRegs;
1311 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1312
1313 return regFile.readFloatReg(phys_reg);
1314}
1315
1316template <class Impl>
1317uint64_t
1318FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid)
1319{
1320 fpRegfileReads++;
1321 int idx = reg_idx + TheISA::NumIntRegs;
1322 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1323
1324 return regFile.readFloatRegBits(phys_reg);
1325}
1326
1327template <class Impl>
1328void
1329FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
1330{
1331 intRegfileWrites++;
1332 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1333
1334 regFile.setIntReg(phys_reg, val);
1335}
1336
1337template <class Impl>
1338void
1339FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid)
1340{
1341 fpRegfileWrites++;
1342 int idx = reg_idx + TheISA::NumIntRegs;
1343 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1344
1345 regFile.setFloatReg(phys_reg, val);
1346}
1347
1348template <class Impl>
1349void
1350FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid)
1351{
1352 fpRegfileWrites++;
1353 int idx = reg_idx + TheISA::NumIntRegs;
1354 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1355
1356 regFile.setFloatRegBits(phys_reg, val);
1357}
1358
1359template <class Impl>
1360TheISA::PCState
1361FullO3CPU<Impl>::pcState(ThreadID tid)
1362{
1363 return commit.pcState(tid);
1364}
1365
1366template <class Impl>
1367void
1368FullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid)
1369{
1370 commit.pcState(val, tid);
1371}
1372
1373template <class Impl>
1374Addr
1375FullO3CPU<Impl>::instAddr(ThreadID tid)
1376{
1377 return commit.instAddr(tid);
1378}
1379
1380template <class Impl>
1381Addr
1382FullO3CPU<Impl>::nextInstAddr(ThreadID tid)
1383{
1384 return commit.nextInstAddr(tid);
1385}
1386
1387template <class Impl>
1388MicroPC
1389FullO3CPU<Impl>::microPC(ThreadID tid)
1390{
1391 return commit.microPC(tid);
1392}
1393
1394template <class Impl>
1395void
1396FullO3CPU<Impl>::squashFromTC(ThreadID tid)
1397{
1398 this->thread[tid]->inSyscall = true;
1399 this->commit.generateTCEvent(tid);
1400}
1401
1402template <class Impl>
1403typename FullO3CPU<Impl>::ListIt
1404FullO3CPU<Impl>::addInst(DynInstPtr &inst)
1405{
1406 instList.push_back(inst);
1407
1408 return --(instList.end());
1409}
1410
1411template <class Impl>
1412void
1413FullO3CPU<Impl>::instDone(ThreadID tid)
1414{
1415 // Keep an instruction count.
1416 thread[tid]->numInst++;
1417 thread[tid]->numInsts++;
1418 committedInsts[tid]++;
1419 totalCommittedInsts++;
1420 system->totalNumInsts++;
1421 // Check for instruction-count-based events.
1422 comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1423 system->instEventQueue.serviceEvents(system->totalNumInsts);
1424}
1425
1426template <class Impl>
1427void
1428FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
1429{
1430 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s "
1431 "[sn:%lli]\n",
1432 inst->threadNumber, inst->pcState(), inst->seqNum);
1433
1434 removeInstsThisCycle = true;
1435
1436 // Remove the front instruction.
1437 removeList.push(inst->getInstListIt());
1438}
1439
1440template <class Impl>
1441void
1442FullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid)
1443{
1444 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1445 " list.\n", tid);
1446
1447 ListIt end_it;
1448
1449 bool rob_empty = false;
1450
1451 if (instList.empty()) {
1452 return;
1453 } else if (rob.isEmpty(/*tid*/)) {
1454 DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1455 end_it = instList.begin();
1456 rob_empty = true;
1457 } else {
1458 end_it = (rob.readTailInst(tid))->getInstListIt();
1459 DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1460 }
1461
1462 removeInstsThisCycle = true;
1463
1464 ListIt inst_it = instList.end();
1465
1466 inst_it--;
1467
1468 // Walk through the instruction list, removing any instructions
1469 // that were inserted after the given instruction iterator, end_it.
1470 while (inst_it != end_it) {
1471 assert(!instList.empty());
1472
1473 squashInstIt(inst_it, tid);
1474
1475 inst_it--;
1476 }
1477
1478 // If the ROB was empty, then we actually need to remove the first
1479 // instruction as well.
1480 if (rob_empty) {
1481 squashInstIt(inst_it, tid);
1482 }
1483}
1484
1485template <class Impl>
1486void
1487FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1488{
1489 assert(!instList.empty());
1490
1491 removeInstsThisCycle = true;
1492
1493 ListIt inst_iter = instList.end();
1494
1495 inst_iter--;
1496
1497 DPRINTF(O3CPU, "Deleting instructions from instruction "
1498 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1499 tid, seq_num, (*inst_iter)->seqNum);
1500
1501 while ((*inst_iter)->seqNum > seq_num) {
1502
1503 bool break_loop = (inst_iter == instList.begin());
1504
1505 squashInstIt(inst_iter, tid);
1506
1507 inst_iter--;
1508
1509 if (break_loop)
1510 break;
1511 }
1512}
1513
1514template <class Impl>
1515inline void
1516FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid)
1517{
1518 if ((*instIt)->threadNumber == tid) {
1519 DPRINTF(O3CPU, "Squashing instruction, "
1520 "[tid:%i] [sn:%lli] PC %s\n",
1521 (*instIt)->threadNumber,
1522 (*instIt)->seqNum,
1523 (*instIt)->pcState());
1524
1525 // Mark it as squashed.
1526 (*instIt)->setSquashed();
1527
1528 // @todo: Formulate a consistent method for deleting
1529 // instructions from the instruction list
1530 // Remove the instruction from the list.
1531 removeList.push(instIt);
1532 }
1533}
1534
1535template <class Impl>
1536void
1537FullO3CPU<Impl>::cleanUpRemovedInsts()
1538{
1539 while (!removeList.empty()) {
1540 DPRINTF(O3CPU, "Removing instruction, "
1541 "[tid:%i] [sn:%lli] PC %s\n",
1542 (*removeList.front())->threadNumber,
1543 (*removeList.front())->seqNum,
1544 (*removeList.front())->pcState());
1545
1546 instList.erase(removeList.front());
1547
1548 removeList.pop();
1549 }
1550
1551 removeInstsThisCycle = false;
1552}
1553/*
1554template <class Impl>
1555void
1556FullO3CPU<Impl>::removeAllInsts()
1557{
1558 instList.clear();
1559}
1560*/
1561template <class Impl>
1562void
1563FullO3CPU<Impl>::dumpInsts()
1564{
1565 int num = 0;
1566
1567 ListIt inst_list_it = instList.begin();
1568
1569 cprintf("Dumping Instruction List\n");
1570
1571 while (inst_list_it != instList.end()) {
1572 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1573 "Squashed:%i\n\n",
1574 num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber,
1575 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1576 (*inst_list_it)->isSquashed());
1577 inst_list_it++;
1578 ++num;
1579 }
1580}
1581/*
1582template <class Impl>
1583void
1584FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
1585{
1586 iew.wakeDependents(inst);
1587}
1588*/
1589template <class Impl>
1590void
1591FullO3CPU<Impl>::wakeCPU()
1592{
1593 if (activityRec.active() || tickEvent.scheduled()) {
1594 DPRINTF(Activity, "CPU already running.\n");
1595 return;
1596 }
1597
1598 DPRINTF(Activity, "Waking up CPU\n");
1599
1600 idleCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
1601 numCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
1602
1603 schedule(tickEvent, nextCycle());
1604}
1605
1606#if FULL_SYSTEM
1607template <class Impl>
1608void
1609FullO3CPU<Impl>::wakeup()
1610{
1611 if (this->thread[0]->status() != ThreadContext::Suspended)
1612 return;
1613
1614 this->wakeCPU();
1615
1616 DPRINTF(Quiesce, "Suspended Processor woken\n");
1617 this->threadContexts[0]->activate();
1618}
1619#endif
1620
1621template <class Impl>
1622ThreadID
1623FullO3CPU<Impl>::getFreeTid()
1624{
1625 for (ThreadID tid = 0; tid < numThreads; tid++) {
1626 if (!tids[tid]) {
1627 tids[tid] = true;
1628 return tid;
1629 }
1630 }
1631
1632 return InvalidThreadID;
1633}
1634
1635template <class Impl>
1636void
1637FullO3CPU<Impl>::doContextSwitch()
1638{
1639 if (contextSwitch) {
1640
1641 //ADD CODE TO DEACTIVE THREAD HERE (???)
1642
1643 ThreadID size = cpuWaitList.size();
1644 for (ThreadID tid = 0; tid < size; tid++) {
1645 activateWhenReady(tid);
1646 }
1647
1648 if (cpuWaitList.size() == 0)
1649 contextSwitch = true;
1650 }
1651}
1652
1653template <class Impl>
1654void
1655FullO3CPU<Impl>::updateThreadPriority()
1656{
1657 if (activeThreads.size() > 1) {
1658 //DEFAULT TO ROUND ROBIN SCHEME
1659 //e.g. Move highest priority to end of thread list
1660 list<ThreadID>::iterator list_begin = activeThreads.begin();
1661
1662 unsigned high_thread = *list_begin;
1663
1664 activeThreads.erase(list_begin);
1665
1666 activeThreads.push_back(high_thread);
1667 }
1668}
1669
1670// Forward declaration of FullO3CPU.
1671template class FullO3CPU<O3CPUImpl>;
| 1233
1234 fetch.takeOverFrom();
1235 decode.takeOverFrom();
1236 rename.takeOverFrom();
1237 iew.takeOverFrom();
1238 commit.takeOverFrom();
1239
1240 assert(!tickEvent.scheduled() || tickEvent.squashed());
1241
1242 // @todo: Figure out how to properly select the tid to put onto
1243 // the active threads list.
1244 ThreadID tid = 0;
1245
1246 list<ThreadID>::iterator isActive =
1247 std::find(activeThreads.begin(), activeThreads.end(), tid);
1248
1249 if (isActive == activeThreads.end()) {
1250 //May Need to Re-code this if the delay variable is the delay
1251 //needed for thread to activate
1252 DPRINTF(O3CPU, "Adding Thread %i to active threads list\n",
1253 tid);
1254
1255 activeThreads.push_back(tid);
1256 }
1257
1258 // Set all statuses to active, schedule the CPU's tick event.
1259 // @todo: Fix up statuses so this is handled properly
1260 ThreadID size = threadContexts.size();
1261 for (ThreadID i = 0; i < size; ++i) {
1262 ThreadContext *tc = threadContexts[i];
1263 if (tc->status() == ThreadContext::Active && _status != Running) {
1264 _status = Running;
1265 reschedule(tickEvent, nextCycle(), true);
1266 }
1267 }
1268 if (!tickEvent.scheduled())
1269 schedule(tickEvent, nextCycle());
1270
1271 lastRunningCycle = curTick();
1272}
1273
1274template <class Impl>
1275TheISA::MiscReg
1276FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid)
1277{
1278 return this->isa[tid].readMiscRegNoEffect(misc_reg);
1279}
1280
1281template <class Impl>
1282TheISA::MiscReg
1283FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
1284{
1285 miscRegfileReads++;
1286 return this->isa[tid].readMiscReg(misc_reg, tcBase(tid));
1287}
1288
1289template <class Impl>
1290void
1291FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
1292 const TheISA::MiscReg &val, ThreadID tid)
1293{
1294 this->isa[tid].setMiscRegNoEffect(misc_reg, val);
1295}
1296
1297template <class Impl>
1298void
1299FullO3CPU<Impl>::setMiscReg(int misc_reg,
1300 const TheISA::MiscReg &val, ThreadID tid)
1301{
1302 miscRegfileWrites++;
1303 this->isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
1304}
1305
1306template <class Impl>
1307uint64_t
1308FullO3CPU<Impl>::readIntReg(int reg_idx)
1309{
1310 intRegfileReads++;
1311 return regFile.readIntReg(reg_idx);
1312}
1313
1314template <class Impl>
1315FloatReg
1316FullO3CPU<Impl>::readFloatReg(int reg_idx)
1317{
1318 fpRegfileReads++;
1319 return regFile.readFloatReg(reg_idx);
1320}
1321
1322template <class Impl>
1323FloatRegBits
1324FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
1325{
1326 fpRegfileReads++;
1327 return regFile.readFloatRegBits(reg_idx);
1328}
1329
1330template <class Impl>
1331void
1332FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
1333{
1334 intRegfileWrites++;
1335 regFile.setIntReg(reg_idx, val);
1336}
1337
1338template <class Impl>
1339void
1340FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
1341{
1342 fpRegfileWrites++;
1343 regFile.setFloatReg(reg_idx, val);
1344}
1345
1346template <class Impl>
1347void
1348FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
1349{
1350 fpRegfileWrites++;
1351 regFile.setFloatRegBits(reg_idx, val);
1352}
1353
1354template <class Impl>
1355uint64_t
1356FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1357{
1358 intRegfileReads++;
1359 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1360
1361 return regFile.readIntReg(phys_reg);
1362}
1363
1364template <class Impl>
1365float
1366FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
1367{
1368 fpRegfileReads++;
1369 int idx = reg_idx + TheISA::NumIntRegs;
1370 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1371
1372 return regFile.readFloatReg(phys_reg);
1373}
1374
1375template <class Impl>
1376uint64_t
1377FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid)
1378{
1379 fpRegfileReads++;
1380 int idx = reg_idx + TheISA::NumIntRegs;
1381 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1382
1383 return regFile.readFloatRegBits(phys_reg);
1384}
1385
1386template <class Impl>
1387void
1388FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
1389{
1390 intRegfileWrites++;
1391 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1392
1393 regFile.setIntReg(phys_reg, val);
1394}
1395
1396template <class Impl>
1397void
1398FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid)
1399{
1400 fpRegfileWrites++;
1401 int idx = reg_idx + TheISA::NumIntRegs;
1402 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1403
1404 regFile.setFloatReg(phys_reg, val);
1405}
1406
1407template <class Impl>
1408void
1409FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid)
1410{
1411 fpRegfileWrites++;
1412 int idx = reg_idx + TheISA::NumIntRegs;
1413 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1414
1415 regFile.setFloatRegBits(phys_reg, val);
1416}
1417
1418template <class Impl>
1419TheISA::PCState
1420FullO3CPU<Impl>::pcState(ThreadID tid)
1421{
1422 return commit.pcState(tid);
1423}
1424
1425template <class Impl>
1426void
1427FullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid)
1428{
1429 commit.pcState(val, tid);
1430}
1431
1432template <class Impl>
1433Addr
1434FullO3CPU<Impl>::instAddr(ThreadID tid)
1435{
1436 return commit.instAddr(tid);
1437}
1438
1439template <class Impl>
1440Addr
1441FullO3CPU<Impl>::nextInstAddr(ThreadID tid)
1442{
1443 return commit.nextInstAddr(tid);
1444}
1445
1446template <class Impl>
1447MicroPC
1448FullO3CPU<Impl>::microPC(ThreadID tid)
1449{
1450 return commit.microPC(tid);
1451}
1452
1453template <class Impl>
1454void
1455FullO3CPU<Impl>::squashFromTC(ThreadID tid)
1456{
1457 this->thread[tid]->inSyscall = true;
1458 this->commit.generateTCEvent(tid);
1459}
1460
1461template <class Impl>
1462typename FullO3CPU<Impl>::ListIt
1463FullO3CPU<Impl>::addInst(DynInstPtr &inst)
1464{
1465 instList.push_back(inst);
1466
1467 return --(instList.end());
1468}
1469
1470template <class Impl>
1471void
1472FullO3CPU<Impl>::instDone(ThreadID tid)
1473{
1474 // Keep an instruction count.
1475 thread[tid]->numInst++;
1476 thread[tid]->numInsts++;
1477 committedInsts[tid]++;
1478 totalCommittedInsts++;
1479 system->totalNumInsts++;
1480 // Check for instruction-count-based events.
1481 comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1482 system->instEventQueue.serviceEvents(system->totalNumInsts);
1483}
1484
1485template <class Impl>
1486void
1487FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
1488{
1489 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s "
1490 "[sn:%lli]\n",
1491 inst->threadNumber, inst->pcState(), inst->seqNum);
1492
1493 removeInstsThisCycle = true;
1494
1495 // Remove the front instruction.
1496 removeList.push(inst->getInstListIt());
1497}
1498
1499template <class Impl>
1500void
1501FullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid)
1502{
1503 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1504 " list.\n", tid);
1505
1506 ListIt end_it;
1507
1508 bool rob_empty = false;
1509
1510 if (instList.empty()) {
1511 return;
1512 } else if (rob.isEmpty(/*tid*/)) {
1513 DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1514 end_it = instList.begin();
1515 rob_empty = true;
1516 } else {
1517 end_it = (rob.readTailInst(tid))->getInstListIt();
1518 DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1519 }
1520
1521 removeInstsThisCycle = true;
1522
1523 ListIt inst_it = instList.end();
1524
1525 inst_it--;
1526
1527 // Walk through the instruction list, removing any instructions
1528 // that were inserted after the given instruction iterator, end_it.
1529 while (inst_it != end_it) {
1530 assert(!instList.empty());
1531
1532 squashInstIt(inst_it, tid);
1533
1534 inst_it--;
1535 }
1536
1537 // If the ROB was empty, then we actually need to remove the first
1538 // instruction as well.
1539 if (rob_empty) {
1540 squashInstIt(inst_it, tid);
1541 }
1542}
1543
1544template <class Impl>
1545void
1546FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1547{
1548 assert(!instList.empty());
1549
1550 removeInstsThisCycle = true;
1551
1552 ListIt inst_iter = instList.end();
1553
1554 inst_iter--;
1555
1556 DPRINTF(O3CPU, "Deleting instructions from instruction "
1557 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1558 tid, seq_num, (*inst_iter)->seqNum);
1559
1560 while ((*inst_iter)->seqNum > seq_num) {
1561
1562 bool break_loop = (inst_iter == instList.begin());
1563
1564 squashInstIt(inst_iter, tid);
1565
1566 inst_iter--;
1567
1568 if (break_loop)
1569 break;
1570 }
1571}
1572
1573template <class Impl>
1574inline void
1575FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid)
1576{
1577 if ((*instIt)->threadNumber == tid) {
1578 DPRINTF(O3CPU, "Squashing instruction, "
1579 "[tid:%i] [sn:%lli] PC %s\n",
1580 (*instIt)->threadNumber,
1581 (*instIt)->seqNum,
1582 (*instIt)->pcState());
1583
1584 // Mark it as squashed.
1585 (*instIt)->setSquashed();
1586
1587 // @todo: Formulate a consistent method for deleting
1588 // instructions from the instruction list
1589 // Remove the instruction from the list.
1590 removeList.push(instIt);
1591 }
1592}
1593
1594template <class Impl>
1595void
1596FullO3CPU<Impl>::cleanUpRemovedInsts()
1597{
1598 while (!removeList.empty()) {
1599 DPRINTF(O3CPU, "Removing instruction, "
1600 "[tid:%i] [sn:%lli] PC %s\n",
1601 (*removeList.front())->threadNumber,
1602 (*removeList.front())->seqNum,
1603 (*removeList.front())->pcState());
1604
1605 instList.erase(removeList.front());
1606
1607 removeList.pop();
1608 }
1609
1610 removeInstsThisCycle = false;
1611}
1612/*
1613template <class Impl>
1614void
1615FullO3CPU<Impl>::removeAllInsts()
1616{
1617 instList.clear();
1618}
1619*/
1620template <class Impl>
1621void
1622FullO3CPU<Impl>::dumpInsts()
1623{
1624 int num = 0;
1625
1626 ListIt inst_list_it = instList.begin();
1627
1628 cprintf("Dumping Instruction List\n");
1629
1630 while (inst_list_it != instList.end()) {
1631 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1632 "Squashed:%i\n\n",
1633 num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber,
1634 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1635 (*inst_list_it)->isSquashed());
1636 inst_list_it++;
1637 ++num;
1638 }
1639}
1640/*
1641template <class Impl>
1642void
1643FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
1644{
1645 iew.wakeDependents(inst);
1646}
1647*/
1648template <class Impl>
1649void
1650FullO3CPU<Impl>::wakeCPU()
1651{
1652 if (activityRec.active() || tickEvent.scheduled()) {
1653 DPRINTF(Activity, "CPU already running.\n");
1654 return;
1655 }
1656
1657 DPRINTF(Activity, "Waking up CPU\n");
1658
1659 idleCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
1660 numCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
1661
1662 schedule(tickEvent, nextCycle());
1663}
1664
1665#if FULL_SYSTEM
1666template <class Impl>
1667void
1668FullO3CPU<Impl>::wakeup()
1669{
1670 if (this->thread[0]->status() != ThreadContext::Suspended)
1671 return;
1672
1673 this->wakeCPU();
1674
1675 DPRINTF(Quiesce, "Suspended Processor woken\n");
1676 this->threadContexts[0]->activate();
1677}
1678#endif
1679
1680template <class Impl>
1681ThreadID
1682FullO3CPU<Impl>::getFreeTid()
1683{
1684 for (ThreadID tid = 0; tid < numThreads; tid++) {
1685 if (!tids[tid]) {
1686 tids[tid] = true;
1687 return tid;
1688 }
1689 }
1690
1691 return InvalidThreadID;
1692}
1693
1694template <class Impl>
1695void
1696FullO3CPU<Impl>::doContextSwitch()
1697{
1698 if (contextSwitch) {
1699
1700 //ADD CODE TO DEACTIVE THREAD HERE (???)
1701
1702 ThreadID size = cpuWaitList.size();
1703 for (ThreadID tid = 0; tid < size; tid++) {
1704 activateWhenReady(tid);
1705 }
1706
1707 if (cpuWaitList.size() == 0)
1708 contextSwitch = true;
1709 }
1710}
1711
1712template <class Impl>
1713void
1714FullO3CPU<Impl>::updateThreadPriority()
1715{
1716 if (activeThreads.size() > 1) {
1717 //DEFAULT TO ROUND ROBIN SCHEME
1718 //e.g. Move highest priority to end of thread list
1719 list<ThreadID>::iterator list_begin = activeThreads.begin();
1720
1721 unsigned high_thread = *list_begin;
1722
1723 activeThreads.erase(list_begin);
1724
1725 activeThreads.push_back(high_thread);
1726 }
1727}
1728
1729// Forward declaration of FullO3CPU.
1730template class FullO3CPU<O3CPUImpl>;
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