1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * Copyright (c) 2011 Regents of the University of California
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Kevin Lim
30 * Korey Sewell
31 * Rick Strong
32 */
33
34#include "config/full_system.hh"
35#include "config/the_isa.hh"
36#include "config/use_checker.hh"
37#include "cpu/o3/cpu.hh"
38#include "cpu/o3/isa_specific.hh"
39#include "cpu/o3/thread_context.hh"
40#include "cpu/activity.hh"
41#include "cpu/simple_thread.hh"
42#include "cpu/thread_context.hh"
43#include "debug/Activity.hh"
44#include "debug/O3CPU.hh"
45#include "debug/Quiesce.hh"
46#include "enums/MemoryMode.hh"
47#include "sim/core.hh"
48#include "sim/stat_control.hh"
| 1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * Copyright (c) 2011 Regents of the University of California
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Kevin Lim
30 * Korey Sewell
31 * Rick Strong
32 */
33
34#include "config/full_system.hh"
35#include "config/the_isa.hh"
36#include "config/use_checker.hh"
37#include "cpu/o3/cpu.hh"
38#include "cpu/o3/isa_specific.hh"
39#include "cpu/o3/thread_context.hh"
40#include "cpu/activity.hh"
41#include "cpu/simple_thread.hh"
42#include "cpu/thread_context.hh"
43#include "debug/Activity.hh"
44#include "debug/O3CPU.hh"
45#include "debug/Quiesce.hh"
46#include "enums/MemoryMode.hh"
47#include "sim/core.hh"
48#include "sim/stat_control.hh"
|
| 49#include "sim/system.hh"
|
49
50#if FULL_SYSTEM
51#include "cpu/quiesce_event.hh"
| 50
51#if FULL_SYSTEM
52#include "cpu/quiesce_event.hh"
|
52#include "sim/system.hh"
| |
53#else
54#include "sim/process.hh"
55#endif
56
57#if USE_CHECKER
58#include "cpu/checker/cpu.hh"
59#endif
60
61#if THE_ISA == ALPHA_ISA
62#include "arch/alpha/osfpal.hh"
63#include "debug/Activity.hh"
64#endif
65
66class BaseCPUParams;
67
68using namespace TheISA;
69using namespace std;
70
71BaseO3CPU::BaseO3CPU(BaseCPUParams *params)
72 : BaseCPU(params)
73{
74}
75
76void
77BaseO3CPU::regStats()
78{
79 BaseCPU::regStats();
80}
81
82template <class Impl>
83FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
84 : Event(CPU_Tick_Pri), cpu(c)
85{
86}
87
88template <class Impl>
89void
90FullO3CPU<Impl>::TickEvent::process()
91{
92 cpu->tick();
93}
94
95template <class Impl>
96const char *
97FullO3CPU<Impl>::TickEvent::description() const
98{
99 return "FullO3CPU tick";
100}
101
102template <class Impl>
103FullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent()
104 : Event(CPU_Switch_Pri)
105{
106}
107
108template <class Impl>
109void
110FullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num,
111 FullO3CPU<Impl> *thread_cpu)
112{
113 tid = thread_num;
114 cpu = thread_cpu;
115}
116
117template <class Impl>
118void
119FullO3CPU<Impl>::ActivateThreadEvent::process()
120{
121 cpu->activateThread(tid);
122}
123
124template <class Impl>
125const char *
126FullO3CPU<Impl>::ActivateThreadEvent::description() const
127{
128 return "FullO3CPU \"Activate Thread\"";
129}
130
131template <class Impl>
132FullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent()
133 : Event(CPU_Tick_Pri), tid(0), remove(false), cpu(NULL)
134{
135}
136
137template <class Impl>
138void
139FullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num,
140 FullO3CPU<Impl> *thread_cpu)
141{
142 tid = thread_num;
143 cpu = thread_cpu;
144 remove = false;
145}
146
147template <class Impl>
148void
149FullO3CPU<Impl>::DeallocateContextEvent::process()
150{
151 cpu->deactivateThread(tid);
152 if (remove)
153 cpu->removeThread(tid);
154}
155
156template <class Impl>
157const char *
158FullO3CPU<Impl>::DeallocateContextEvent::description() const
159{
160 return "FullO3CPU \"Deallocate Context\"";
161}
162
163template <class Impl>
164FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
165 : BaseO3CPU(params),
166 itb(params->itb),
167 dtb(params->dtb),
168 tickEvent(this),
169#ifndef NDEBUG
170 instcount(0),
171#endif
172 removeInstsThisCycle(false),
173 fetch(this, params),
174 decode(this, params),
175 rename(this, params),
176 iew(this, params),
177 commit(this, params),
178
179 regFile(this, params->numPhysIntRegs,
180 params->numPhysFloatRegs),
181
182 freeList(params->numThreads,
183 TheISA::NumIntRegs, params->numPhysIntRegs,
184 TheISA::NumFloatRegs, params->numPhysFloatRegs),
185
186 rob(this,
187 params->numROBEntries, params->squashWidth,
188 params->smtROBPolicy, params->smtROBThreshold,
189 params->numThreads),
190
191 scoreboard(params->numThreads,
192 TheISA::NumIntRegs, params->numPhysIntRegs,
193 TheISA::NumFloatRegs, params->numPhysFloatRegs,
194 TheISA::NumMiscRegs * numThreads,
195 TheISA::ZeroReg),
196
197 timeBuffer(params->backComSize, params->forwardComSize),
198 fetchQueue(params->backComSize, params->forwardComSize),
199 decodeQueue(params->backComSize, params->forwardComSize),
200 renameQueue(params->backComSize, params->forwardComSize),
201 iewQueue(params->backComSize, params->forwardComSize),
202 activityRec(name(), NumStages,
203 params->backComSize + params->forwardComSize,
204 params->activity),
205
206 globalSeqNum(1),
| 53#else
54#include "sim/process.hh"
55#endif
56
57#if USE_CHECKER
58#include "cpu/checker/cpu.hh"
59#endif
60
61#if THE_ISA == ALPHA_ISA
62#include "arch/alpha/osfpal.hh"
63#include "debug/Activity.hh"
64#endif
65
66class BaseCPUParams;
67
68using namespace TheISA;
69using namespace std;
70
71BaseO3CPU::BaseO3CPU(BaseCPUParams *params)
72 : BaseCPU(params)
73{
74}
75
76void
77BaseO3CPU::regStats()
78{
79 BaseCPU::regStats();
80}
81
82template <class Impl>
83FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
84 : Event(CPU_Tick_Pri), cpu(c)
85{
86}
87
88template <class Impl>
89void
90FullO3CPU<Impl>::TickEvent::process()
91{
92 cpu->tick();
93}
94
95template <class Impl>
96const char *
97FullO3CPU<Impl>::TickEvent::description() const
98{
99 return "FullO3CPU tick";
100}
101
102template <class Impl>
103FullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent()
104 : Event(CPU_Switch_Pri)
105{
106}
107
108template <class Impl>
109void
110FullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num,
111 FullO3CPU<Impl> *thread_cpu)
112{
113 tid = thread_num;
114 cpu = thread_cpu;
115}
116
117template <class Impl>
118void
119FullO3CPU<Impl>::ActivateThreadEvent::process()
120{
121 cpu->activateThread(tid);
122}
123
124template <class Impl>
125const char *
126FullO3CPU<Impl>::ActivateThreadEvent::description() const
127{
128 return "FullO3CPU \"Activate Thread\"";
129}
130
131template <class Impl>
132FullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent()
133 : Event(CPU_Tick_Pri), tid(0), remove(false), cpu(NULL)
134{
135}
136
137template <class Impl>
138void
139FullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num,
140 FullO3CPU<Impl> *thread_cpu)
141{
142 tid = thread_num;
143 cpu = thread_cpu;
144 remove = false;
145}
146
147template <class Impl>
148void
149FullO3CPU<Impl>::DeallocateContextEvent::process()
150{
151 cpu->deactivateThread(tid);
152 if (remove)
153 cpu->removeThread(tid);
154}
155
156template <class Impl>
157const char *
158FullO3CPU<Impl>::DeallocateContextEvent::description() const
159{
160 return "FullO3CPU \"Deallocate Context\"";
161}
162
163template <class Impl>
164FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
165 : BaseO3CPU(params),
166 itb(params->itb),
167 dtb(params->dtb),
168 tickEvent(this),
169#ifndef NDEBUG
170 instcount(0),
171#endif
172 removeInstsThisCycle(false),
173 fetch(this, params),
174 decode(this, params),
175 rename(this, params),
176 iew(this, params),
177 commit(this, params),
178
179 regFile(this, params->numPhysIntRegs,
180 params->numPhysFloatRegs),
181
182 freeList(params->numThreads,
183 TheISA::NumIntRegs, params->numPhysIntRegs,
184 TheISA::NumFloatRegs, params->numPhysFloatRegs),
185
186 rob(this,
187 params->numROBEntries, params->squashWidth,
188 params->smtROBPolicy, params->smtROBThreshold,
189 params->numThreads),
190
191 scoreboard(params->numThreads,
192 TheISA::NumIntRegs, params->numPhysIntRegs,
193 TheISA::NumFloatRegs, params->numPhysFloatRegs,
194 TheISA::NumMiscRegs * numThreads,
195 TheISA::ZeroReg),
196
197 timeBuffer(params->backComSize, params->forwardComSize),
198 fetchQueue(params->backComSize, params->forwardComSize),
199 decodeQueue(params->backComSize, params->forwardComSize),
200 renameQueue(params->backComSize, params->forwardComSize),
201 iewQueue(params->backComSize, params->forwardComSize),
202 activityRec(name(), NumStages,
203 params->backComSize + params->forwardComSize,
204 params->activity),
205
206 globalSeqNum(1),
|
207#if FULL_SYSTEM
| |
208 system(params->system),
| 207 system(params->system),
|
209#endif // FULL_SYSTEM
| |
210 drainCount(0),
211 deferRegistration(params->defer_registration)
212{
213 if (!deferRegistration) {
214 _status = Running;
215 } else {
216 _status = Idle;
217 }
218
219#if USE_CHECKER
220 if (params->checker) {
221 BaseCPU *temp_checker = params->checker;
222 checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
223#if FULL_SYSTEM
224 checker->setSystem(params->system);
225#endif
226 } else {
227 checker = NULL;
228 }
229#endif // USE_CHECKER
230
231#if !FULL_SYSTEM
232 thread.resize(numThreads);
233 tids.resize(numThreads);
234#endif
235
236 // The stages also need their CPU pointer setup. However this
237 // must be done at the upper level CPU because they have pointers
238 // to the upper level CPU, and not this FullO3CPU.
239
240 // Set up Pointers to the activeThreads list for each stage
241 fetch.setActiveThreads(&activeThreads);
242 decode.setActiveThreads(&activeThreads);
243 rename.setActiveThreads(&activeThreads);
244 iew.setActiveThreads(&activeThreads);
245 commit.setActiveThreads(&activeThreads);
246
247 // Give each of the stages the time buffer they will use.
248 fetch.setTimeBuffer(&timeBuffer);
249 decode.setTimeBuffer(&timeBuffer);
250 rename.setTimeBuffer(&timeBuffer);
251 iew.setTimeBuffer(&timeBuffer);
252 commit.setTimeBuffer(&timeBuffer);
253
254 // Also setup each of the stages' queues.
255 fetch.setFetchQueue(&fetchQueue);
256 decode.setFetchQueue(&fetchQueue);
257 commit.setFetchQueue(&fetchQueue);
258 decode.setDecodeQueue(&decodeQueue);
259 rename.setDecodeQueue(&decodeQueue);
260 rename.setRenameQueue(&renameQueue);
261 iew.setRenameQueue(&renameQueue);
262 iew.setIEWQueue(&iewQueue);
263 commit.setIEWQueue(&iewQueue);
264 commit.setRenameQueue(&renameQueue);
265
266 commit.setIEWStage(&iew);
267 rename.setIEWStage(&iew);
268 rename.setCommitStage(&commit);
269
270#if !FULL_SYSTEM
271 ThreadID active_threads = params->workload.size();
272
273 if (active_threads > Impl::MaxThreads) {
274 panic("Workload Size too large. Increase the 'MaxThreads'"
275 "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or "
276 "edit your workload size.");
277 }
278#else
279 ThreadID active_threads = 1;
280#endif
281
282 //Make Sure That this a Valid Architeture
283 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs);
284 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
285
286 rename.setScoreboard(&scoreboard);
287 iew.setScoreboard(&scoreboard);
288
289 // Setup the rename map for whichever stages need it.
290 PhysRegIndex lreg_idx = 0;
291 PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs
292
293 for (ThreadID tid = 0; tid < numThreads; tid++) {
294 bool bindRegs = (tid <= active_threads - 1);
295
296 commitRenameMap[tid].init(TheISA::NumIntRegs,
297 params->numPhysIntRegs,
298 lreg_idx, //Index for Logical. Regs
299
300 TheISA::NumFloatRegs,
301 params->numPhysFloatRegs,
302 freg_idx, //Index for Float Regs
303
304 TheISA::NumMiscRegs,
305
306 TheISA::ZeroReg,
307 TheISA::ZeroReg,
308
309 tid,
310 false);
311
312 renameMap[tid].init(TheISA::NumIntRegs,
313 params->numPhysIntRegs,
314 lreg_idx, //Index for Logical. Regs
315
316 TheISA::NumFloatRegs,
317 params->numPhysFloatRegs,
318 freg_idx, //Index for Float Regs
319
320 TheISA::NumMiscRegs,
321
322 TheISA::ZeroReg,
323 TheISA::ZeroReg,
324
325 tid,
326 bindRegs);
327
328 activateThreadEvent[tid].init(tid, this);
329 deallocateContextEvent[tid].init(tid, this);
330 }
331
332 rename.setRenameMap(renameMap);
333 commit.setRenameMap(commitRenameMap);
334
335 // Give renameMap & rename stage access to the freeList;
336 for (ThreadID tid = 0; tid < numThreads; tid++)
337 renameMap[tid].setFreeList(&freeList);
338 rename.setFreeList(&freeList);
339
340 // Setup the ROB for whichever stages need it.
341 commit.setROB(&rob);
342
343 lastRunningCycle = curTick();
344
345 lastActivatedCycle = -1;
346#if 0
347 // Give renameMap & rename stage access to the freeList;
348 for (ThreadID tid = 0; tid < numThreads; tid++)
349 globalSeqNum[tid] = 1;
350#endif
351
352 contextSwitch = false;
353 DPRINTF(O3CPU, "Creating O3CPU object.\n");
354
355 // Setup any thread state.
356 this->thread.resize(this->numThreads);
357
358 for (ThreadID tid = 0; tid < this->numThreads; ++tid) {
359#if FULL_SYSTEM
360 // SMT is not supported in FS mode yet.
361 assert(this->numThreads == 1);
362 this->thread[tid] = new Thread(this, 0);
363#else
364 if (tid < params->workload.size()) {
365 DPRINTF(O3CPU, "Workload[%i] process is %#x",
366 tid, this->thread[tid]);
367 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
368 (typename Impl::O3CPU *)(this),
369 tid, params->workload[tid]);
370
371 //usedTids[tid] = true;
372 //threadMap[tid] = tid;
373 } else {
374 //Allocate Empty thread so M5 can use later
375 //when scheduling threads to CPU
376 Process* dummy_proc = NULL;
377
378 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
379 (typename Impl::O3CPU *)(this),
380 tid, dummy_proc);
381 //usedTids[tid] = false;
382 }
383#endif // !FULL_SYSTEM
384
385 ThreadContext *tc;
386
387 // Setup the TC that will serve as the interface to the threads/CPU.
388 O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>;
389
390 tc = o3_tc;
391
392 // If we're using a checker, then the TC should be the
393 // CheckerThreadContext.
394#if USE_CHECKER
395 if (params->checker) {
396 tc = new CheckerThreadContext<O3ThreadContext<Impl> >(
397 o3_tc, this->checker);
398 }
399#endif
400
401 o3_tc->cpu = (typename Impl::O3CPU *)(this);
402 assert(o3_tc->cpu);
403 o3_tc->thread = this->thread[tid];
404
405#if FULL_SYSTEM
406 // Setup quiesce event.
407 this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
408#endif
409 // Give the thread the TC.
410 this->thread[tid]->tc = tc;
411
412 // Add the TC to the CPU's list of TC's.
413 this->threadContexts.push_back(tc);
414 }
415
416 for (ThreadID tid = 0; tid < this->numThreads; tid++)
417 this->thread[tid]->setFuncExeInst(0);
418
419 lockAddr = 0;
420 lockFlag = false;
421}
422
423template <class Impl>
424FullO3CPU<Impl>::~FullO3CPU()
425{
426}
427
428template <class Impl>
429void
430FullO3CPU<Impl>::regStats()
431{
432 BaseO3CPU::regStats();
433
434 // Register any of the O3CPU's stats here.
435 timesIdled
436 .name(name() + ".timesIdled")
437 .desc("Number of times that the entire CPU went into an idle state and"
438 " unscheduled itself")
439 .prereq(timesIdled);
440
441 idleCycles
442 .name(name() + ".idleCycles")
443 .desc("Total number of cycles that the CPU has spent unscheduled due "
444 "to idling")
445 .prereq(idleCycles);
446
447 // Number of Instructions simulated
448 // --------------------------------
449 // Should probably be in Base CPU but need templated
450 // MaxThreads so put in here instead
451 committedInsts
452 .init(numThreads)
453 .name(name() + ".committedInsts")
454 .desc("Number of Instructions Simulated");
455
456 totalCommittedInsts
457 .name(name() + ".committedInsts_total")
458 .desc("Number of Instructions Simulated");
459
460 cpi
461 .name(name() + ".cpi")
462 .desc("CPI: Cycles Per Instruction")
463 .precision(6);
464 cpi = numCycles / committedInsts;
465
466 totalCpi
467 .name(name() + ".cpi_total")
468 .desc("CPI: Total CPI of All Threads")
469 .precision(6);
470 totalCpi = numCycles / totalCommittedInsts;
471
472 ipc
473 .name(name() + ".ipc")
474 .desc("IPC: Instructions Per Cycle")
475 .precision(6);
476 ipc = committedInsts / numCycles;
477
478 totalIpc
479 .name(name() + ".ipc_total")
480 .desc("IPC: Total IPC of All Threads")
481 .precision(6);
482 totalIpc = totalCommittedInsts / numCycles;
483
484 this->fetch.regStats();
485 this->decode.regStats();
486 this->rename.regStats();
487 this->iew.regStats();
488 this->commit.regStats();
489 this->rob.regStats();
490
491 intRegfileReads
492 .name(name() + ".int_regfile_reads")
493 .desc("number of integer regfile reads")
494 .prereq(intRegfileReads);
495
496 intRegfileWrites
497 .name(name() + ".int_regfile_writes")
498 .desc("number of integer regfile writes")
499 .prereq(intRegfileWrites);
500
501 fpRegfileReads
502 .name(name() + ".fp_regfile_reads")
503 .desc("number of floating regfile reads")
504 .prereq(fpRegfileReads);
505
506 fpRegfileWrites
507 .name(name() + ".fp_regfile_writes")
508 .desc("number of floating regfile writes")
509 .prereq(fpRegfileWrites);
510
511 miscRegfileReads
512 .name(name() + ".misc_regfile_reads")
513 .desc("number of misc regfile reads")
514 .prereq(miscRegfileReads);
515
516 miscRegfileWrites
517 .name(name() + ".misc_regfile_writes")
518 .desc("number of misc regfile writes")
519 .prereq(miscRegfileWrites);
520}
521
522template <class Impl>
523Port *
524FullO3CPU<Impl>::getPort(const std::string &if_name, int idx)
525{
526 if (if_name == "dcache_port")
527 return iew.getDcachePort();
528 else if (if_name == "icache_port")
529 return fetch.getIcachePort();
530 else
531 panic("No Such Port\n");
532}
533
534template <class Impl>
535void
536FullO3CPU<Impl>::tick()
537{
538 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
539
540 ++numCycles;
541
542// activity = false;
543
544 //Tick each of the stages
545 fetch.tick();
546
547 decode.tick();
548
549 rename.tick();
550
551 iew.tick();
552
553 commit.tick();
554
555#if !FULL_SYSTEM
556 doContextSwitch();
557#endif
558
559 // Now advance the time buffers
560 timeBuffer.advance();
561
562 fetchQueue.advance();
563 decodeQueue.advance();
564 renameQueue.advance();
565 iewQueue.advance();
566
567 activityRec.advance();
568
569 if (removeInstsThisCycle) {
570 cleanUpRemovedInsts();
571 }
572
573 if (!tickEvent.scheduled()) {
574 if (_status == SwitchedOut ||
575 getState() == SimObject::Drained) {
576 DPRINTF(O3CPU, "Switched out!\n");
577 // increment stat
578 lastRunningCycle = curTick();
579 } else if (!activityRec.active() || _status == Idle) {
580 DPRINTF(O3CPU, "Idle!\n");
581 lastRunningCycle = curTick();
582 timesIdled++;
583 } else {
584 schedule(tickEvent, nextCycle(curTick() + ticks(1)));
585 DPRINTF(O3CPU, "Scheduling next tick!\n");
586 }
587 }
588
589#if !FULL_SYSTEM
590 updateThreadPriority();
591#endif
592}
593
594template <class Impl>
595void
596FullO3CPU<Impl>::init()
597{
598 BaseCPU::init();
599
600 // Set inSyscall so that the CPU doesn't squash when initially
601 // setting up registers.
602 for (ThreadID tid = 0; tid < numThreads; ++tid)
603 thread[tid]->inSyscall = true;
604
605#if FULL_SYSTEM
606 for (ThreadID tid = 0; tid < numThreads; tid++) {
607 ThreadContext *src_tc = threadContexts[tid];
608 TheISA::initCPU(src_tc, src_tc->contextId());
609 }
610#endif
611
612 // Clear inSyscall.
613 for (int tid = 0; tid < numThreads; ++tid)
614 thread[tid]->inSyscall = false;
615
616 // Initialize stages.
617 fetch.initStage();
618 iew.initStage();
619 rename.initStage();
620 commit.initStage();
621
622 commit.setThreads(thread);
623}
624
625template <class Impl>
626void
627FullO3CPU<Impl>::activateThread(ThreadID tid)
628{
629 list<ThreadID>::iterator isActive =
630 std::find(activeThreads.begin(), activeThreads.end(), tid);
631
632 DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid);
633
634 if (isActive == activeThreads.end()) {
635 DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n",
636 tid);
637
638 activeThreads.push_back(tid);
639 }
640}
641
642template <class Impl>
643void
644FullO3CPU<Impl>::deactivateThread(ThreadID tid)
645{
646 //Remove From Active List, if Active
647 list<ThreadID>::iterator thread_it =
648 std::find(activeThreads.begin(), activeThreads.end(), tid);
649
650 DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid);
651
652 if (thread_it != activeThreads.end()) {
653 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
654 tid);
655 activeThreads.erase(thread_it);
656 }
657}
658
659template <class Impl>
660Counter
661FullO3CPU<Impl>::totalInstructions() const
662{
663 Counter total(0);
664
665 ThreadID size = thread.size();
666 for (ThreadID i = 0; i < size; i++)
667 total += thread[i]->numInst;
668
669 return total;
670}
671
672template <class Impl>
673void
674FullO3CPU<Impl>::activateContext(ThreadID tid, int delay)
675{
676 // Needs to set each stage to running as well.
677 if (delay){
678 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate "
679 "on cycle %d\n", tid, curTick() + ticks(delay));
680 scheduleActivateThreadEvent(tid, delay);
681 } else {
682 activateThread(tid);
683 }
684
685 if (lastActivatedCycle < curTick()) {
686 scheduleTickEvent(delay);
687
688 // Be sure to signal that there's some activity so the CPU doesn't
689 // deschedule itself.
690 activityRec.activity();
691 fetch.wakeFromQuiesce();
692
693 lastActivatedCycle = curTick();
694
695 _status = Running;
696 }
697}
698
699template <class Impl>
700bool
701FullO3CPU<Impl>::deallocateContext(ThreadID tid, bool remove, int delay)
702{
703 // Schedule removal of thread data from CPU
704 if (delay){
705 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate "
706 "on cycle %d\n", tid, curTick() + ticks(delay));
707 scheduleDeallocateContextEvent(tid, remove, delay);
708 return false;
709 } else {
710 deactivateThread(tid);
711 if (remove)
712 removeThread(tid);
713 return true;
714 }
715}
716
717template <class Impl>
718void
719FullO3CPU<Impl>::suspendContext(ThreadID tid)
720{
721 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
722 bool deallocated = deallocateContext(tid, false, 1);
723 // If this was the last thread then unschedule the tick event.
724 if ((activeThreads.size() == 1 && !deallocated) ||
725 activeThreads.size() == 0)
726 unscheduleTickEvent();
727 _status = Idle;
728}
729
730template <class Impl>
731void
732FullO3CPU<Impl>::haltContext(ThreadID tid)
733{
734 //For now, this is the same as deallocate
735 DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
736 deallocateContext(tid, true, 1);
737}
738
739template <class Impl>
740void
741FullO3CPU<Impl>::insertThread(ThreadID tid)
742{
743 DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
744 // Will change now that the PC and thread state is internal to the CPU
745 // and not in the ThreadContext.
746#if FULL_SYSTEM
747 ThreadContext *src_tc = system->threadContexts[tid];
748#else
749 ThreadContext *src_tc = tcBase(tid);
750#endif
751
752 //Bind Int Regs to Rename Map
753 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
754 PhysRegIndex phys_reg = freeList.getIntReg();
755
756 renameMap[tid].setEntry(ireg,phys_reg);
757 scoreboard.setReg(phys_reg);
758 }
759
760 //Bind Float Regs to Rename Map
761 for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
762 PhysRegIndex phys_reg = freeList.getFloatReg();
763
764 renameMap[tid].setEntry(freg,phys_reg);
765 scoreboard.setReg(phys_reg);
766 }
767
768 //Copy Thread Data Into RegFile
769 //this->copyFromTC(tid);
770
771 //Set PC/NPC/NNPC
772 pcState(src_tc->pcState(), tid);
773
774 src_tc->setStatus(ThreadContext::Active);
775
776 activateContext(tid,1);
777
778 //Reset ROB/IQ/LSQ Entries
779 commit.rob->resetEntries();
780 iew.resetEntries();
781}
782
783template <class Impl>
784void
785FullO3CPU<Impl>::removeThread(ThreadID tid)
786{
787 DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
788
789 // Copy Thread Data From RegFile
790 // If thread is suspended, it might be re-allocated
791 // this->copyToTC(tid);
792
793
794 // @todo: 2-27-2008: Fix how we free up rename mappings
795 // here to alleviate the case for double-freeing registers
796 // in SMT workloads.
797
798 // Unbind Int Regs from Rename Map
799 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
800 PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
801
802 scoreboard.unsetReg(phys_reg);
803 freeList.addReg(phys_reg);
804 }
805
806 // Unbind Float Regs from Rename Map
807 for (int freg = TheISA::NumIntRegs; freg < TheISA::NumFloatRegs; freg++) {
808 PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
809
810 scoreboard.unsetReg(phys_reg);
811 freeList.addReg(phys_reg);
812 }
813
814 // Squash Throughout Pipeline
815 DynInstPtr inst = commit.rob->readHeadInst(tid);
816 InstSeqNum squash_seq_num = inst->seqNum;
817 fetch.squash(0, squash_seq_num, inst, tid);
818 decode.squash(tid);
819 rename.squash(squash_seq_num, tid);
820 iew.squash(tid);
821 iew.ldstQueue.squash(squash_seq_num, tid);
822 commit.rob->squash(squash_seq_num, tid);
823
824
825 assert(iew.instQueue.getCount(tid) == 0);
826 assert(iew.ldstQueue.getCount(tid) == 0);
827
828 // Reset ROB/IQ/LSQ Entries
829
830 // Commented out for now. This should be possible to do by
831 // telling all the pipeline stages to drain first, and then
832 // checking until the drain completes. Once the pipeline is
833 // drained, call resetEntries(). - 10-09-06 ktlim
834/*
835 if (activeThreads.size() >= 1) {
836 commit.rob->resetEntries();
837 iew.resetEntries();
838 }
839*/
840}
841
842
843template <class Impl>
844void
845FullO3CPU<Impl>::activateWhenReady(ThreadID tid)
846{
847 DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming"
848 "(e.g. PhysRegs/ROB/IQ/LSQ) \n",
849 tid);
850
851 bool ready = true;
852
853 if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) {
854 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
855 "Phys. Int. Regs.\n",
856 tid);
857 ready = false;
858 } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) {
859 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
860 "Phys. Float. Regs.\n",
861 tid);
862 ready = false;
863 } else if (commit.rob->numFreeEntries() >=
864 commit.rob->entryAmount(activeThreads.size() + 1)) {
865 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
866 "ROB entries.\n",
867 tid);
868 ready = false;
869 } else if (iew.instQueue.numFreeEntries() >=
870 iew.instQueue.entryAmount(activeThreads.size() + 1)) {
871 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
872 "IQ entries.\n",
873 tid);
874 ready = false;
875 } else if (iew.ldstQueue.numFreeEntries() >=
876 iew.ldstQueue.entryAmount(activeThreads.size() + 1)) {
877 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
878 "LSQ entries.\n",
879 tid);
880 ready = false;
881 }
882
883 if (ready) {
884 insertThread(tid);
885
886 contextSwitch = false;
887
888 cpuWaitList.remove(tid);
889 } else {
890 suspendContext(tid);
891
892 //blocks fetch
893 contextSwitch = true;
894
895 //@todo: dont always add to waitlist
896 //do waitlist
897 cpuWaitList.push_back(tid);
898 }
899}
900
901#if FULL_SYSTEM
902template <class Impl>
903Fault
904FullO3CPU<Impl>::hwrei(ThreadID tid)
905{
906#if THE_ISA == ALPHA_ISA
907 // Need to clear the lock flag upon returning from an interrupt.
908 this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
909
910 this->thread[tid]->kernelStats->hwrei();
911
912 // FIXME: XXX check for interrupts? XXX
913#endif
914 return NoFault;
915}
916
917template <class Impl>
918bool
919FullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid)
920{
921#if THE_ISA == ALPHA_ISA
922 if (this->thread[tid]->kernelStats)
923 this->thread[tid]->kernelStats->callpal(palFunc,
924 this->threadContexts[tid]);
925
926 switch (palFunc) {
927 case PAL::halt:
928 halt();
929 if (--System::numSystemsRunning == 0)
930 exitSimLoop("all cpus halted");
931 break;
932
933 case PAL::bpt:
934 case PAL::bugchk:
935 if (this->system->breakpoint())
936 return false;
937 break;
938 }
939#endif
940 return true;
941}
942
943template <class Impl>
944Fault
945FullO3CPU<Impl>::getInterrupts()
946{
947 // Check if there are any outstanding interrupts
948 return this->interrupts->getInterrupt(this->threadContexts[0]);
949}
950
951template <class Impl>
952void
953FullO3CPU<Impl>::processInterrupts(Fault interrupt)
954{
955 // Check for interrupts here. For now can copy the code that
956 // exists within isa_fullsys_traits.hh. Also assume that thread 0
957 // is the one that handles the interrupts.
958 // @todo: Possibly consolidate the interrupt checking code.
959 // @todo: Allow other threads to handle interrupts.
960
961 assert(interrupt != NoFault);
962 this->interrupts->updateIntrInfo(this->threadContexts[0]);
963
964 DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
965 this->trap(interrupt, 0, NULL);
966}
967
968template <class Impl>
969void
970FullO3CPU<Impl>::updateMemPorts()
971{
972 // Update all ThreadContext's memory ports (Functional/Virtual
973 // Ports)
974 ThreadID size = thread.size();
975 for (ThreadID i = 0; i < size; ++i)
976 thread[i]->connectMemPorts(thread[i]->getTC());
977}
978#endif
979
980template <class Impl>
981void
982FullO3CPU<Impl>::trap(Fault fault, ThreadID tid, StaticInstPtr inst)
983{
984 // Pass the thread's TC into the invoke method.
985 fault->invoke(this->threadContexts[tid], inst);
986}
987
988#if !FULL_SYSTEM
989
990template <class Impl>
991void
992FullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid)
993{
994 DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid);
995
996 DPRINTF(Activity,"Activity: syscall() called.\n");
997
998 // Temporarily increase this by one to account for the syscall
999 // instruction.
1000 ++(this->thread[tid]->funcExeInst);
1001
1002 // Execute the actual syscall.
1003 this->thread[tid]->syscall(callnum);
1004
1005 // Decrease funcExeInst by one as the normal commit will handle
1006 // incrementing it.
1007 --(this->thread[tid]->funcExeInst);
1008}
1009
1010#endif
1011
1012template <class Impl>
1013void
1014FullO3CPU<Impl>::serialize(std::ostream &os)
1015{
1016 SimObject::State so_state = SimObject::getState();
1017 SERIALIZE_ENUM(so_state);
1018 BaseCPU::serialize(os);
1019 nameOut(os, csprintf("%s.tickEvent", name()));
1020 tickEvent.serialize(os);
1021
1022 // Use SimpleThread's ability to checkpoint to make it easier to
1023 // write out the registers. Also make this static so it doesn't
1024 // get instantiated multiple times (causes a panic in statistics).
1025 static SimpleThread temp;
1026
1027 ThreadID size = thread.size();
1028 for (ThreadID i = 0; i < size; i++) {
1029 nameOut(os, csprintf("%s.xc.%i", name(), i));
1030 temp.copyTC(thread[i]->getTC());
1031 temp.serialize(os);
1032 }
1033}
1034
1035template <class Impl>
1036void
1037FullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion)
1038{
1039 SimObject::State so_state;
1040 UNSERIALIZE_ENUM(so_state);
1041 BaseCPU::unserialize(cp, section);
1042 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
1043
1044 // Use SimpleThread's ability to checkpoint to make it easier to
1045 // read in the registers. Also make this static so it doesn't
1046 // get instantiated multiple times (causes a panic in statistics).
1047 static SimpleThread temp;
1048
1049 ThreadID size = thread.size();
1050 for (ThreadID i = 0; i < size; i++) {
1051 temp.copyTC(thread[i]->getTC());
1052 temp.unserialize(cp, csprintf("%s.xc.%i", section, i));
1053 thread[i]->getTC()->copyArchRegs(temp.getTC());
1054 }
1055}
1056
1057template <class Impl>
1058unsigned int
1059FullO3CPU<Impl>::drain(Event *drain_event)
1060{
1061 DPRINTF(O3CPU, "Switching out\n");
1062
1063 // If the CPU isn't doing anything, then return immediately.
1064 if (_status == Idle || _status == SwitchedOut) {
1065 return 0;
1066 }
1067
1068 drainCount = 0;
1069 fetch.drain();
1070 decode.drain();
1071 rename.drain();
1072 iew.drain();
1073 commit.drain();
1074
1075 // Wake the CPU and record activity so everything can drain out if
1076 // the CPU was not able to immediately drain.
1077 if (getState() != SimObject::Drained) {
1078 // A bit of a hack...set the drainEvent after all the drain()
1079 // calls have been made, that way if all of the stages drain
1080 // immediately, the signalDrained() function knows not to call
1081 // process on the drain event.
1082 drainEvent = drain_event;
1083
1084 wakeCPU();
1085 activityRec.activity();
1086
1087 return 1;
1088 } else {
1089 return 0;
1090 }
1091}
1092
1093template <class Impl>
1094void
1095FullO3CPU<Impl>::resume()
1096{
1097 fetch.resume();
1098 decode.resume();
1099 rename.resume();
1100 iew.resume();
1101 commit.resume();
1102
1103 changeState(SimObject::Running);
1104
1105 if (_status == SwitchedOut || _status == Idle)
1106 return;
1107
| 208 drainCount(0),
209 deferRegistration(params->defer_registration)
210{
211 if (!deferRegistration) {
212 _status = Running;
213 } else {
214 _status = Idle;
215 }
216
217#if USE_CHECKER
218 if (params->checker) {
219 BaseCPU *temp_checker = params->checker;
220 checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
221#if FULL_SYSTEM
222 checker->setSystem(params->system);
223#endif
224 } else {
225 checker = NULL;
226 }
227#endif // USE_CHECKER
228
229#if !FULL_SYSTEM
230 thread.resize(numThreads);
231 tids.resize(numThreads);
232#endif
233
234 // The stages also need their CPU pointer setup. However this
235 // must be done at the upper level CPU because they have pointers
236 // to the upper level CPU, and not this FullO3CPU.
237
238 // Set up Pointers to the activeThreads list for each stage
239 fetch.setActiveThreads(&activeThreads);
240 decode.setActiveThreads(&activeThreads);
241 rename.setActiveThreads(&activeThreads);
242 iew.setActiveThreads(&activeThreads);
243 commit.setActiveThreads(&activeThreads);
244
245 // Give each of the stages the time buffer they will use.
246 fetch.setTimeBuffer(&timeBuffer);
247 decode.setTimeBuffer(&timeBuffer);
248 rename.setTimeBuffer(&timeBuffer);
249 iew.setTimeBuffer(&timeBuffer);
250 commit.setTimeBuffer(&timeBuffer);
251
252 // Also setup each of the stages' queues.
253 fetch.setFetchQueue(&fetchQueue);
254 decode.setFetchQueue(&fetchQueue);
255 commit.setFetchQueue(&fetchQueue);
256 decode.setDecodeQueue(&decodeQueue);
257 rename.setDecodeQueue(&decodeQueue);
258 rename.setRenameQueue(&renameQueue);
259 iew.setRenameQueue(&renameQueue);
260 iew.setIEWQueue(&iewQueue);
261 commit.setIEWQueue(&iewQueue);
262 commit.setRenameQueue(&renameQueue);
263
264 commit.setIEWStage(&iew);
265 rename.setIEWStage(&iew);
266 rename.setCommitStage(&commit);
267
268#if !FULL_SYSTEM
269 ThreadID active_threads = params->workload.size();
270
271 if (active_threads > Impl::MaxThreads) {
272 panic("Workload Size too large. Increase the 'MaxThreads'"
273 "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or "
274 "edit your workload size.");
275 }
276#else
277 ThreadID active_threads = 1;
278#endif
279
280 //Make Sure That this a Valid Architeture
281 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs);
282 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
283
284 rename.setScoreboard(&scoreboard);
285 iew.setScoreboard(&scoreboard);
286
287 // Setup the rename map for whichever stages need it.
288 PhysRegIndex lreg_idx = 0;
289 PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs
290
291 for (ThreadID tid = 0; tid < numThreads; tid++) {
292 bool bindRegs = (tid <= active_threads - 1);
293
294 commitRenameMap[tid].init(TheISA::NumIntRegs,
295 params->numPhysIntRegs,
296 lreg_idx, //Index for Logical. Regs
297
298 TheISA::NumFloatRegs,
299 params->numPhysFloatRegs,
300 freg_idx, //Index for Float Regs
301
302 TheISA::NumMiscRegs,
303
304 TheISA::ZeroReg,
305 TheISA::ZeroReg,
306
307 tid,
308 false);
309
310 renameMap[tid].init(TheISA::NumIntRegs,
311 params->numPhysIntRegs,
312 lreg_idx, //Index for Logical. Regs
313
314 TheISA::NumFloatRegs,
315 params->numPhysFloatRegs,
316 freg_idx, //Index for Float Regs
317
318 TheISA::NumMiscRegs,
319
320 TheISA::ZeroReg,
321 TheISA::ZeroReg,
322
323 tid,
324 bindRegs);
325
326 activateThreadEvent[tid].init(tid, this);
327 deallocateContextEvent[tid].init(tid, this);
328 }
329
330 rename.setRenameMap(renameMap);
331 commit.setRenameMap(commitRenameMap);
332
333 // Give renameMap & rename stage access to the freeList;
334 for (ThreadID tid = 0; tid < numThreads; tid++)
335 renameMap[tid].setFreeList(&freeList);
336 rename.setFreeList(&freeList);
337
338 // Setup the ROB for whichever stages need it.
339 commit.setROB(&rob);
340
341 lastRunningCycle = curTick();
342
343 lastActivatedCycle = -1;
344#if 0
345 // Give renameMap & rename stage access to the freeList;
346 for (ThreadID tid = 0; tid < numThreads; tid++)
347 globalSeqNum[tid] = 1;
348#endif
349
350 contextSwitch = false;
351 DPRINTF(O3CPU, "Creating O3CPU object.\n");
352
353 // Setup any thread state.
354 this->thread.resize(this->numThreads);
355
356 for (ThreadID tid = 0; tid < this->numThreads; ++tid) {
357#if FULL_SYSTEM
358 // SMT is not supported in FS mode yet.
359 assert(this->numThreads == 1);
360 this->thread[tid] = new Thread(this, 0);
361#else
362 if (tid < params->workload.size()) {
363 DPRINTF(O3CPU, "Workload[%i] process is %#x",
364 tid, this->thread[tid]);
365 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
366 (typename Impl::O3CPU *)(this),
367 tid, params->workload[tid]);
368
369 //usedTids[tid] = true;
370 //threadMap[tid] = tid;
371 } else {
372 //Allocate Empty thread so M5 can use later
373 //when scheduling threads to CPU
374 Process* dummy_proc = NULL;
375
376 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
377 (typename Impl::O3CPU *)(this),
378 tid, dummy_proc);
379 //usedTids[tid] = false;
380 }
381#endif // !FULL_SYSTEM
382
383 ThreadContext *tc;
384
385 // Setup the TC that will serve as the interface to the threads/CPU.
386 O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>;
387
388 tc = o3_tc;
389
390 // If we're using a checker, then the TC should be the
391 // CheckerThreadContext.
392#if USE_CHECKER
393 if (params->checker) {
394 tc = new CheckerThreadContext<O3ThreadContext<Impl> >(
395 o3_tc, this->checker);
396 }
397#endif
398
399 o3_tc->cpu = (typename Impl::O3CPU *)(this);
400 assert(o3_tc->cpu);
401 o3_tc->thread = this->thread[tid];
402
403#if FULL_SYSTEM
404 // Setup quiesce event.
405 this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
406#endif
407 // Give the thread the TC.
408 this->thread[tid]->tc = tc;
409
410 // Add the TC to the CPU's list of TC's.
411 this->threadContexts.push_back(tc);
412 }
413
414 for (ThreadID tid = 0; tid < this->numThreads; tid++)
415 this->thread[tid]->setFuncExeInst(0);
416
417 lockAddr = 0;
418 lockFlag = false;
419}
420
421template <class Impl>
422FullO3CPU<Impl>::~FullO3CPU()
423{
424}
425
426template <class Impl>
427void
428FullO3CPU<Impl>::regStats()
429{
430 BaseO3CPU::regStats();
431
432 // Register any of the O3CPU's stats here.
433 timesIdled
434 .name(name() + ".timesIdled")
435 .desc("Number of times that the entire CPU went into an idle state and"
436 " unscheduled itself")
437 .prereq(timesIdled);
438
439 idleCycles
440 .name(name() + ".idleCycles")
441 .desc("Total number of cycles that the CPU has spent unscheduled due "
442 "to idling")
443 .prereq(idleCycles);
444
445 // Number of Instructions simulated
446 // --------------------------------
447 // Should probably be in Base CPU but need templated
448 // MaxThreads so put in here instead
449 committedInsts
450 .init(numThreads)
451 .name(name() + ".committedInsts")
452 .desc("Number of Instructions Simulated");
453
454 totalCommittedInsts
455 .name(name() + ".committedInsts_total")
456 .desc("Number of Instructions Simulated");
457
458 cpi
459 .name(name() + ".cpi")
460 .desc("CPI: Cycles Per Instruction")
461 .precision(6);
462 cpi = numCycles / committedInsts;
463
464 totalCpi
465 .name(name() + ".cpi_total")
466 .desc("CPI: Total CPI of All Threads")
467 .precision(6);
468 totalCpi = numCycles / totalCommittedInsts;
469
470 ipc
471 .name(name() + ".ipc")
472 .desc("IPC: Instructions Per Cycle")
473 .precision(6);
474 ipc = committedInsts / numCycles;
475
476 totalIpc
477 .name(name() + ".ipc_total")
478 .desc("IPC: Total IPC of All Threads")
479 .precision(6);
480 totalIpc = totalCommittedInsts / numCycles;
481
482 this->fetch.regStats();
483 this->decode.regStats();
484 this->rename.regStats();
485 this->iew.regStats();
486 this->commit.regStats();
487 this->rob.regStats();
488
489 intRegfileReads
490 .name(name() + ".int_regfile_reads")
491 .desc("number of integer regfile reads")
492 .prereq(intRegfileReads);
493
494 intRegfileWrites
495 .name(name() + ".int_regfile_writes")
496 .desc("number of integer regfile writes")
497 .prereq(intRegfileWrites);
498
499 fpRegfileReads
500 .name(name() + ".fp_regfile_reads")
501 .desc("number of floating regfile reads")
502 .prereq(fpRegfileReads);
503
504 fpRegfileWrites
505 .name(name() + ".fp_regfile_writes")
506 .desc("number of floating regfile writes")
507 .prereq(fpRegfileWrites);
508
509 miscRegfileReads
510 .name(name() + ".misc_regfile_reads")
511 .desc("number of misc regfile reads")
512 .prereq(miscRegfileReads);
513
514 miscRegfileWrites
515 .name(name() + ".misc_regfile_writes")
516 .desc("number of misc regfile writes")
517 .prereq(miscRegfileWrites);
518}
519
520template <class Impl>
521Port *
522FullO3CPU<Impl>::getPort(const std::string &if_name, int idx)
523{
524 if (if_name == "dcache_port")
525 return iew.getDcachePort();
526 else if (if_name == "icache_port")
527 return fetch.getIcachePort();
528 else
529 panic("No Such Port\n");
530}
531
532template <class Impl>
533void
534FullO3CPU<Impl>::tick()
535{
536 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
537
538 ++numCycles;
539
540// activity = false;
541
542 //Tick each of the stages
543 fetch.tick();
544
545 decode.tick();
546
547 rename.tick();
548
549 iew.tick();
550
551 commit.tick();
552
553#if !FULL_SYSTEM
554 doContextSwitch();
555#endif
556
557 // Now advance the time buffers
558 timeBuffer.advance();
559
560 fetchQueue.advance();
561 decodeQueue.advance();
562 renameQueue.advance();
563 iewQueue.advance();
564
565 activityRec.advance();
566
567 if (removeInstsThisCycle) {
568 cleanUpRemovedInsts();
569 }
570
571 if (!tickEvent.scheduled()) {
572 if (_status == SwitchedOut ||
573 getState() == SimObject::Drained) {
574 DPRINTF(O3CPU, "Switched out!\n");
575 // increment stat
576 lastRunningCycle = curTick();
577 } else if (!activityRec.active() || _status == Idle) {
578 DPRINTF(O3CPU, "Idle!\n");
579 lastRunningCycle = curTick();
580 timesIdled++;
581 } else {
582 schedule(tickEvent, nextCycle(curTick() + ticks(1)));
583 DPRINTF(O3CPU, "Scheduling next tick!\n");
584 }
585 }
586
587#if !FULL_SYSTEM
588 updateThreadPriority();
589#endif
590}
591
592template <class Impl>
593void
594FullO3CPU<Impl>::init()
595{
596 BaseCPU::init();
597
598 // Set inSyscall so that the CPU doesn't squash when initially
599 // setting up registers.
600 for (ThreadID tid = 0; tid < numThreads; ++tid)
601 thread[tid]->inSyscall = true;
602
603#if FULL_SYSTEM
604 for (ThreadID tid = 0; tid < numThreads; tid++) {
605 ThreadContext *src_tc = threadContexts[tid];
606 TheISA::initCPU(src_tc, src_tc->contextId());
607 }
608#endif
609
610 // Clear inSyscall.
611 for (int tid = 0; tid < numThreads; ++tid)
612 thread[tid]->inSyscall = false;
613
614 // Initialize stages.
615 fetch.initStage();
616 iew.initStage();
617 rename.initStage();
618 commit.initStage();
619
620 commit.setThreads(thread);
621}
622
623template <class Impl>
624void
625FullO3CPU<Impl>::activateThread(ThreadID tid)
626{
627 list<ThreadID>::iterator isActive =
628 std::find(activeThreads.begin(), activeThreads.end(), tid);
629
630 DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid);
631
632 if (isActive == activeThreads.end()) {
633 DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n",
634 tid);
635
636 activeThreads.push_back(tid);
637 }
638}
639
640template <class Impl>
641void
642FullO3CPU<Impl>::deactivateThread(ThreadID tid)
643{
644 //Remove From Active List, if Active
645 list<ThreadID>::iterator thread_it =
646 std::find(activeThreads.begin(), activeThreads.end(), tid);
647
648 DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid);
649
650 if (thread_it != activeThreads.end()) {
651 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
652 tid);
653 activeThreads.erase(thread_it);
654 }
655}
656
657template <class Impl>
658Counter
659FullO3CPU<Impl>::totalInstructions() const
660{
661 Counter total(0);
662
663 ThreadID size = thread.size();
664 for (ThreadID i = 0; i < size; i++)
665 total += thread[i]->numInst;
666
667 return total;
668}
669
670template <class Impl>
671void
672FullO3CPU<Impl>::activateContext(ThreadID tid, int delay)
673{
674 // Needs to set each stage to running as well.
675 if (delay){
676 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate "
677 "on cycle %d\n", tid, curTick() + ticks(delay));
678 scheduleActivateThreadEvent(tid, delay);
679 } else {
680 activateThread(tid);
681 }
682
683 if (lastActivatedCycle < curTick()) {
684 scheduleTickEvent(delay);
685
686 // Be sure to signal that there's some activity so the CPU doesn't
687 // deschedule itself.
688 activityRec.activity();
689 fetch.wakeFromQuiesce();
690
691 lastActivatedCycle = curTick();
692
693 _status = Running;
694 }
695}
696
697template <class Impl>
698bool
699FullO3CPU<Impl>::deallocateContext(ThreadID tid, bool remove, int delay)
700{
701 // Schedule removal of thread data from CPU
702 if (delay){
703 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate "
704 "on cycle %d\n", tid, curTick() + ticks(delay));
705 scheduleDeallocateContextEvent(tid, remove, delay);
706 return false;
707 } else {
708 deactivateThread(tid);
709 if (remove)
710 removeThread(tid);
711 return true;
712 }
713}
714
715template <class Impl>
716void
717FullO3CPU<Impl>::suspendContext(ThreadID tid)
718{
719 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
720 bool deallocated = deallocateContext(tid, false, 1);
721 // If this was the last thread then unschedule the tick event.
722 if ((activeThreads.size() == 1 && !deallocated) ||
723 activeThreads.size() == 0)
724 unscheduleTickEvent();
725 _status = Idle;
726}
727
728template <class Impl>
729void
730FullO3CPU<Impl>::haltContext(ThreadID tid)
731{
732 //For now, this is the same as deallocate
733 DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
734 deallocateContext(tid, true, 1);
735}
736
737template <class Impl>
738void
739FullO3CPU<Impl>::insertThread(ThreadID tid)
740{
741 DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
742 // Will change now that the PC and thread state is internal to the CPU
743 // and not in the ThreadContext.
744#if FULL_SYSTEM
745 ThreadContext *src_tc = system->threadContexts[tid];
746#else
747 ThreadContext *src_tc = tcBase(tid);
748#endif
749
750 //Bind Int Regs to Rename Map
751 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
752 PhysRegIndex phys_reg = freeList.getIntReg();
753
754 renameMap[tid].setEntry(ireg,phys_reg);
755 scoreboard.setReg(phys_reg);
756 }
757
758 //Bind Float Regs to Rename Map
759 for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
760 PhysRegIndex phys_reg = freeList.getFloatReg();
761
762 renameMap[tid].setEntry(freg,phys_reg);
763 scoreboard.setReg(phys_reg);
764 }
765
766 //Copy Thread Data Into RegFile
767 //this->copyFromTC(tid);
768
769 //Set PC/NPC/NNPC
770 pcState(src_tc->pcState(), tid);
771
772 src_tc->setStatus(ThreadContext::Active);
773
774 activateContext(tid,1);
775
776 //Reset ROB/IQ/LSQ Entries
777 commit.rob->resetEntries();
778 iew.resetEntries();
779}
780
781template <class Impl>
782void
783FullO3CPU<Impl>::removeThread(ThreadID tid)
784{
785 DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
786
787 // Copy Thread Data From RegFile
788 // If thread is suspended, it might be re-allocated
789 // this->copyToTC(tid);
790
791
792 // @todo: 2-27-2008: Fix how we free up rename mappings
793 // here to alleviate the case for double-freeing registers
794 // in SMT workloads.
795
796 // Unbind Int Regs from Rename Map
797 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
798 PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
799
800 scoreboard.unsetReg(phys_reg);
801 freeList.addReg(phys_reg);
802 }
803
804 // Unbind Float Regs from Rename Map
805 for (int freg = TheISA::NumIntRegs; freg < TheISA::NumFloatRegs; freg++) {
806 PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
807
808 scoreboard.unsetReg(phys_reg);
809 freeList.addReg(phys_reg);
810 }
811
812 // Squash Throughout Pipeline
813 DynInstPtr inst = commit.rob->readHeadInst(tid);
814 InstSeqNum squash_seq_num = inst->seqNum;
815 fetch.squash(0, squash_seq_num, inst, tid);
816 decode.squash(tid);
817 rename.squash(squash_seq_num, tid);
818 iew.squash(tid);
819 iew.ldstQueue.squash(squash_seq_num, tid);
820 commit.rob->squash(squash_seq_num, tid);
821
822
823 assert(iew.instQueue.getCount(tid) == 0);
824 assert(iew.ldstQueue.getCount(tid) == 0);
825
826 // Reset ROB/IQ/LSQ Entries
827
828 // Commented out for now. This should be possible to do by
829 // telling all the pipeline stages to drain first, and then
830 // checking until the drain completes. Once the pipeline is
831 // drained, call resetEntries(). - 10-09-06 ktlim
832/*
833 if (activeThreads.size() >= 1) {
834 commit.rob->resetEntries();
835 iew.resetEntries();
836 }
837*/
838}
839
840
841template <class Impl>
842void
843FullO3CPU<Impl>::activateWhenReady(ThreadID tid)
844{
845 DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming"
846 "(e.g. PhysRegs/ROB/IQ/LSQ) \n",
847 tid);
848
849 bool ready = true;
850
851 if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) {
852 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
853 "Phys. Int. Regs.\n",
854 tid);
855 ready = false;
856 } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) {
857 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
858 "Phys. Float. Regs.\n",
859 tid);
860 ready = false;
861 } else if (commit.rob->numFreeEntries() >=
862 commit.rob->entryAmount(activeThreads.size() + 1)) {
863 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
864 "ROB entries.\n",
865 tid);
866 ready = false;
867 } else if (iew.instQueue.numFreeEntries() >=
868 iew.instQueue.entryAmount(activeThreads.size() + 1)) {
869 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
870 "IQ entries.\n",
871 tid);
872 ready = false;
873 } else if (iew.ldstQueue.numFreeEntries() >=
874 iew.ldstQueue.entryAmount(activeThreads.size() + 1)) {
875 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
876 "LSQ entries.\n",
877 tid);
878 ready = false;
879 }
880
881 if (ready) {
882 insertThread(tid);
883
884 contextSwitch = false;
885
886 cpuWaitList.remove(tid);
887 } else {
888 suspendContext(tid);
889
890 //blocks fetch
891 contextSwitch = true;
892
893 //@todo: dont always add to waitlist
894 //do waitlist
895 cpuWaitList.push_back(tid);
896 }
897}
898
899#if FULL_SYSTEM
900template <class Impl>
901Fault
902FullO3CPU<Impl>::hwrei(ThreadID tid)
903{
904#if THE_ISA == ALPHA_ISA
905 // Need to clear the lock flag upon returning from an interrupt.
906 this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
907
908 this->thread[tid]->kernelStats->hwrei();
909
910 // FIXME: XXX check for interrupts? XXX
911#endif
912 return NoFault;
913}
914
915template <class Impl>
916bool
917FullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid)
918{
919#if THE_ISA == ALPHA_ISA
920 if (this->thread[tid]->kernelStats)
921 this->thread[tid]->kernelStats->callpal(palFunc,
922 this->threadContexts[tid]);
923
924 switch (palFunc) {
925 case PAL::halt:
926 halt();
927 if (--System::numSystemsRunning == 0)
928 exitSimLoop("all cpus halted");
929 break;
930
931 case PAL::bpt:
932 case PAL::bugchk:
933 if (this->system->breakpoint())
934 return false;
935 break;
936 }
937#endif
938 return true;
939}
940
941template <class Impl>
942Fault
943FullO3CPU<Impl>::getInterrupts()
944{
945 // Check if there are any outstanding interrupts
946 return this->interrupts->getInterrupt(this->threadContexts[0]);
947}
948
949template <class Impl>
950void
951FullO3CPU<Impl>::processInterrupts(Fault interrupt)
952{
953 // Check for interrupts here. For now can copy the code that
954 // exists within isa_fullsys_traits.hh. Also assume that thread 0
955 // is the one that handles the interrupts.
956 // @todo: Possibly consolidate the interrupt checking code.
957 // @todo: Allow other threads to handle interrupts.
958
959 assert(interrupt != NoFault);
960 this->interrupts->updateIntrInfo(this->threadContexts[0]);
961
962 DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
963 this->trap(interrupt, 0, NULL);
964}
965
966template <class Impl>
967void
968FullO3CPU<Impl>::updateMemPorts()
969{
970 // Update all ThreadContext's memory ports (Functional/Virtual
971 // Ports)
972 ThreadID size = thread.size();
973 for (ThreadID i = 0; i < size; ++i)
974 thread[i]->connectMemPorts(thread[i]->getTC());
975}
976#endif
977
978template <class Impl>
979void
980FullO3CPU<Impl>::trap(Fault fault, ThreadID tid, StaticInstPtr inst)
981{
982 // Pass the thread's TC into the invoke method.
983 fault->invoke(this->threadContexts[tid], inst);
984}
985
986#if !FULL_SYSTEM
987
988template <class Impl>
989void
990FullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid)
991{
992 DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid);
993
994 DPRINTF(Activity,"Activity: syscall() called.\n");
995
996 // Temporarily increase this by one to account for the syscall
997 // instruction.
998 ++(this->thread[tid]->funcExeInst);
999
1000 // Execute the actual syscall.
1001 this->thread[tid]->syscall(callnum);
1002
1003 // Decrease funcExeInst by one as the normal commit will handle
1004 // incrementing it.
1005 --(this->thread[tid]->funcExeInst);
1006}
1007
1008#endif
1009
1010template <class Impl>
1011void
1012FullO3CPU<Impl>::serialize(std::ostream &os)
1013{
1014 SimObject::State so_state = SimObject::getState();
1015 SERIALIZE_ENUM(so_state);
1016 BaseCPU::serialize(os);
1017 nameOut(os, csprintf("%s.tickEvent", name()));
1018 tickEvent.serialize(os);
1019
1020 // Use SimpleThread's ability to checkpoint to make it easier to
1021 // write out the registers. Also make this static so it doesn't
1022 // get instantiated multiple times (causes a panic in statistics).
1023 static SimpleThread temp;
1024
1025 ThreadID size = thread.size();
1026 for (ThreadID i = 0; i < size; i++) {
1027 nameOut(os, csprintf("%s.xc.%i", name(), i));
1028 temp.copyTC(thread[i]->getTC());
1029 temp.serialize(os);
1030 }
1031}
1032
1033template <class Impl>
1034void
1035FullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion)
1036{
1037 SimObject::State so_state;
1038 UNSERIALIZE_ENUM(so_state);
1039 BaseCPU::unserialize(cp, section);
1040 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
1041
1042 // Use SimpleThread's ability to checkpoint to make it easier to
1043 // read in the registers. Also make this static so it doesn't
1044 // get instantiated multiple times (causes a panic in statistics).
1045 static SimpleThread temp;
1046
1047 ThreadID size = thread.size();
1048 for (ThreadID i = 0; i < size; i++) {
1049 temp.copyTC(thread[i]->getTC());
1050 temp.unserialize(cp, csprintf("%s.xc.%i", section, i));
1051 thread[i]->getTC()->copyArchRegs(temp.getTC());
1052 }
1053}
1054
1055template <class Impl>
1056unsigned int
1057FullO3CPU<Impl>::drain(Event *drain_event)
1058{
1059 DPRINTF(O3CPU, "Switching out\n");
1060
1061 // If the CPU isn't doing anything, then return immediately.
1062 if (_status == Idle || _status == SwitchedOut) {
1063 return 0;
1064 }
1065
1066 drainCount = 0;
1067 fetch.drain();
1068 decode.drain();
1069 rename.drain();
1070 iew.drain();
1071 commit.drain();
1072
1073 // Wake the CPU and record activity so everything can drain out if
1074 // the CPU was not able to immediately drain.
1075 if (getState() != SimObject::Drained) {
1076 // A bit of a hack...set the drainEvent after all the drain()
1077 // calls have been made, that way if all of the stages drain
1078 // immediately, the signalDrained() function knows not to call
1079 // process on the drain event.
1080 drainEvent = drain_event;
1081
1082 wakeCPU();
1083 activityRec.activity();
1084
1085 return 1;
1086 } else {
1087 return 0;
1088 }
1089}
1090
1091template <class Impl>
1092void
1093FullO3CPU<Impl>::resume()
1094{
1095 fetch.resume();
1096 decode.resume();
1097 rename.resume();
1098 iew.resume();
1099 commit.resume();
1100
1101 changeState(SimObject::Running);
1102
1103 if (_status == SwitchedOut || _status == Idle)
1104 return;
1105
|
1108#if FULL_SYSTEM
| |
1109 assert(system->getMemoryMode() == Enums::timing);
| 1106 assert(system->getMemoryMode() == Enums::timing);
|
1110#endif
| |
1111
1112 if (!tickEvent.scheduled())
1113 schedule(tickEvent, nextCycle());
1114 _status = Running;
1115}
1116
1117template <class Impl>
1118void
1119FullO3CPU<Impl>::signalDrained()
1120{
1121 if (++drainCount == NumStages) {
1122 if (tickEvent.scheduled())
1123 tickEvent.squash();
1124
1125 changeState(SimObject::Drained);
1126
1127 BaseCPU::switchOut();
1128
1129 if (drainEvent) {
1130 drainEvent->process();
1131 drainEvent = NULL;
1132 }
1133 }
1134 assert(drainCount <= 5);
1135}
1136
1137template <class Impl>
1138void
1139FullO3CPU<Impl>::switchOut()
1140{
1141 fetch.switchOut();
1142 rename.switchOut();
1143 iew.switchOut();
1144 commit.switchOut();
1145 instList.clear();
1146 while (!removeList.empty()) {
1147 removeList.pop();
1148 }
1149
1150 _status = SwitchedOut;
1151#if USE_CHECKER
1152 if (checker)
1153 checker->switchOut();
1154#endif
1155 if (tickEvent.scheduled())
1156 tickEvent.squash();
1157}
1158
1159template <class Impl>
1160void
1161FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
1162{
1163 // Flush out any old data from the time buffers.
1164 for (int i = 0; i < timeBuffer.getSize(); ++i) {
1165 timeBuffer.advance();
1166 fetchQueue.advance();
1167 decodeQueue.advance();
1168 renameQueue.advance();
1169 iewQueue.advance();
1170 }
1171
1172 activityRec.reset();
1173
1174 BaseCPU::takeOverFrom(oldCPU, fetch.getIcachePort(), iew.getDcachePort());
1175
1176 fetch.takeOverFrom();
1177 decode.takeOverFrom();
1178 rename.takeOverFrom();
1179 iew.takeOverFrom();
1180 commit.takeOverFrom();
1181
1182 assert(!tickEvent.scheduled() || tickEvent.squashed());
1183
1184 // @todo: Figure out how to properly select the tid to put onto
1185 // the active threads list.
1186 ThreadID tid = 0;
1187
1188 list<ThreadID>::iterator isActive =
1189 std::find(activeThreads.begin(), activeThreads.end(), tid);
1190
1191 if (isActive == activeThreads.end()) {
1192 //May Need to Re-code this if the delay variable is the delay
1193 //needed for thread to activate
1194 DPRINTF(O3CPU, "Adding Thread %i to active threads list\n",
1195 tid);
1196
1197 activeThreads.push_back(tid);
1198 }
1199
1200 // Set all statuses to active, schedule the CPU's tick event.
1201 // @todo: Fix up statuses so this is handled properly
1202 ThreadID size = threadContexts.size();
1203 for (ThreadID i = 0; i < size; ++i) {
1204 ThreadContext *tc = threadContexts[i];
1205 if (tc->status() == ThreadContext::Active && _status != Running) {
1206 _status = Running;
1207 reschedule(tickEvent, nextCycle(), true);
1208 }
1209 }
1210 if (!tickEvent.scheduled())
1211 schedule(tickEvent, nextCycle());
1212}
1213
1214template <class Impl>
1215TheISA::MiscReg
1216FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid)
1217{
1218 return this->isa[tid].readMiscRegNoEffect(misc_reg);
1219}
1220
1221template <class Impl>
1222TheISA::MiscReg
1223FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
1224{
1225 miscRegfileReads++;
1226 return this->isa[tid].readMiscReg(misc_reg, tcBase(tid));
1227}
1228
1229template <class Impl>
1230void
1231FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
1232 const TheISA::MiscReg &val, ThreadID tid)
1233{
1234 this->isa[tid].setMiscRegNoEffect(misc_reg, val);
1235}
1236
1237template <class Impl>
1238void
1239FullO3CPU<Impl>::setMiscReg(int misc_reg,
1240 const TheISA::MiscReg &val, ThreadID tid)
1241{
1242 miscRegfileWrites++;
1243 this->isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
1244}
1245
1246template <class Impl>
1247uint64_t
1248FullO3CPU<Impl>::readIntReg(int reg_idx)
1249{
1250 intRegfileReads++;
1251 return regFile.readIntReg(reg_idx);
1252}
1253
1254template <class Impl>
1255FloatReg
1256FullO3CPU<Impl>::readFloatReg(int reg_idx)
1257{
1258 fpRegfileReads++;
1259 return regFile.readFloatReg(reg_idx);
1260}
1261
1262template <class Impl>
1263FloatRegBits
1264FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
1265{
1266 fpRegfileReads++;
1267 return regFile.readFloatRegBits(reg_idx);
1268}
1269
1270template <class Impl>
1271void
1272FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
1273{
1274 intRegfileWrites++;
1275 regFile.setIntReg(reg_idx, val);
1276}
1277
1278template <class Impl>
1279void
1280FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
1281{
1282 fpRegfileWrites++;
1283 regFile.setFloatReg(reg_idx, val);
1284}
1285
1286template <class Impl>
1287void
1288FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
1289{
1290 fpRegfileWrites++;
1291 regFile.setFloatRegBits(reg_idx, val);
1292}
1293
1294template <class Impl>
1295uint64_t
1296FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1297{
1298 intRegfileReads++;
1299 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1300
1301 return regFile.readIntReg(phys_reg);
1302}
1303
1304template <class Impl>
1305float
1306FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
1307{
1308 fpRegfileReads++;
1309 int idx = reg_idx + TheISA::NumIntRegs;
1310 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1311
1312 return regFile.readFloatReg(phys_reg);
1313}
1314
1315template <class Impl>
1316uint64_t
1317FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid)
1318{
1319 fpRegfileReads++;
1320 int idx = reg_idx + TheISA::NumIntRegs;
1321 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1322
1323 return regFile.readFloatRegBits(phys_reg);
1324}
1325
1326template <class Impl>
1327void
1328FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
1329{
1330 intRegfileWrites++;
1331 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1332
1333 regFile.setIntReg(phys_reg, val);
1334}
1335
1336template <class Impl>
1337void
1338FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid)
1339{
1340 fpRegfileWrites++;
1341 int idx = reg_idx + TheISA::NumIntRegs;
1342 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1343
1344 regFile.setFloatReg(phys_reg, val);
1345}
1346
1347template <class Impl>
1348void
1349FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid)
1350{
1351 fpRegfileWrites++;
1352 int idx = reg_idx + TheISA::NumIntRegs;
1353 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1354
1355 regFile.setFloatRegBits(phys_reg, val);
1356}
1357
1358template <class Impl>
1359TheISA::PCState
1360FullO3CPU<Impl>::pcState(ThreadID tid)
1361{
1362 return commit.pcState(tid);
1363}
1364
1365template <class Impl>
1366void
1367FullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid)
1368{
1369 commit.pcState(val, tid);
1370}
1371
1372template <class Impl>
1373Addr
1374FullO3CPU<Impl>::instAddr(ThreadID tid)
1375{
1376 return commit.instAddr(tid);
1377}
1378
1379template <class Impl>
1380Addr
1381FullO3CPU<Impl>::nextInstAddr(ThreadID tid)
1382{
1383 return commit.nextInstAddr(tid);
1384}
1385
1386template <class Impl>
1387MicroPC
1388FullO3CPU<Impl>::microPC(ThreadID tid)
1389{
1390 return commit.microPC(tid);
1391}
1392
1393template <class Impl>
1394void
1395FullO3CPU<Impl>::squashFromTC(ThreadID tid)
1396{
1397 this->thread[tid]->inSyscall = true;
1398 this->commit.generateTCEvent(tid);
1399}
1400
1401template <class Impl>
1402typename FullO3CPU<Impl>::ListIt
1403FullO3CPU<Impl>::addInst(DynInstPtr &inst)
1404{
1405 instList.push_back(inst);
1406
1407 return --(instList.end());
1408}
1409
1410template <class Impl>
1411void
1412FullO3CPU<Impl>::instDone(ThreadID tid)
1413{
1414 // Keep an instruction count.
1415 thread[tid]->numInst++;
1416 thread[tid]->numInsts++;
1417 committedInsts[tid]++;
1418 totalCommittedInsts++;
1419 system->totalNumInsts++;
1420 // Check for instruction-count-based events.
1421 comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1422 system->instEventQueue.serviceEvents(system->totalNumInsts);
1423}
1424
1425template <class Impl>
1426void
1427FullO3CPU<Impl>::addToRemoveList(DynInstPtr &inst)
1428{
1429 removeInstsThisCycle = true;
1430
1431 removeList.push(inst->getInstListIt());
1432}
1433
1434template <class Impl>
1435void
1436FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
1437{
1438 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s "
1439 "[sn:%lli]\n",
1440 inst->threadNumber, inst->pcState(), inst->seqNum);
1441
1442 removeInstsThisCycle = true;
1443
1444 // Remove the front instruction.
1445 removeList.push(inst->getInstListIt());
1446}
1447
1448template <class Impl>
1449void
1450FullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid)
1451{
1452 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1453 " list.\n", tid);
1454
1455 ListIt end_it;
1456
1457 bool rob_empty = false;
1458
1459 if (instList.empty()) {
1460 return;
1461 } else if (rob.isEmpty(/*tid*/)) {
1462 DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1463 end_it = instList.begin();
1464 rob_empty = true;
1465 } else {
1466 end_it = (rob.readTailInst(tid))->getInstListIt();
1467 DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1468 }
1469
1470 removeInstsThisCycle = true;
1471
1472 ListIt inst_it = instList.end();
1473
1474 inst_it--;
1475
1476 // Walk through the instruction list, removing any instructions
1477 // that were inserted after the given instruction iterator, end_it.
1478 while (inst_it != end_it) {
1479 assert(!instList.empty());
1480
1481 squashInstIt(inst_it, tid);
1482
1483 inst_it--;
1484 }
1485
1486 // If the ROB was empty, then we actually need to remove the first
1487 // instruction as well.
1488 if (rob_empty) {
1489 squashInstIt(inst_it, tid);
1490 }
1491}
1492
1493template <class Impl>
1494void
1495FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1496{
1497 assert(!instList.empty());
1498
1499 removeInstsThisCycle = true;
1500
1501 ListIt inst_iter = instList.end();
1502
1503 inst_iter--;
1504
1505 DPRINTF(O3CPU, "Deleting instructions from instruction "
1506 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1507 tid, seq_num, (*inst_iter)->seqNum);
1508
1509 while ((*inst_iter)->seqNum > seq_num) {
1510
1511 bool break_loop = (inst_iter == instList.begin());
1512
1513 squashInstIt(inst_iter, tid);
1514
1515 inst_iter--;
1516
1517 if (break_loop)
1518 break;
1519 }
1520}
1521
1522template <class Impl>
1523inline void
1524FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid)
1525{
1526 if ((*instIt)->threadNumber == tid) {
1527 DPRINTF(O3CPU, "Squashing instruction, "
1528 "[tid:%i] [sn:%lli] PC %s\n",
1529 (*instIt)->threadNumber,
1530 (*instIt)->seqNum,
1531 (*instIt)->pcState());
1532
1533 // Mark it as squashed.
1534 (*instIt)->setSquashed();
1535
1536 // @todo: Formulate a consistent method for deleting
1537 // instructions from the instruction list
1538 // Remove the instruction from the list.
1539 removeList.push(instIt);
1540 }
1541}
1542
1543template <class Impl>
1544void
1545FullO3CPU<Impl>::cleanUpRemovedInsts()
1546{
1547 while (!removeList.empty()) {
1548 DPRINTF(O3CPU, "Removing instruction, "
1549 "[tid:%i] [sn:%lli] PC %s\n",
1550 (*removeList.front())->threadNumber,
1551 (*removeList.front())->seqNum,
1552 (*removeList.front())->pcState());
1553
1554 instList.erase(removeList.front());
1555
1556 removeList.pop();
1557 }
1558
1559 removeInstsThisCycle = false;
1560}
1561/*
1562template <class Impl>
1563void
1564FullO3CPU<Impl>::removeAllInsts()
1565{
1566 instList.clear();
1567}
1568*/
1569template <class Impl>
1570void
1571FullO3CPU<Impl>::dumpInsts()
1572{
1573 int num = 0;
1574
1575 ListIt inst_list_it = instList.begin();
1576
1577 cprintf("Dumping Instruction List\n");
1578
1579 while (inst_list_it != instList.end()) {
1580 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1581 "Squashed:%i\n\n",
1582 num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber,
1583 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1584 (*inst_list_it)->isSquashed());
1585 inst_list_it++;
1586 ++num;
1587 }
1588}
1589/*
1590template <class Impl>
1591void
1592FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
1593{
1594 iew.wakeDependents(inst);
1595}
1596*/
1597template <class Impl>
1598void
1599FullO3CPU<Impl>::wakeCPU()
1600{
1601 if (activityRec.active() || tickEvent.scheduled()) {
1602 DPRINTF(Activity, "CPU already running.\n");
1603 return;
1604 }
1605
1606 DPRINTF(Activity, "Waking up CPU\n");
1607
1608 idleCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
1609 numCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
1610
1611 schedule(tickEvent, nextCycle());
1612}
1613
1614#if FULL_SYSTEM
1615template <class Impl>
1616void
1617FullO3CPU<Impl>::wakeup()
1618{
1619 if (this->thread[0]->status() != ThreadContext::Suspended)
1620 return;
1621
1622 this->wakeCPU();
1623
1624 DPRINTF(Quiesce, "Suspended Processor woken\n");
1625 this->threadContexts[0]->activate();
1626}
1627#endif
1628
1629template <class Impl>
1630ThreadID
1631FullO3CPU<Impl>::getFreeTid()
1632{
1633 for (ThreadID tid = 0; tid < numThreads; tid++) {
1634 if (!tids[tid]) {
1635 tids[tid] = true;
1636 return tid;
1637 }
1638 }
1639
1640 return InvalidThreadID;
1641}
1642
1643template <class Impl>
1644void
1645FullO3CPU<Impl>::doContextSwitch()
1646{
1647 if (contextSwitch) {
1648
1649 //ADD CODE TO DEACTIVE THREAD HERE (???)
1650
1651 ThreadID size = cpuWaitList.size();
1652 for (ThreadID tid = 0; tid < size; tid++) {
1653 activateWhenReady(tid);
1654 }
1655
1656 if (cpuWaitList.size() == 0)
1657 contextSwitch = true;
1658 }
1659}
1660
1661template <class Impl>
1662void
1663FullO3CPU<Impl>::updateThreadPriority()
1664{
1665 if (activeThreads.size() > 1) {
1666 //DEFAULT TO ROUND ROBIN SCHEME
1667 //e.g. Move highest priority to end of thread list
1668 list<ThreadID>::iterator list_begin = activeThreads.begin();
1669 list<ThreadID>::iterator list_end = activeThreads.end();
1670
1671 unsigned high_thread = *list_begin;
1672
1673 activeThreads.erase(list_begin);
1674
1675 activeThreads.push_back(high_thread);
1676 }
1677}
1678
1679// Forward declaration of FullO3CPU.
1680template class FullO3CPU<O3CPUImpl>;
| 1107
1108 if (!tickEvent.scheduled())
1109 schedule(tickEvent, nextCycle());
1110 _status = Running;
1111}
1112
1113template <class Impl>
1114void
1115FullO3CPU<Impl>::signalDrained()
1116{
1117 if (++drainCount == NumStages) {
1118 if (tickEvent.scheduled())
1119 tickEvent.squash();
1120
1121 changeState(SimObject::Drained);
1122
1123 BaseCPU::switchOut();
1124
1125 if (drainEvent) {
1126 drainEvent->process();
1127 drainEvent = NULL;
1128 }
1129 }
1130 assert(drainCount <= 5);
1131}
1132
1133template <class Impl>
1134void
1135FullO3CPU<Impl>::switchOut()
1136{
1137 fetch.switchOut();
1138 rename.switchOut();
1139 iew.switchOut();
1140 commit.switchOut();
1141 instList.clear();
1142 while (!removeList.empty()) {
1143 removeList.pop();
1144 }
1145
1146 _status = SwitchedOut;
1147#if USE_CHECKER
1148 if (checker)
1149 checker->switchOut();
1150#endif
1151 if (tickEvent.scheduled())
1152 tickEvent.squash();
1153}
1154
1155template <class Impl>
1156void
1157FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
1158{
1159 // Flush out any old data from the time buffers.
1160 for (int i = 0; i < timeBuffer.getSize(); ++i) {
1161 timeBuffer.advance();
1162 fetchQueue.advance();
1163 decodeQueue.advance();
1164 renameQueue.advance();
1165 iewQueue.advance();
1166 }
1167
1168 activityRec.reset();
1169
1170 BaseCPU::takeOverFrom(oldCPU, fetch.getIcachePort(), iew.getDcachePort());
1171
1172 fetch.takeOverFrom();
1173 decode.takeOverFrom();
1174 rename.takeOverFrom();
1175 iew.takeOverFrom();
1176 commit.takeOverFrom();
1177
1178 assert(!tickEvent.scheduled() || tickEvent.squashed());
1179
1180 // @todo: Figure out how to properly select the tid to put onto
1181 // the active threads list.
1182 ThreadID tid = 0;
1183
1184 list<ThreadID>::iterator isActive =
1185 std::find(activeThreads.begin(), activeThreads.end(), tid);
1186
1187 if (isActive == activeThreads.end()) {
1188 //May Need to Re-code this if the delay variable is the delay
1189 //needed for thread to activate
1190 DPRINTF(O3CPU, "Adding Thread %i to active threads list\n",
1191 tid);
1192
1193 activeThreads.push_back(tid);
1194 }
1195
1196 // Set all statuses to active, schedule the CPU's tick event.
1197 // @todo: Fix up statuses so this is handled properly
1198 ThreadID size = threadContexts.size();
1199 for (ThreadID i = 0; i < size; ++i) {
1200 ThreadContext *tc = threadContexts[i];
1201 if (tc->status() == ThreadContext::Active && _status != Running) {
1202 _status = Running;
1203 reschedule(tickEvent, nextCycle(), true);
1204 }
1205 }
1206 if (!tickEvent.scheduled())
1207 schedule(tickEvent, nextCycle());
1208}
1209
1210template <class Impl>
1211TheISA::MiscReg
1212FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid)
1213{
1214 return this->isa[tid].readMiscRegNoEffect(misc_reg);
1215}
1216
1217template <class Impl>
1218TheISA::MiscReg
1219FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
1220{
1221 miscRegfileReads++;
1222 return this->isa[tid].readMiscReg(misc_reg, tcBase(tid));
1223}
1224
1225template <class Impl>
1226void
1227FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
1228 const TheISA::MiscReg &val, ThreadID tid)
1229{
1230 this->isa[tid].setMiscRegNoEffect(misc_reg, val);
1231}
1232
1233template <class Impl>
1234void
1235FullO3CPU<Impl>::setMiscReg(int misc_reg,
1236 const TheISA::MiscReg &val, ThreadID tid)
1237{
1238 miscRegfileWrites++;
1239 this->isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
1240}
1241
1242template <class Impl>
1243uint64_t
1244FullO3CPU<Impl>::readIntReg(int reg_idx)
1245{
1246 intRegfileReads++;
1247 return regFile.readIntReg(reg_idx);
1248}
1249
1250template <class Impl>
1251FloatReg
1252FullO3CPU<Impl>::readFloatReg(int reg_idx)
1253{
1254 fpRegfileReads++;
1255 return regFile.readFloatReg(reg_idx);
1256}
1257
1258template <class Impl>
1259FloatRegBits
1260FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
1261{
1262 fpRegfileReads++;
1263 return regFile.readFloatRegBits(reg_idx);
1264}
1265
1266template <class Impl>
1267void
1268FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
1269{
1270 intRegfileWrites++;
1271 regFile.setIntReg(reg_idx, val);
1272}
1273
1274template <class Impl>
1275void
1276FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
1277{
1278 fpRegfileWrites++;
1279 regFile.setFloatReg(reg_idx, val);
1280}
1281
1282template <class Impl>
1283void
1284FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
1285{
1286 fpRegfileWrites++;
1287 regFile.setFloatRegBits(reg_idx, val);
1288}
1289
1290template <class Impl>
1291uint64_t
1292FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1293{
1294 intRegfileReads++;
1295 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1296
1297 return regFile.readIntReg(phys_reg);
1298}
1299
1300template <class Impl>
1301float
1302FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
1303{
1304 fpRegfileReads++;
1305 int idx = reg_idx + TheISA::NumIntRegs;
1306 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1307
1308 return regFile.readFloatReg(phys_reg);
1309}
1310
1311template <class Impl>
1312uint64_t
1313FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid)
1314{
1315 fpRegfileReads++;
1316 int idx = reg_idx + TheISA::NumIntRegs;
1317 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1318
1319 return regFile.readFloatRegBits(phys_reg);
1320}
1321
1322template <class Impl>
1323void
1324FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
1325{
1326 intRegfileWrites++;
1327 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1328
1329 regFile.setIntReg(phys_reg, val);
1330}
1331
1332template <class Impl>
1333void
1334FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid)
1335{
1336 fpRegfileWrites++;
1337 int idx = reg_idx + TheISA::NumIntRegs;
1338 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1339
1340 regFile.setFloatReg(phys_reg, val);
1341}
1342
1343template <class Impl>
1344void
1345FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid)
1346{
1347 fpRegfileWrites++;
1348 int idx = reg_idx + TheISA::NumIntRegs;
1349 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1350
1351 regFile.setFloatRegBits(phys_reg, val);
1352}
1353
1354template <class Impl>
1355TheISA::PCState
1356FullO3CPU<Impl>::pcState(ThreadID tid)
1357{
1358 return commit.pcState(tid);
1359}
1360
1361template <class Impl>
1362void
1363FullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid)
1364{
1365 commit.pcState(val, tid);
1366}
1367
1368template <class Impl>
1369Addr
1370FullO3CPU<Impl>::instAddr(ThreadID tid)
1371{
1372 return commit.instAddr(tid);
1373}
1374
1375template <class Impl>
1376Addr
1377FullO3CPU<Impl>::nextInstAddr(ThreadID tid)
1378{
1379 return commit.nextInstAddr(tid);
1380}
1381
1382template <class Impl>
1383MicroPC
1384FullO3CPU<Impl>::microPC(ThreadID tid)
1385{
1386 return commit.microPC(tid);
1387}
1388
1389template <class Impl>
1390void
1391FullO3CPU<Impl>::squashFromTC(ThreadID tid)
1392{
1393 this->thread[tid]->inSyscall = true;
1394 this->commit.generateTCEvent(tid);
1395}
1396
1397template <class Impl>
1398typename FullO3CPU<Impl>::ListIt
1399FullO3CPU<Impl>::addInst(DynInstPtr &inst)
1400{
1401 instList.push_back(inst);
1402
1403 return --(instList.end());
1404}
1405
1406template <class Impl>
1407void
1408FullO3CPU<Impl>::instDone(ThreadID tid)
1409{
1410 // Keep an instruction count.
1411 thread[tid]->numInst++;
1412 thread[tid]->numInsts++;
1413 committedInsts[tid]++;
1414 totalCommittedInsts++;
1415 system->totalNumInsts++;
1416 // Check for instruction-count-based events.
1417 comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1418 system->instEventQueue.serviceEvents(system->totalNumInsts);
1419}
1420
1421template <class Impl>
1422void
1423FullO3CPU<Impl>::addToRemoveList(DynInstPtr &inst)
1424{
1425 removeInstsThisCycle = true;
1426
1427 removeList.push(inst->getInstListIt());
1428}
1429
1430template <class Impl>
1431void
1432FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
1433{
1434 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s "
1435 "[sn:%lli]\n",
1436 inst->threadNumber, inst->pcState(), inst->seqNum);
1437
1438 removeInstsThisCycle = true;
1439
1440 // Remove the front instruction.
1441 removeList.push(inst->getInstListIt());
1442}
1443
1444template <class Impl>
1445void
1446FullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid)
1447{
1448 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1449 " list.\n", tid);
1450
1451 ListIt end_it;
1452
1453 bool rob_empty = false;
1454
1455 if (instList.empty()) {
1456 return;
1457 } else if (rob.isEmpty(/*tid*/)) {
1458 DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1459 end_it = instList.begin();
1460 rob_empty = true;
1461 } else {
1462 end_it = (rob.readTailInst(tid))->getInstListIt();
1463 DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1464 }
1465
1466 removeInstsThisCycle = true;
1467
1468 ListIt inst_it = instList.end();
1469
1470 inst_it--;
1471
1472 // Walk through the instruction list, removing any instructions
1473 // that were inserted after the given instruction iterator, end_it.
1474 while (inst_it != end_it) {
1475 assert(!instList.empty());
1476
1477 squashInstIt(inst_it, tid);
1478
1479 inst_it--;
1480 }
1481
1482 // If the ROB was empty, then we actually need to remove the first
1483 // instruction as well.
1484 if (rob_empty) {
1485 squashInstIt(inst_it, tid);
1486 }
1487}
1488
1489template <class Impl>
1490void
1491FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1492{
1493 assert(!instList.empty());
1494
1495 removeInstsThisCycle = true;
1496
1497 ListIt inst_iter = instList.end();
1498
1499 inst_iter--;
1500
1501 DPRINTF(O3CPU, "Deleting instructions from instruction "
1502 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1503 tid, seq_num, (*inst_iter)->seqNum);
1504
1505 while ((*inst_iter)->seqNum > seq_num) {
1506
1507 bool break_loop = (inst_iter == instList.begin());
1508
1509 squashInstIt(inst_iter, tid);
1510
1511 inst_iter--;
1512
1513 if (break_loop)
1514 break;
1515 }
1516}
1517
1518template <class Impl>
1519inline void
1520FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid)
1521{
1522 if ((*instIt)->threadNumber == tid) {
1523 DPRINTF(O3CPU, "Squashing instruction, "
1524 "[tid:%i] [sn:%lli] PC %s\n",
1525 (*instIt)->threadNumber,
1526 (*instIt)->seqNum,
1527 (*instIt)->pcState());
1528
1529 // Mark it as squashed.
1530 (*instIt)->setSquashed();
1531
1532 // @todo: Formulate a consistent method for deleting
1533 // instructions from the instruction list
1534 // Remove the instruction from the list.
1535 removeList.push(instIt);
1536 }
1537}
1538
1539template <class Impl>
1540void
1541FullO3CPU<Impl>::cleanUpRemovedInsts()
1542{
1543 while (!removeList.empty()) {
1544 DPRINTF(O3CPU, "Removing instruction, "
1545 "[tid:%i] [sn:%lli] PC %s\n",
1546 (*removeList.front())->threadNumber,
1547 (*removeList.front())->seqNum,
1548 (*removeList.front())->pcState());
1549
1550 instList.erase(removeList.front());
1551
1552 removeList.pop();
1553 }
1554
1555 removeInstsThisCycle = false;
1556}
1557/*
1558template <class Impl>
1559void
1560FullO3CPU<Impl>::removeAllInsts()
1561{
1562 instList.clear();
1563}
1564*/
1565template <class Impl>
1566void
1567FullO3CPU<Impl>::dumpInsts()
1568{
1569 int num = 0;
1570
1571 ListIt inst_list_it = instList.begin();
1572
1573 cprintf("Dumping Instruction List\n");
1574
1575 while (inst_list_it != instList.end()) {
1576 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1577 "Squashed:%i\n\n",
1578 num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber,
1579 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1580 (*inst_list_it)->isSquashed());
1581 inst_list_it++;
1582 ++num;
1583 }
1584}
1585/*
1586template <class Impl>
1587void
1588FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
1589{
1590 iew.wakeDependents(inst);
1591}
1592*/
1593template <class Impl>
1594void
1595FullO3CPU<Impl>::wakeCPU()
1596{
1597 if (activityRec.active() || tickEvent.scheduled()) {
1598 DPRINTF(Activity, "CPU already running.\n");
1599 return;
1600 }
1601
1602 DPRINTF(Activity, "Waking up CPU\n");
1603
1604 idleCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
1605 numCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
1606
1607 schedule(tickEvent, nextCycle());
1608}
1609
1610#if FULL_SYSTEM
1611template <class Impl>
1612void
1613FullO3CPU<Impl>::wakeup()
1614{
1615 if (this->thread[0]->status() != ThreadContext::Suspended)
1616 return;
1617
1618 this->wakeCPU();
1619
1620 DPRINTF(Quiesce, "Suspended Processor woken\n");
1621 this->threadContexts[0]->activate();
1622}
1623#endif
1624
1625template <class Impl>
1626ThreadID
1627FullO3CPU<Impl>::getFreeTid()
1628{
1629 for (ThreadID tid = 0; tid < numThreads; tid++) {
1630 if (!tids[tid]) {
1631 tids[tid] = true;
1632 return tid;
1633 }
1634 }
1635
1636 return InvalidThreadID;
1637}
1638
1639template <class Impl>
1640void
1641FullO3CPU<Impl>::doContextSwitch()
1642{
1643 if (contextSwitch) {
1644
1645 //ADD CODE TO DEACTIVE THREAD HERE (???)
1646
1647 ThreadID size = cpuWaitList.size();
1648 for (ThreadID tid = 0; tid < size; tid++) {
1649 activateWhenReady(tid);
1650 }
1651
1652 if (cpuWaitList.size() == 0)
1653 contextSwitch = true;
1654 }
1655}
1656
1657template <class Impl>
1658void
1659FullO3CPU<Impl>::updateThreadPriority()
1660{
1661 if (activeThreads.size() > 1) {
1662 //DEFAULT TO ROUND ROBIN SCHEME
1663 //e.g. Move highest priority to end of thread list
1664 list<ThreadID>::iterator list_begin = activeThreads.begin();
1665 list<ThreadID>::iterator list_end = activeThreads.end();
1666
1667 unsigned high_thread = *list_begin;
1668
1669 activeThreads.erase(list_begin);
1670
1671 activeThreads.push_back(high_thread);
1672 }
1673}
1674
1675// Forward declaration of FullO3CPU.
1676template class FullO3CPU<O3CPUImpl>;
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