1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#include "config/full_system.hh"
33#include "config/use_checker.hh"
34
35#if FULL_SYSTEM
36#include "cpu/quiesce_event.hh"
37#include "sim/system.hh"
38#else
39#include "sim/process.hh"
40#endif
41
42#include "cpu/activity.hh"
43#include "cpu/simple_thread.hh"
44#include "cpu/thread_context.hh"
45#include "cpu/o3/isa_specific.hh"
46#include "cpu/o3/cpu.hh"
47
48#include "sim/root.hh"
49#include "sim/stat_control.hh"
50
51#if USE_CHECKER
52#include "cpu/checker/cpu.hh"
53#endif
54
55using namespace std;
56using namespace TheISA;
57
58BaseO3CPU::BaseO3CPU(Params *params)
59 : BaseCPU(params), cpu_id(0)
60{
61}
62
63void
64BaseO3CPU::regStats()
65{
66 BaseCPU::regStats();
67}
68
69template <class Impl>
70FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
71 : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
72{
73}
74
75template <class Impl>
76void
77FullO3CPU<Impl>::TickEvent::process()
78{
79 cpu->tick();
80}
81
82template <class Impl>
83const char *
84FullO3CPU<Impl>::TickEvent::description()
85{
86 return "FullO3CPU tick event";
87}
88
89template <class Impl>
90FullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent()
91 : Event(&mainEventQueue, CPU_Switch_Pri)
92{
93}
94
95template <class Impl>
96void
97FullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num,
98 FullO3CPU<Impl> *thread_cpu)
99{
100 tid = thread_num;
101 cpu = thread_cpu;
102}
103
104template <class Impl>
105void
106FullO3CPU<Impl>::ActivateThreadEvent::process()
107{
108 cpu->activateThread(tid);
109}
110
111template <class Impl>
112const char *
113FullO3CPU<Impl>::ActivateThreadEvent::description()
114{
115 return "FullO3CPU \"Activate Thread\" event";
116}
117
118template <class Impl>
119FullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent()
120 : Event(&mainEventQueue, CPU_Tick_Pri)
121{
122}
123
124template <class Impl>
125void
126FullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num,
127 FullO3CPU<Impl> *thread_cpu)
128{
129 tid = thread_num;
130 cpu = thread_cpu;
131}
132
133template <class Impl>
134void
135FullO3CPU<Impl>::DeallocateContextEvent::process()
136{
137 cpu->deactivateThread(tid);
138 if (remove)
139 cpu->removeThread(tid);
140}
141
142template <class Impl>
143const char *
144FullO3CPU<Impl>::DeallocateContextEvent::description()
145{
146 return "FullO3CPU \"Deallocate Context\" event";
147}
148
149template <class Impl>
150FullO3CPU<Impl>::FullO3CPU(Params *params)
151 : BaseO3CPU(params),
152 tickEvent(this),
153 removeInstsThisCycle(false),
154 fetch(params),
155 decode(params),
156 rename(params),
157 iew(params),
158 commit(params),
159
160 regFile(params->numPhysIntRegs, params->numPhysFloatRegs),
161
162 freeList(params->numberOfThreads,
163 TheISA::NumIntRegs, params->numPhysIntRegs,
164 TheISA::NumFloatRegs, params->numPhysFloatRegs),
165
166 rob(params->numROBEntries, params->squashWidth,
167 params->smtROBPolicy, params->smtROBThreshold,
168 params->numberOfThreads),
169
170 scoreboard(params->numberOfThreads,
171 TheISA::NumIntRegs, params->numPhysIntRegs,
172 TheISA::NumFloatRegs, params->numPhysFloatRegs,
173 TheISA::NumMiscRegs * number_of_threads,
174 TheISA::ZeroReg),
175
176 timeBuffer(params->backComSize, params->forwardComSize),
177 fetchQueue(params->backComSize, params->forwardComSize),
178 decodeQueue(params->backComSize, params->forwardComSize),
179 renameQueue(params->backComSize, params->forwardComSize),
180 iewQueue(params->backComSize, params->forwardComSize),
181 activityRec(NumStages,
182 params->backComSize + params->forwardComSize,
183 params->activity),
184
185 globalSeqNum(1),
186#if FULL_SYSTEM
187 system(params->system),
188 physmem(system->physmem),
189#endif // FULL_SYSTEM
190 mem(params->mem),
191 drainCount(0),
192 deferRegistration(params->deferRegistration),
193 numThreads(number_of_threads)
194{
195 if (!deferRegistration) {
196 _status = Running;
197 } else {
198 _status = Idle;
199 }
200
201 checker = NULL;
202
203 if (params->checker) {
204#if USE_CHECKER
205 BaseCPU *temp_checker = params->checker;
206 checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
207 checker->setMemory(mem);
208#if FULL_SYSTEM
209 checker->setSystem(params->system);
210#endif
211#else
212 panic("Checker enabled but not compiled in!");
213#endif // USE_CHECKER
214 }
215
216#if !FULL_SYSTEM
217 thread.resize(number_of_threads);
218 tids.resize(number_of_threads);
219#endif
220
221 // The stages also need their CPU pointer setup. However this
222 // must be done at the upper level CPU because they have pointers
223 // to the upper level CPU, and not this FullO3CPU.
224
225 // Set up Pointers to the activeThreads list for each stage
226 fetch.setActiveThreads(&activeThreads);
227 decode.setActiveThreads(&activeThreads);
228 rename.setActiveThreads(&activeThreads);
229 iew.setActiveThreads(&activeThreads);
230 commit.setActiveThreads(&activeThreads);
231
232 // Give each of the stages the time buffer they will use.
233 fetch.setTimeBuffer(&timeBuffer);
234 decode.setTimeBuffer(&timeBuffer);
235 rename.setTimeBuffer(&timeBuffer);
236 iew.setTimeBuffer(&timeBuffer);
237 commit.setTimeBuffer(&timeBuffer);
238
239 // Also setup each of the stages' queues.
240 fetch.setFetchQueue(&fetchQueue);
241 decode.setFetchQueue(&fetchQueue);
242 commit.setFetchQueue(&fetchQueue);
243 decode.setDecodeQueue(&decodeQueue);
244 rename.setDecodeQueue(&decodeQueue);
245 rename.setRenameQueue(&renameQueue);
246 iew.setRenameQueue(&renameQueue);
247 iew.setIEWQueue(&iewQueue);
248 commit.setIEWQueue(&iewQueue);
249 commit.setRenameQueue(&renameQueue);
250
251 commit.setIEWStage(&iew);
252 rename.setIEWStage(&iew);
253 rename.setCommitStage(&commit);
254
255#if !FULL_SYSTEM
256 int active_threads = params->workload.size();
257
258 if (active_threads > Impl::MaxThreads) {
259 panic("Workload Size too large. Increase the 'MaxThreads'"
260 "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or "
261 "edit your workload size.");
262 }
263#else
264 int active_threads = 1;
265#endif
266
267 //Make Sure That this a Valid Architeture
268 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs);
269 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
270
271 rename.setScoreboard(&scoreboard);
272 iew.setScoreboard(&scoreboard);
273
274 // Setup the rename map for whichever stages need it.
275 PhysRegIndex lreg_idx = 0;
276 PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs
277
278 for (int tid=0; tid < numThreads; tid++) {
279 bool bindRegs = (tid <= active_threads - 1);
280
281 commitRenameMap[tid].init(TheISA::NumIntRegs,
282 params->numPhysIntRegs,
283 lreg_idx, //Index for Logical. Regs
284
285 TheISA::NumFloatRegs,
286 params->numPhysFloatRegs,
287 freg_idx, //Index for Float Regs
288
289 TheISA::NumMiscRegs,
290
291 TheISA::ZeroReg,
292 TheISA::ZeroReg,
293
294 tid,
295 false);
296
297 renameMap[tid].init(TheISA::NumIntRegs,
298 params->numPhysIntRegs,
299 lreg_idx, //Index for Logical. Regs
300
301 TheISA::NumFloatRegs,
302 params->numPhysFloatRegs,
303 freg_idx, //Index for Float Regs
304
305 TheISA::NumMiscRegs,
306
307 TheISA::ZeroReg,
308 TheISA::ZeroReg,
309
310 tid,
311 bindRegs);
312
313 activateThreadEvent[tid].init(tid, this);
314 deallocateContextEvent[tid].init(tid, this);
315 }
316
317 rename.setRenameMap(renameMap);
318 commit.setRenameMap(commitRenameMap);
319
320 // Give renameMap & rename stage access to the freeList;
321 for (int i=0; i < numThreads; i++) {
322 renameMap[i].setFreeList(&freeList);
323 }
324 rename.setFreeList(&freeList);
325
326 // Setup the ROB for whichever stages need it.
327 commit.setROB(&rob);
328
329 lastRunningCycle = curTick;
330
331 lastActivatedCycle = -1;
332
333 // Give renameMap & rename stage access to the freeList;
334 //for (int i=0; i < numThreads; i++) {
335 //globalSeqNum[i] = 1;
336 //}
337
338 contextSwitch = false;
339}
340
341template <class Impl>
342FullO3CPU<Impl>::~FullO3CPU()
343{
344}
345
346template <class Impl>
347void
348FullO3CPU<Impl>::fullCPURegStats()
349{
350 BaseO3CPU::regStats();
351
352 // Register any of the O3CPU's stats here.
353 timesIdled
354 .name(name() + ".timesIdled")
355 .desc("Number of times that the entire CPU went into an idle state and"
356 " unscheduled itself")
357 .prereq(timesIdled);
358
359 idleCycles
360 .name(name() + ".idleCycles")
361 .desc("Total number of cycles that the CPU has spent unscheduled due "
362 "to idling")
363 .prereq(idleCycles);
364
365 // Number of Instructions simulated
366 // --------------------------------
367 // Should probably be in Base CPU but need templated
368 // MaxThreads so put in here instead
369 committedInsts
370 .init(numThreads)
371 .name(name() + ".committedInsts")
372 .desc("Number of Instructions Simulated");
373
374 totalCommittedInsts
375 .name(name() + ".committedInsts_total")
376 .desc("Number of Instructions Simulated");
377
378 cpi
379 .name(name() + ".cpi")
380 .desc("CPI: Cycles Per Instruction")
381 .precision(6);
382 cpi = simTicks / committedInsts;
383
384 totalCpi
385 .name(name() + ".cpi_total")
386 .desc("CPI: Total CPI of All Threads")
387 .precision(6);
388 totalCpi = simTicks / totalCommittedInsts;
389
390 ipc
391 .name(name() + ".ipc")
392 .desc("IPC: Instructions Per Cycle")
393 .precision(6);
394 ipc = committedInsts / simTicks;
395
396 totalIpc
397 .name(name() + ".ipc_total")
398 .desc("IPC: Total IPC of All Threads")
399 .precision(6);
400 totalIpc = totalCommittedInsts / simTicks;
401
402}
403
404template <class Impl>
405Port *
406FullO3CPU<Impl>::getPort(const std::string &if_name, int idx)
407{
408 if (if_name == "dcache_port")
409 return iew.getDcachePort();
410 else if (if_name == "icache_port")
411 return fetch.getIcachePort();
412 else
413 panic("No Such Port\n");
414}
415
416template <class Impl>
417void
418FullO3CPU<Impl>::tick()
419{
420 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
421
422 ++numCycles;
423
424// activity = false;
425
426 //Tick each of the stages
427 fetch.tick();
428
429 decode.tick();
430
431 rename.tick();
432
433 iew.tick();
434
435 commit.tick();
436
437#if !FULL_SYSTEM
438 doContextSwitch();
439#endif
440
441 // Now advance the time buffers
442 timeBuffer.advance();
443
444 fetchQueue.advance();
445 decodeQueue.advance();
446 renameQueue.advance();
447 iewQueue.advance();
448
449 activityRec.advance();
450
451 if (removeInstsThisCycle) {
452 cleanUpRemovedInsts();
453 }
454
455 if (!tickEvent.scheduled()) {
456 if (_status == SwitchedOut ||
457 getState() == SimObject::Drained) {
458 DPRINTF(O3CPU, "Switched out!\n");
459 // increment stat
460 lastRunningCycle = curTick;
461 } else if (!activityRec.active() || _status == Idle) {
462 DPRINTF(O3CPU, "Idle!\n");
463 lastRunningCycle = curTick;
464 timesIdled++;
465 } else {
466 tickEvent.schedule(curTick + cycles(1));
467 DPRINTF(O3CPU, "Scheduling next tick!\n");
468 }
469 }
470
471#if !FULL_SYSTEM
472 updateThreadPriority();
473#endif
474
475}
476
477template <class Impl>
478void
479FullO3CPU<Impl>::init()
480{
481 if (!deferRegistration) {
482 registerThreadContexts();
483 }
484
485 // Set inSyscall so that the CPU doesn't squash when initially
486 // setting up registers.
487 for (int i = 0; i < number_of_threads; ++i)
488 thread[i]->inSyscall = true;
489
490 for (int tid=0; tid < number_of_threads; tid++) {
491#if FULL_SYSTEM
492 ThreadContext *src_tc = threadContexts[tid];
493#else
494 ThreadContext *src_tc = thread[tid]->getTC();
495#endif
496 // Threads start in the Suspended State
497 if (src_tc->status() != ThreadContext::Suspended) {
498 continue;
499 }
500
501#if FULL_SYSTEM
502 TheISA::initCPU(src_tc, src_tc->readCpuId());
503#endif
504 }
505
506 // Clear inSyscall.
507 for (int i = 0; i < number_of_threads; ++i)
508 thread[i]->inSyscall = false;
509
510 // Initialize stages.
511 fetch.initStage();
512 iew.initStage();
513 rename.initStage();
514 commit.initStage();
515
516 commit.setThreads(thread);
517}
518
519template <class Impl>
520void
521FullO3CPU<Impl>::activateThread(unsigned tid)
522{
523 list<unsigned>::iterator isActive = find(
524 activeThreads.begin(), activeThreads.end(), tid);
525
526 DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid);
527
528 if (isActive == activeThreads.end()) {
529 DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n",
530 tid);
531
532 activeThreads.push_back(tid);
533 }
534}
535
536template <class Impl>
537void
538FullO3CPU<Impl>::deactivateThread(unsigned tid)
539{
540 //Remove From Active List, if Active
541 list<unsigned>::iterator thread_it =
542 find(activeThreads.begin(), activeThreads.end(), tid);
543
544 DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid);
545
546 if (thread_it != activeThreads.end()) {
547 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
548 tid);
549 activeThreads.erase(thread_it);
550 }
551}
552
553template <class Impl>
554void
555FullO3CPU<Impl>::activateContext(int tid, int delay)
556{
557 // Needs to set each stage to running as well.
558 if (delay){
559 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate "
560 "on cycle %d\n", tid, curTick + cycles(delay));
561 scheduleActivateThreadEvent(tid, delay);
562 } else {
563 activateThread(tid);
564 }
565
566 if (lastActivatedCycle < curTick) {
567 scheduleTickEvent(delay);
568
569 // Be sure to signal that there's some activity so the CPU doesn't
570 // deschedule itself.
571 activityRec.activity();
572 fetch.wakeFromQuiesce();
573
574 lastActivatedCycle = curTick;
575
576 _status = Running;
577 }
578}
579
580template <class Impl>
581bool
582FullO3CPU<Impl>::deallocateContext(int tid, bool remove, int delay)
583{
584 // Schedule removal of thread data from CPU
585 if (delay){
586 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate "
587 "on cycle %d\n", tid, curTick + cycles(delay));
588 scheduleDeallocateContextEvent(tid, remove, delay);
589 return false;
590 } else {
591 deactivateThread(tid);
592 if (remove)
593 removeThread(tid);
594 return true;
595 }
596}
597
598template <class Impl>
599void
600FullO3CPU<Impl>::suspendContext(int tid)
601{
602 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
603 bool deallocated = deallocateContext(tid, false, 1);
604 // If this was the last thread then unschedule the tick event.
605 if ((activeThreads.size() == 1 && !deallocated) || activeThreads.size() == 0)
606 unscheduleTickEvent();
607 _status = Idle;
608}
609
610template <class Impl>
611void
612FullO3CPU<Impl>::haltContext(int tid)
613{
614 //For now, this is the same as deallocate
615 DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
616 deallocateContext(tid, true, 1);
617}
618
619template <class Impl>
620void
621FullO3CPU<Impl>::insertThread(unsigned tid)
622{
623 DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
624 // Will change now that the PC and thread state is internal to the CPU
625 // and not in the ThreadContext.
626#if FULL_SYSTEM
627 ThreadContext *src_tc = system->threadContexts[tid];
628#else
629 ThreadContext *src_tc = tcBase(tid);
630#endif
631
632 //Bind Int Regs to Rename Map
633 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
634 PhysRegIndex phys_reg = freeList.getIntReg();
635
636 renameMap[tid].setEntry(ireg,phys_reg);
637 scoreboard.setReg(phys_reg);
638 }
639
640 //Bind Float Regs to Rename Map
641 for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
642 PhysRegIndex phys_reg = freeList.getFloatReg();
643
644 renameMap[tid].setEntry(freg,phys_reg);
645 scoreboard.setReg(phys_reg);
646 }
647
648 //Copy Thread Data Into RegFile
649 //this->copyFromTC(tid);
650
651 //Set PC/NPC/NNPC
652 setPC(src_tc->readPC(), tid);
653 setNextPC(src_tc->readNextPC(), tid);
654#if ISA_HAS_DELAY_SLOT
655 setNextNPC(src_tc->readNextNPC(), tid);
656#endif
657
658 src_tc->setStatus(ThreadContext::Active);
659
660 activateContext(tid,1);
661
662 //Reset ROB/IQ/LSQ Entries
663 commit.rob->resetEntries();
664 iew.resetEntries();
665}
666
667template <class Impl>
668void
669FullO3CPU<Impl>::removeThread(unsigned tid)
670{
671 DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
672
673 // Copy Thread Data From RegFile
674 // If thread is suspended, it might be re-allocated
675 //this->copyToTC(tid);
676
677 // Unbind Int Regs from Rename Map
678 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
679 PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
680
681 scoreboard.unsetReg(phys_reg);
682 freeList.addReg(phys_reg);
683 }
684
685 // Unbind Float Regs from Rename Map
686 for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
687 PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
688
689 scoreboard.unsetReg(phys_reg);
690 freeList.addReg(phys_reg);
691 }
692
693 // Squash Throughout Pipeline
694 InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum;
695 fetch.squash(0, squash_seq_num, true, tid);
696 decode.squash(tid);
697 rename.squash(squash_seq_num, tid);
698 iew.squash(tid);
699 commit.rob->squash(squash_seq_num, tid);
700
701 assert(iew.ldstQueue.getCount(tid) == 0);
702
703 // Reset ROB/IQ/LSQ Entries
704 if (activeThreads.size() >= 1) {
705 commit.rob->resetEntries();
706 iew.resetEntries();
707 }
708}
709
710
711template <class Impl>
712void
713FullO3CPU<Impl>::activateWhenReady(int tid)
714{
715 DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming"
716 "(e.g. PhysRegs/ROB/IQ/LSQ) \n",
717 tid);
718
719 bool ready = true;
720
721 if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) {
722 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
723 "Phys. Int. Regs.\n",
724 tid);
725 ready = false;
726 } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) {
727 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
728 "Phys. Float. Regs.\n",
729 tid);
730 ready = false;
731 } else if (commit.rob->numFreeEntries() >=
732 commit.rob->entryAmount(activeThreads.size() + 1)) {
733 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
734 "ROB entries.\n",
735 tid);
736 ready = false;
737 } else if (iew.instQueue.numFreeEntries() >=
738 iew.instQueue.entryAmount(activeThreads.size() + 1)) {
739 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
740 "IQ entries.\n",
741 tid);
742 ready = false;
743 } else if (iew.ldstQueue.numFreeEntries() >=
744 iew.ldstQueue.entryAmount(activeThreads.size() + 1)) {
745 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
746 "LSQ entries.\n",
747 tid);
748 ready = false;
749 }
750
751 if (ready) {
752 insertThread(tid);
753
754 contextSwitch = false;
755
756 cpuWaitList.remove(tid);
757 } else {
758 suspendContext(tid);
759
760 //blocks fetch
761 contextSwitch = true;
762
763 //@todo: dont always add to waitlist
764 //do waitlist
765 cpuWaitList.push_back(tid);
766 }
767}
768
769template <class Impl>
770void
771FullO3CPU<Impl>::serialize(std::ostream &os)
772{
773 SimObject::State so_state = SimObject::getState();
774 SERIALIZE_ENUM(so_state);
775 BaseCPU::serialize(os);
776 nameOut(os, csprintf("%s.tickEvent", name()));
777 tickEvent.serialize(os);
778
779 // Use SimpleThread's ability to checkpoint to make it easier to
780 // write out the registers. Also make this static so it doesn't
781 // get instantiated multiple times (causes a panic in statistics).
782 static SimpleThread temp;
783
784 for (int i = 0; i < thread.size(); i++) {
785 nameOut(os, csprintf("%s.xc.%i", name(), i));
786 temp.copyTC(thread[i]->getTC());
787 temp.serialize(os);
788 }
789}
790
791template <class Impl>
792void
793FullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion)
794{
795 SimObject::State so_state;
796 UNSERIALIZE_ENUM(so_state);
797 BaseCPU::unserialize(cp, section);
798 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
799
800 // Use SimpleThread's ability to checkpoint to make it easier to
801 // read in the registers. Also make this static so it doesn't
802 // get instantiated multiple times (causes a panic in statistics).
803 static SimpleThread temp;
804
805 for (int i = 0; i < thread.size(); i++) {
806 temp.copyTC(thread[i]->getTC());
807 temp.unserialize(cp, csprintf("%s.xc.%i", section, i));
808 thread[i]->getTC()->copyArchRegs(temp.getTC());
809 }
810}
811
812template <class Impl>
813unsigned int
814FullO3CPU<Impl>::drain(Event *drain_event)
815{
816 DPRINTF(O3CPU, "Switching out\n");
817 drainCount = 0;
818 fetch.drain();
819 decode.drain();
820 rename.drain();
821 iew.drain();
822 commit.drain();
823
824 // Wake the CPU and record activity so everything can drain out if
825 // the CPU was not able to immediately drain.
826 if (getState() != SimObject::Drained) {
827 // A bit of a hack...set the drainEvent after all the drain()
828 // calls have been made, that way if all of the stages drain
829 // immediately, the signalDrained() function knows not to call
830 // process on the drain event.
831 drainEvent = drain_event;
832
833 wakeCPU();
834 activityRec.activity();
835
836 return 1;
837 } else {
838 return 0;
839 }
840}
841
842template <class Impl>
843void
844FullO3CPU<Impl>::resume()
845{
846#if FULL_SYSTEM
847 assert(system->getMemoryMode() == System::Timing);
848#endif
849 fetch.resume();
850 decode.resume();
851 rename.resume();
852 iew.resume();
853 commit.resume();
854
855 changeState(SimObject::Running);
856
857 if (_status == SwitchedOut || _status == Idle)
858 return;
859
860 if (!tickEvent.scheduled())
861 tickEvent.schedule(curTick);
862 _status = Running;
863}
864
865template <class Impl>
866void
867FullO3CPU<Impl>::signalDrained()
868{
869 if (++drainCount == NumStages) {
870 if (tickEvent.scheduled())
871 tickEvent.squash();
872
873 changeState(SimObject::Drained);
874
875 BaseCPU::switchOut();
876
877 if (drainEvent) {
878 drainEvent->process();
879 drainEvent = NULL;
880 }
881 }
882 assert(drainCount <= 5);
883}
884
885template <class Impl>
886void
887FullO3CPU<Impl>::switchOut()
888{
889 fetch.switchOut();
890 rename.switchOut();
891 iew.switchOut();
892 commit.switchOut();
893 instList.clear();
894 while (!removeList.empty()) {
895 removeList.pop();
896 }
897
898 _status = SwitchedOut;
899#if USE_CHECKER
900 if (checker)
901 checker->switchOut();
902#endif
903 if (tickEvent.scheduled())
904 tickEvent.squash();
905}
906
907template <class Impl>
908void
909FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
910{
911 // Flush out any old data from the time buffers.
912 for (int i = 0; i < timeBuffer.getSize(); ++i) {
913 timeBuffer.advance();
914 fetchQueue.advance();
915 decodeQueue.advance();
916 renameQueue.advance();
917 iewQueue.advance();
918 }
919
920 activityRec.reset();
921
922 BaseCPU::takeOverFrom(oldCPU);
923
924 fetch.takeOverFrom();
925 decode.takeOverFrom();
926 rename.takeOverFrom();
927 iew.takeOverFrom();
928 commit.takeOverFrom();
929
930 assert(!tickEvent.scheduled());
931
932 // @todo: Figure out how to properly select the tid to put onto
933 // the active threads list.
934 int tid = 0;
935
936 list<unsigned>::iterator isActive = find(
937 activeThreads.begin(), activeThreads.end(), tid);
938
939 if (isActive == activeThreads.end()) {
940 //May Need to Re-code this if the delay variable is the delay
941 //needed for thread to activate
942 DPRINTF(O3CPU, "Adding Thread %i to active threads list\n",
943 tid);
944
945 activeThreads.push_back(tid);
946 }
947
948 // Set all statuses to active, schedule the CPU's tick event.
949 // @todo: Fix up statuses so this is handled properly
950 for (int i = 0; i < threadContexts.size(); ++i) {
951 ThreadContext *tc = threadContexts[i];
952 if (tc->status() == ThreadContext::Active && _status != Running) {
953 _status = Running;
954 tickEvent.schedule(curTick);
955 }
956 }
957 if (!tickEvent.scheduled())
958 tickEvent.schedule(curTick);
959
960 Port *peer;
961 Port *icachePort = fetch.getIcachePort();
962 if (icachePort->getPeer() == NULL) {
| 1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#include "config/full_system.hh"
33#include "config/use_checker.hh"
34
35#if FULL_SYSTEM
36#include "cpu/quiesce_event.hh"
37#include "sim/system.hh"
38#else
39#include "sim/process.hh"
40#endif
41
42#include "cpu/activity.hh"
43#include "cpu/simple_thread.hh"
44#include "cpu/thread_context.hh"
45#include "cpu/o3/isa_specific.hh"
46#include "cpu/o3/cpu.hh"
47
48#include "sim/root.hh"
49#include "sim/stat_control.hh"
50
51#if USE_CHECKER
52#include "cpu/checker/cpu.hh"
53#endif
54
55using namespace std;
56using namespace TheISA;
57
58BaseO3CPU::BaseO3CPU(Params *params)
59 : BaseCPU(params), cpu_id(0)
60{
61}
62
63void
64BaseO3CPU::regStats()
65{
66 BaseCPU::regStats();
67}
68
69template <class Impl>
70FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
71 : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
72{
73}
74
75template <class Impl>
76void
77FullO3CPU<Impl>::TickEvent::process()
78{
79 cpu->tick();
80}
81
82template <class Impl>
83const char *
84FullO3CPU<Impl>::TickEvent::description()
85{
86 return "FullO3CPU tick event";
87}
88
89template <class Impl>
90FullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent()
91 : Event(&mainEventQueue, CPU_Switch_Pri)
92{
93}
94
95template <class Impl>
96void
97FullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num,
98 FullO3CPU<Impl> *thread_cpu)
99{
100 tid = thread_num;
101 cpu = thread_cpu;
102}
103
104template <class Impl>
105void
106FullO3CPU<Impl>::ActivateThreadEvent::process()
107{
108 cpu->activateThread(tid);
109}
110
111template <class Impl>
112const char *
113FullO3CPU<Impl>::ActivateThreadEvent::description()
114{
115 return "FullO3CPU \"Activate Thread\" event";
116}
117
118template <class Impl>
119FullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent()
120 : Event(&mainEventQueue, CPU_Tick_Pri)
121{
122}
123
124template <class Impl>
125void
126FullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num,
127 FullO3CPU<Impl> *thread_cpu)
128{
129 tid = thread_num;
130 cpu = thread_cpu;
131}
132
133template <class Impl>
134void
135FullO3CPU<Impl>::DeallocateContextEvent::process()
136{
137 cpu->deactivateThread(tid);
138 if (remove)
139 cpu->removeThread(tid);
140}
141
142template <class Impl>
143const char *
144FullO3CPU<Impl>::DeallocateContextEvent::description()
145{
146 return "FullO3CPU \"Deallocate Context\" event";
147}
148
149template <class Impl>
150FullO3CPU<Impl>::FullO3CPU(Params *params)
151 : BaseO3CPU(params),
152 tickEvent(this),
153 removeInstsThisCycle(false),
154 fetch(params),
155 decode(params),
156 rename(params),
157 iew(params),
158 commit(params),
159
160 regFile(params->numPhysIntRegs, params->numPhysFloatRegs),
161
162 freeList(params->numberOfThreads,
163 TheISA::NumIntRegs, params->numPhysIntRegs,
164 TheISA::NumFloatRegs, params->numPhysFloatRegs),
165
166 rob(params->numROBEntries, params->squashWidth,
167 params->smtROBPolicy, params->smtROBThreshold,
168 params->numberOfThreads),
169
170 scoreboard(params->numberOfThreads,
171 TheISA::NumIntRegs, params->numPhysIntRegs,
172 TheISA::NumFloatRegs, params->numPhysFloatRegs,
173 TheISA::NumMiscRegs * number_of_threads,
174 TheISA::ZeroReg),
175
176 timeBuffer(params->backComSize, params->forwardComSize),
177 fetchQueue(params->backComSize, params->forwardComSize),
178 decodeQueue(params->backComSize, params->forwardComSize),
179 renameQueue(params->backComSize, params->forwardComSize),
180 iewQueue(params->backComSize, params->forwardComSize),
181 activityRec(NumStages,
182 params->backComSize + params->forwardComSize,
183 params->activity),
184
185 globalSeqNum(1),
186#if FULL_SYSTEM
187 system(params->system),
188 physmem(system->physmem),
189#endif // FULL_SYSTEM
190 mem(params->mem),
191 drainCount(0),
192 deferRegistration(params->deferRegistration),
193 numThreads(number_of_threads)
194{
195 if (!deferRegistration) {
196 _status = Running;
197 } else {
198 _status = Idle;
199 }
200
201 checker = NULL;
202
203 if (params->checker) {
204#if USE_CHECKER
205 BaseCPU *temp_checker = params->checker;
206 checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
207 checker->setMemory(mem);
208#if FULL_SYSTEM
209 checker->setSystem(params->system);
210#endif
211#else
212 panic("Checker enabled but not compiled in!");
213#endif // USE_CHECKER
214 }
215
216#if !FULL_SYSTEM
217 thread.resize(number_of_threads);
218 tids.resize(number_of_threads);
219#endif
220
221 // The stages also need their CPU pointer setup. However this
222 // must be done at the upper level CPU because they have pointers
223 // to the upper level CPU, and not this FullO3CPU.
224
225 // Set up Pointers to the activeThreads list for each stage
226 fetch.setActiveThreads(&activeThreads);
227 decode.setActiveThreads(&activeThreads);
228 rename.setActiveThreads(&activeThreads);
229 iew.setActiveThreads(&activeThreads);
230 commit.setActiveThreads(&activeThreads);
231
232 // Give each of the stages the time buffer they will use.
233 fetch.setTimeBuffer(&timeBuffer);
234 decode.setTimeBuffer(&timeBuffer);
235 rename.setTimeBuffer(&timeBuffer);
236 iew.setTimeBuffer(&timeBuffer);
237 commit.setTimeBuffer(&timeBuffer);
238
239 // Also setup each of the stages' queues.
240 fetch.setFetchQueue(&fetchQueue);
241 decode.setFetchQueue(&fetchQueue);
242 commit.setFetchQueue(&fetchQueue);
243 decode.setDecodeQueue(&decodeQueue);
244 rename.setDecodeQueue(&decodeQueue);
245 rename.setRenameQueue(&renameQueue);
246 iew.setRenameQueue(&renameQueue);
247 iew.setIEWQueue(&iewQueue);
248 commit.setIEWQueue(&iewQueue);
249 commit.setRenameQueue(&renameQueue);
250
251 commit.setIEWStage(&iew);
252 rename.setIEWStage(&iew);
253 rename.setCommitStage(&commit);
254
255#if !FULL_SYSTEM
256 int active_threads = params->workload.size();
257
258 if (active_threads > Impl::MaxThreads) {
259 panic("Workload Size too large. Increase the 'MaxThreads'"
260 "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or "
261 "edit your workload size.");
262 }
263#else
264 int active_threads = 1;
265#endif
266
267 //Make Sure That this a Valid Architeture
268 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs);
269 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
270
271 rename.setScoreboard(&scoreboard);
272 iew.setScoreboard(&scoreboard);
273
274 // Setup the rename map for whichever stages need it.
275 PhysRegIndex lreg_idx = 0;
276 PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs
277
278 for (int tid=0; tid < numThreads; tid++) {
279 bool bindRegs = (tid <= active_threads - 1);
280
281 commitRenameMap[tid].init(TheISA::NumIntRegs,
282 params->numPhysIntRegs,
283 lreg_idx, //Index for Logical. Regs
284
285 TheISA::NumFloatRegs,
286 params->numPhysFloatRegs,
287 freg_idx, //Index for Float Regs
288
289 TheISA::NumMiscRegs,
290
291 TheISA::ZeroReg,
292 TheISA::ZeroReg,
293
294 tid,
295 false);
296
297 renameMap[tid].init(TheISA::NumIntRegs,
298 params->numPhysIntRegs,
299 lreg_idx, //Index for Logical. Regs
300
301 TheISA::NumFloatRegs,
302 params->numPhysFloatRegs,
303 freg_idx, //Index for Float Regs
304
305 TheISA::NumMiscRegs,
306
307 TheISA::ZeroReg,
308 TheISA::ZeroReg,
309
310 tid,
311 bindRegs);
312
313 activateThreadEvent[tid].init(tid, this);
314 deallocateContextEvent[tid].init(tid, this);
315 }
316
317 rename.setRenameMap(renameMap);
318 commit.setRenameMap(commitRenameMap);
319
320 // Give renameMap & rename stage access to the freeList;
321 for (int i=0; i < numThreads; i++) {
322 renameMap[i].setFreeList(&freeList);
323 }
324 rename.setFreeList(&freeList);
325
326 // Setup the ROB for whichever stages need it.
327 commit.setROB(&rob);
328
329 lastRunningCycle = curTick;
330
331 lastActivatedCycle = -1;
332
333 // Give renameMap & rename stage access to the freeList;
334 //for (int i=0; i < numThreads; i++) {
335 //globalSeqNum[i] = 1;
336 //}
337
338 contextSwitch = false;
339}
340
341template <class Impl>
342FullO3CPU<Impl>::~FullO3CPU()
343{
344}
345
346template <class Impl>
347void
348FullO3CPU<Impl>::fullCPURegStats()
349{
350 BaseO3CPU::regStats();
351
352 // Register any of the O3CPU's stats here.
353 timesIdled
354 .name(name() + ".timesIdled")
355 .desc("Number of times that the entire CPU went into an idle state and"
356 " unscheduled itself")
357 .prereq(timesIdled);
358
359 idleCycles
360 .name(name() + ".idleCycles")
361 .desc("Total number of cycles that the CPU has spent unscheduled due "
362 "to idling")
363 .prereq(idleCycles);
364
365 // Number of Instructions simulated
366 // --------------------------------
367 // Should probably be in Base CPU but need templated
368 // MaxThreads so put in here instead
369 committedInsts
370 .init(numThreads)
371 .name(name() + ".committedInsts")
372 .desc("Number of Instructions Simulated");
373
374 totalCommittedInsts
375 .name(name() + ".committedInsts_total")
376 .desc("Number of Instructions Simulated");
377
378 cpi
379 .name(name() + ".cpi")
380 .desc("CPI: Cycles Per Instruction")
381 .precision(6);
382 cpi = simTicks / committedInsts;
383
384 totalCpi
385 .name(name() + ".cpi_total")
386 .desc("CPI: Total CPI of All Threads")
387 .precision(6);
388 totalCpi = simTicks / totalCommittedInsts;
389
390 ipc
391 .name(name() + ".ipc")
392 .desc("IPC: Instructions Per Cycle")
393 .precision(6);
394 ipc = committedInsts / simTicks;
395
396 totalIpc
397 .name(name() + ".ipc_total")
398 .desc("IPC: Total IPC of All Threads")
399 .precision(6);
400 totalIpc = totalCommittedInsts / simTicks;
401
402}
403
404template <class Impl>
405Port *
406FullO3CPU<Impl>::getPort(const std::string &if_name, int idx)
407{
408 if (if_name == "dcache_port")
409 return iew.getDcachePort();
410 else if (if_name == "icache_port")
411 return fetch.getIcachePort();
412 else
413 panic("No Such Port\n");
414}
415
416template <class Impl>
417void
418FullO3CPU<Impl>::tick()
419{
420 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
421
422 ++numCycles;
423
424// activity = false;
425
426 //Tick each of the stages
427 fetch.tick();
428
429 decode.tick();
430
431 rename.tick();
432
433 iew.tick();
434
435 commit.tick();
436
437#if !FULL_SYSTEM
438 doContextSwitch();
439#endif
440
441 // Now advance the time buffers
442 timeBuffer.advance();
443
444 fetchQueue.advance();
445 decodeQueue.advance();
446 renameQueue.advance();
447 iewQueue.advance();
448
449 activityRec.advance();
450
451 if (removeInstsThisCycle) {
452 cleanUpRemovedInsts();
453 }
454
455 if (!tickEvent.scheduled()) {
456 if (_status == SwitchedOut ||
457 getState() == SimObject::Drained) {
458 DPRINTF(O3CPU, "Switched out!\n");
459 // increment stat
460 lastRunningCycle = curTick;
461 } else if (!activityRec.active() || _status == Idle) {
462 DPRINTF(O3CPU, "Idle!\n");
463 lastRunningCycle = curTick;
464 timesIdled++;
465 } else {
466 tickEvent.schedule(curTick + cycles(1));
467 DPRINTF(O3CPU, "Scheduling next tick!\n");
468 }
469 }
470
471#if !FULL_SYSTEM
472 updateThreadPriority();
473#endif
474
475}
476
477template <class Impl>
478void
479FullO3CPU<Impl>::init()
480{
481 if (!deferRegistration) {
482 registerThreadContexts();
483 }
484
485 // Set inSyscall so that the CPU doesn't squash when initially
486 // setting up registers.
487 for (int i = 0; i < number_of_threads; ++i)
488 thread[i]->inSyscall = true;
489
490 for (int tid=0; tid < number_of_threads; tid++) {
491#if FULL_SYSTEM
492 ThreadContext *src_tc = threadContexts[tid];
493#else
494 ThreadContext *src_tc = thread[tid]->getTC();
495#endif
496 // Threads start in the Suspended State
497 if (src_tc->status() != ThreadContext::Suspended) {
498 continue;
499 }
500
501#if FULL_SYSTEM
502 TheISA::initCPU(src_tc, src_tc->readCpuId());
503#endif
504 }
505
506 // Clear inSyscall.
507 for (int i = 0; i < number_of_threads; ++i)
508 thread[i]->inSyscall = false;
509
510 // Initialize stages.
511 fetch.initStage();
512 iew.initStage();
513 rename.initStage();
514 commit.initStage();
515
516 commit.setThreads(thread);
517}
518
519template <class Impl>
520void
521FullO3CPU<Impl>::activateThread(unsigned tid)
522{
523 list<unsigned>::iterator isActive = find(
524 activeThreads.begin(), activeThreads.end(), tid);
525
526 DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid);
527
528 if (isActive == activeThreads.end()) {
529 DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n",
530 tid);
531
532 activeThreads.push_back(tid);
533 }
534}
535
536template <class Impl>
537void
538FullO3CPU<Impl>::deactivateThread(unsigned tid)
539{
540 //Remove From Active List, if Active
541 list<unsigned>::iterator thread_it =
542 find(activeThreads.begin(), activeThreads.end(), tid);
543
544 DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid);
545
546 if (thread_it != activeThreads.end()) {
547 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
548 tid);
549 activeThreads.erase(thread_it);
550 }
551}
552
553template <class Impl>
554void
555FullO3CPU<Impl>::activateContext(int tid, int delay)
556{
557 // Needs to set each stage to running as well.
558 if (delay){
559 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate "
560 "on cycle %d\n", tid, curTick + cycles(delay));
561 scheduleActivateThreadEvent(tid, delay);
562 } else {
563 activateThread(tid);
564 }
565
566 if (lastActivatedCycle < curTick) {
567 scheduleTickEvent(delay);
568
569 // Be sure to signal that there's some activity so the CPU doesn't
570 // deschedule itself.
571 activityRec.activity();
572 fetch.wakeFromQuiesce();
573
574 lastActivatedCycle = curTick;
575
576 _status = Running;
577 }
578}
579
580template <class Impl>
581bool
582FullO3CPU<Impl>::deallocateContext(int tid, bool remove, int delay)
583{
584 // Schedule removal of thread data from CPU
585 if (delay){
586 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate "
587 "on cycle %d\n", tid, curTick + cycles(delay));
588 scheduleDeallocateContextEvent(tid, remove, delay);
589 return false;
590 } else {
591 deactivateThread(tid);
592 if (remove)
593 removeThread(tid);
594 return true;
595 }
596}
597
598template <class Impl>
599void
600FullO3CPU<Impl>::suspendContext(int tid)
601{
602 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
603 bool deallocated = deallocateContext(tid, false, 1);
604 // If this was the last thread then unschedule the tick event.
605 if ((activeThreads.size() == 1 && !deallocated) || activeThreads.size() == 0)
606 unscheduleTickEvent();
607 _status = Idle;
608}
609
610template <class Impl>
611void
612FullO3CPU<Impl>::haltContext(int tid)
613{
614 //For now, this is the same as deallocate
615 DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
616 deallocateContext(tid, true, 1);
617}
618
619template <class Impl>
620void
621FullO3CPU<Impl>::insertThread(unsigned tid)
622{
623 DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
624 // Will change now that the PC and thread state is internal to the CPU
625 // and not in the ThreadContext.
626#if FULL_SYSTEM
627 ThreadContext *src_tc = system->threadContexts[tid];
628#else
629 ThreadContext *src_tc = tcBase(tid);
630#endif
631
632 //Bind Int Regs to Rename Map
633 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
634 PhysRegIndex phys_reg = freeList.getIntReg();
635
636 renameMap[tid].setEntry(ireg,phys_reg);
637 scoreboard.setReg(phys_reg);
638 }
639
640 //Bind Float Regs to Rename Map
641 for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
642 PhysRegIndex phys_reg = freeList.getFloatReg();
643
644 renameMap[tid].setEntry(freg,phys_reg);
645 scoreboard.setReg(phys_reg);
646 }
647
648 //Copy Thread Data Into RegFile
649 //this->copyFromTC(tid);
650
651 //Set PC/NPC/NNPC
652 setPC(src_tc->readPC(), tid);
653 setNextPC(src_tc->readNextPC(), tid);
654#if ISA_HAS_DELAY_SLOT
655 setNextNPC(src_tc->readNextNPC(), tid);
656#endif
657
658 src_tc->setStatus(ThreadContext::Active);
659
660 activateContext(tid,1);
661
662 //Reset ROB/IQ/LSQ Entries
663 commit.rob->resetEntries();
664 iew.resetEntries();
665}
666
667template <class Impl>
668void
669FullO3CPU<Impl>::removeThread(unsigned tid)
670{
671 DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
672
673 // Copy Thread Data From RegFile
674 // If thread is suspended, it might be re-allocated
675 //this->copyToTC(tid);
676
677 // Unbind Int Regs from Rename Map
678 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
679 PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
680
681 scoreboard.unsetReg(phys_reg);
682 freeList.addReg(phys_reg);
683 }
684
685 // Unbind Float Regs from Rename Map
686 for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
687 PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
688
689 scoreboard.unsetReg(phys_reg);
690 freeList.addReg(phys_reg);
691 }
692
693 // Squash Throughout Pipeline
694 InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum;
695 fetch.squash(0, squash_seq_num, true, tid);
696 decode.squash(tid);
697 rename.squash(squash_seq_num, tid);
698 iew.squash(tid);
699 commit.rob->squash(squash_seq_num, tid);
700
701 assert(iew.ldstQueue.getCount(tid) == 0);
702
703 // Reset ROB/IQ/LSQ Entries
704 if (activeThreads.size() >= 1) {
705 commit.rob->resetEntries();
706 iew.resetEntries();
707 }
708}
709
710
711template <class Impl>
712void
713FullO3CPU<Impl>::activateWhenReady(int tid)
714{
715 DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming"
716 "(e.g. PhysRegs/ROB/IQ/LSQ) \n",
717 tid);
718
719 bool ready = true;
720
721 if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) {
722 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
723 "Phys. Int. Regs.\n",
724 tid);
725 ready = false;
726 } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) {
727 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
728 "Phys. Float. Regs.\n",
729 tid);
730 ready = false;
731 } else if (commit.rob->numFreeEntries() >=
732 commit.rob->entryAmount(activeThreads.size() + 1)) {
733 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
734 "ROB entries.\n",
735 tid);
736 ready = false;
737 } else if (iew.instQueue.numFreeEntries() >=
738 iew.instQueue.entryAmount(activeThreads.size() + 1)) {
739 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
740 "IQ entries.\n",
741 tid);
742 ready = false;
743 } else if (iew.ldstQueue.numFreeEntries() >=
744 iew.ldstQueue.entryAmount(activeThreads.size() + 1)) {
745 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
746 "LSQ entries.\n",
747 tid);
748 ready = false;
749 }
750
751 if (ready) {
752 insertThread(tid);
753
754 contextSwitch = false;
755
756 cpuWaitList.remove(tid);
757 } else {
758 suspendContext(tid);
759
760 //blocks fetch
761 contextSwitch = true;
762
763 //@todo: dont always add to waitlist
764 //do waitlist
765 cpuWaitList.push_back(tid);
766 }
767}
768
769template <class Impl>
770void
771FullO3CPU<Impl>::serialize(std::ostream &os)
772{
773 SimObject::State so_state = SimObject::getState();
774 SERIALIZE_ENUM(so_state);
775 BaseCPU::serialize(os);
776 nameOut(os, csprintf("%s.tickEvent", name()));
777 tickEvent.serialize(os);
778
779 // Use SimpleThread's ability to checkpoint to make it easier to
780 // write out the registers. Also make this static so it doesn't
781 // get instantiated multiple times (causes a panic in statistics).
782 static SimpleThread temp;
783
784 for (int i = 0; i < thread.size(); i++) {
785 nameOut(os, csprintf("%s.xc.%i", name(), i));
786 temp.copyTC(thread[i]->getTC());
787 temp.serialize(os);
788 }
789}
790
791template <class Impl>
792void
793FullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion)
794{
795 SimObject::State so_state;
796 UNSERIALIZE_ENUM(so_state);
797 BaseCPU::unserialize(cp, section);
798 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
799
800 // Use SimpleThread's ability to checkpoint to make it easier to
801 // read in the registers. Also make this static so it doesn't
802 // get instantiated multiple times (causes a panic in statistics).
803 static SimpleThread temp;
804
805 for (int i = 0; i < thread.size(); i++) {
806 temp.copyTC(thread[i]->getTC());
807 temp.unserialize(cp, csprintf("%s.xc.%i", section, i));
808 thread[i]->getTC()->copyArchRegs(temp.getTC());
809 }
810}
811
812template <class Impl>
813unsigned int
814FullO3CPU<Impl>::drain(Event *drain_event)
815{
816 DPRINTF(O3CPU, "Switching out\n");
817 drainCount = 0;
818 fetch.drain();
819 decode.drain();
820 rename.drain();
821 iew.drain();
822 commit.drain();
823
824 // Wake the CPU and record activity so everything can drain out if
825 // the CPU was not able to immediately drain.
826 if (getState() != SimObject::Drained) {
827 // A bit of a hack...set the drainEvent after all the drain()
828 // calls have been made, that way if all of the stages drain
829 // immediately, the signalDrained() function knows not to call
830 // process on the drain event.
831 drainEvent = drain_event;
832
833 wakeCPU();
834 activityRec.activity();
835
836 return 1;
837 } else {
838 return 0;
839 }
840}
841
842template <class Impl>
843void
844FullO3CPU<Impl>::resume()
845{
846#if FULL_SYSTEM
847 assert(system->getMemoryMode() == System::Timing);
848#endif
849 fetch.resume();
850 decode.resume();
851 rename.resume();
852 iew.resume();
853 commit.resume();
854
855 changeState(SimObject::Running);
856
857 if (_status == SwitchedOut || _status == Idle)
858 return;
859
860 if (!tickEvent.scheduled())
861 tickEvent.schedule(curTick);
862 _status = Running;
863}
864
865template <class Impl>
866void
867FullO3CPU<Impl>::signalDrained()
868{
869 if (++drainCount == NumStages) {
870 if (tickEvent.scheduled())
871 tickEvent.squash();
872
873 changeState(SimObject::Drained);
874
875 BaseCPU::switchOut();
876
877 if (drainEvent) {
878 drainEvent->process();
879 drainEvent = NULL;
880 }
881 }
882 assert(drainCount <= 5);
883}
884
885template <class Impl>
886void
887FullO3CPU<Impl>::switchOut()
888{
889 fetch.switchOut();
890 rename.switchOut();
891 iew.switchOut();
892 commit.switchOut();
893 instList.clear();
894 while (!removeList.empty()) {
895 removeList.pop();
896 }
897
898 _status = SwitchedOut;
899#if USE_CHECKER
900 if (checker)
901 checker->switchOut();
902#endif
903 if (tickEvent.scheduled())
904 tickEvent.squash();
905}
906
907template <class Impl>
908void
909FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
910{
911 // Flush out any old data from the time buffers.
912 for (int i = 0; i < timeBuffer.getSize(); ++i) {
913 timeBuffer.advance();
914 fetchQueue.advance();
915 decodeQueue.advance();
916 renameQueue.advance();
917 iewQueue.advance();
918 }
919
920 activityRec.reset();
921
922 BaseCPU::takeOverFrom(oldCPU);
923
924 fetch.takeOverFrom();
925 decode.takeOverFrom();
926 rename.takeOverFrom();
927 iew.takeOverFrom();
928 commit.takeOverFrom();
929
930 assert(!tickEvent.scheduled());
931
932 // @todo: Figure out how to properly select the tid to put onto
933 // the active threads list.
934 int tid = 0;
935
936 list<unsigned>::iterator isActive = find(
937 activeThreads.begin(), activeThreads.end(), tid);
938
939 if (isActive == activeThreads.end()) {
940 //May Need to Re-code this if the delay variable is the delay
941 //needed for thread to activate
942 DPRINTF(O3CPU, "Adding Thread %i to active threads list\n",
943 tid);
944
945 activeThreads.push_back(tid);
946 }
947
948 // Set all statuses to active, schedule the CPU's tick event.
949 // @todo: Fix up statuses so this is handled properly
950 for (int i = 0; i < threadContexts.size(); ++i) {
951 ThreadContext *tc = threadContexts[i];
952 if (tc->status() == ThreadContext::Active && _status != Running) {
953 _status = Running;
954 tickEvent.schedule(curTick);
955 }
956 }
957 if (!tickEvent.scheduled())
958 tickEvent.schedule(curTick);
959
960 Port *peer;
961 Port *icachePort = fetch.getIcachePort();
962 if (icachePort->getPeer() == NULL) {
|
973 dcachePort->setPeer(peer);
974 } else {
975 peer = dcachePort->getPeer();
976 }
977 peer->setPeer(dcachePort);
978}
979
980template <class Impl>
981uint64_t
982FullO3CPU<Impl>::readIntReg(int reg_idx)
983{
984 return regFile.readIntReg(reg_idx);
985}
986
987template <class Impl>
988FloatReg
989FullO3CPU<Impl>::readFloatReg(int reg_idx, int width)
990{
991 return regFile.readFloatReg(reg_idx, width);
992}
993
994template <class Impl>
995FloatReg
996FullO3CPU<Impl>::readFloatReg(int reg_idx)
997{
998 return regFile.readFloatReg(reg_idx);
999}
1000
1001template <class Impl>
1002FloatRegBits
1003FullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width)
1004{
1005 return regFile.readFloatRegBits(reg_idx, width);
1006}
1007
1008template <class Impl>
1009FloatRegBits
1010FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
1011{
1012 return regFile.readFloatRegBits(reg_idx);
1013}
1014
1015template <class Impl>
1016void
1017FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
1018{
1019 regFile.setIntReg(reg_idx, val);
1020}
1021
1022template <class Impl>
1023void
1024FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width)
1025{
1026 regFile.setFloatReg(reg_idx, val, width);
1027}
1028
1029template <class Impl>
1030void
1031FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
1032{
1033 regFile.setFloatReg(reg_idx, val);
1034}
1035
1036template <class Impl>
1037void
1038FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width)
1039{
1040 regFile.setFloatRegBits(reg_idx, val, width);
1041}
1042
1043template <class Impl>
1044void
1045FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
1046{
1047 regFile.setFloatRegBits(reg_idx, val);
1048}
1049
1050template <class Impl>
1051uint64_t
1052FullO3CPU<Impl>::readArchIntReg(int reg_idx, unsigned tid)
1053{
1054 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1055
1056 return regFile.readIntReg(phys_reg);
1057}
1058
1059template <class Impl>
1060float
1061FullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, unsigned tid)
1062{
1063 int idx = reg_idx + TheISA::FP_Base_DepTag;
1064 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1065
1066 return regFile.readFloatReg(phys_reg);
1067}
1068
1069template <class Impl>
1070double
1071FullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, unsigned tid)
1072{
1073 int idx = reg_idx + TheISA::FP_Base_DepTag;
1074 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1075
1076 return regFile.readFloatReg(phys_reg, 64);
1077}
1078
1079template <class Impl>
1080uint64_t
1081FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, unsigned tid)
1082{
1083 int idx = reg_idx + TheISA::FP_Base_DepTag;
1084 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1085
1086 return regFile.readFloatRegBits(phys_reg);
1087}
1088
1089template <class Impl>
1090void
1091FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, unsigned tid)
1092{
1093 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1094
1095 regFile.setIntReg(phys_reg, val);
1096}
1097
1098template <class Impl>
1099void
1100FullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, unsigned tid)
1101{
1102 int idx = reg_idx + TheISA::FP_Base_DepTag;
1103 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1104
1105 regFile.setFloatReg(phys_reg, val);
1106}
1107
1108template <class Impl>
1109void
1110FullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, unsigned tid)
1111{
1112 int idx = reg_idx + TheISA::FP_Base_DepTag;
1113 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1114
1115 regFile.setFloatReg(phys_reg, val, 64);
1116}
1117
1118template <class Impl>
1119void
1120FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid)
1121{
1122 int idx = reg_idx + TheISA::FP_Base_DepTag;
1123 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1124
1125 regFile.setFloatRegBits(phys_reg, val);
1126}
1127
1128template <class Impl>
1129uint64_t
1130FullO3CPU<Impl>::readPC(unsigned tid)
1131{
1132 return commit.readPC(tid);
1133}
1134
1135template <class Impl>
1136void
1137FullO3CPU<Impl>::setPC(Addr new_PC,unsigned tid)
1138{
1139 commit.setPC(new_PC, tid);
1140}
1141
1142template <class Impl>
1143uint64_t
1144FullO3CPU<Impl>::readNextPC(unsigned tid)
1145{
1146 return commit.readNextPC(tid);
1147}
1148
1149template <class Impl>
1150void
1151FullO3CPU<Impl>::setNextPC(uint64_t val,unsigned tid)
1152{
1153 commit.setNextPC(val, tid);
1154}
1155
1156template <class Impl>
1157uint64_t
1158FullO3CPU<Impl>::readNextNPC(unsigned tid)
1159{
1160 return commit.readNextNPC(tid);
1161}
1162
1163template <class Impl>
1164void
1165FullO3CPU<Impl>::setNextNPC(uint64_t val,unsigned tid)
1166{
1167 commit.setNextNPC(val, tid);
1168}
1169
1170template <class Impl>
1171typename FullO3CPU<Impl>::ListIt
1172FullO3CPU<Impl>::addInst(DynInstPtr &inst)
1173{
1174 instList.push_back(inst);
1175
1176 return --(instList.end());
1177}
1178
1179template <class Impl>
1180void
1181FullO3CPU<Impl>::instDone(unsigned tid)
1182{
1183 // Keep an instruction count.
1184 thread[tid]->numInst++;
1185 thread[tid]->numInsts++;
1186 committedInsts[tid]++;
1187 totalCommittedInsts++;
1188
1189 // Check for instruction-count-based events.
1190 comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1191}
1192
1193template <class Impl>
1194void
1195FullO3CPU<Impl>::addToRemoveList(DynInstPtr &inst)
1196{
1197 removeInstsThisCycle = true;
1198
1199 removeList.push(inst->getInstListIt());
1200}
1201
1202template <class Impl>
1203void
1204FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
1205{
1206 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %#x "
1207 "[sn:%lli]\n",
1208 inst->threadNumber, inst->readPC(), inst->seqNum);
1209
1210 removeInstsThisCycle = true;
1211
1212 // Remove the front instruction.
1213 removeList.push(inst->getInstListIt());
1214}
1215
1216template <class Impl>
1217void
1218FullO3CPU<Impl>::removeInstsNotInROB(unsigned tid,
1219 bool squash_delay_slot,
1220 const InstSeqNum &delay_slot_seq_num)
1221{
1222 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1223 " list.\n", tid);
1224
1225 ListIt end_it;
1226
1227 bool rob_empty = false;
1228
1229 if (instList.empty()) {
1230 return;
1231 } else if (rob.isEmpty(/*tid*/)) {
1232 DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1233 end_it = instList.begin();
1234 rob_empty = true;
1235 } else {
1236 end_it = (rob.readTailInst(tid))->getInstListIt();
1237 DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1238 }
1239
1240 removeInstsThisCycle = true;
1241
1242 ListIt inst_it = instList.end();
1243
1244 inst_it--;
1245
1246 // Walk through the instruction list, removing any instructions
1247 // that were inserted after the given instruction iterator, end_it.
1248 while (inst_it != end_it) {
1249 assert(!instList.empty());
1250
1251#if ISA_HAS_DELAY_SLOT
1252 if(!squash_delay_slot &&
1253 delay_slot_seq_num >= (*inst_it)->seqNum) {
1254 break;
1255 }
1256#endif
1257 squashInstIt(inst_it, tid);
1258
1259 inst_it--;
1260 }
1261
1262 // If the ROB was empty, then we actually need to remove the first
1263 // instruction as well.
1264 if (rob_empty) {
1265 squashInstIt(inst_it, tid);
1266 }
1267}
1268
1269template <class Impl>
1270void
1271FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num,
1272 unsigned tid)
1273{
1274 assert(!instList.empty());
1275
1276 removeInstsThisCycle = true;
1277
1278 ListIt inst_iter = instList.end();
1279
1280 inst_iter--;
1281
1282 DPRINTF(O3CPU, "Deleting instructions from instruction "
1283 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1284 tid, seq_num, (*inst_iter)->seqNum);
1285
1286 while ((*inst_iter)->seqNum > seq_num) {
1287
1288 bool break_loop = (inst_iter == instList.begin());
1289
1290 squashInstIt(inst_iter, tid);
1291
1292 inst_iter--;
1293
1294 if (break_loop)
1295 break;
1296 }
1297}
1298
1299template <class Impl>
1300inline void
1301FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, const unsigned &tid)
1302{
1303 if ((*instIt)->threadNumber == tid) {
1304 DPRINTF(O3CPU, "Squashing instruction, "
1305 "[tid:%i] [sn:%lli] PC %#x\n",
1306 (*instIt)->threadNumber,
1307 (*instIt)->seqNum,
1308 (*instIt)->readPC());
1309
1310 // Mark it as squashed.
1311 (*instIt)->setSquashed();
1312
1313 // @todo: Formulate a consistent method for deleting
1314 // instructions from the instruction list
1315 // Remove the instruction from the list.
1316 removeList.push(instIt);
1317 }
1318}
1319
1320template <class Impl>
1321void
1322FullO3CPU<Impl>::cleanUpRemovedInsts()
1323{
1324 while (!removeList.empty()) {
1325 DPRINTF(O3CPU, "Removing instruction, "
1326 "[tid:%i] [sn:%lli] PC %#x\n",
1327 (*removeList.front())->threadNumber,
1328 (*removeList.front())->seqNum,
1329 (*removeList.front())->readPC());
1330
1331 instList.erase(removeList.front());
1332
1333 removeList.pop();
1334 }
1335
1336 removeInstsThisCycle = false;
1337}
1338/*
1339template <class Impl>
1340void
1341FullO3CPU<Impl>::removeAllInsts()
1342{
1343 instList.clear();
1344}
1345*/
1346template <class Impl>
1347void
1348FullO3CPU<Impl>::dumpInsts()
1349{
1350 int num = 0;
1351
1352 ListIt inst_list_it = instList.begin();
1353
1354 cprintf("Dumping Instruction List\n");
1355
1356 while (inst_list_it != instList.end()) {
1357 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1358 "Squashed:%i\n\n",
1359 num, (*inst_list_it)->readPC(), (*inst_list_it)->threadNumber,
1360 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1361 (*inst_list_it)->isSquashed());
1362 inst_list_it++;
1363 ++num;
1364 }
1365}
1366/*
1367template <class Impl>
1368void
1369FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
1370{
1371 iew.wakeDependents(inst);
1372}
1373*/
1374template <class Impl>
1375void
1376FullO3CPU<Impl>::wakeCPU()
1377{
1378 if (activityRec.active() || tickEvent.scheduled()) {
1379 DPRINTF(Activity, "CPU already running.\n");
1380 return;
1381 }
1382
1383 DPRINTF(Activity, "Waking up CPU\n");
1384
1385 idleCycles += (curTick - 1) - lastRunningCycle;
1386
1387 tickEvent.schedule(curTick);
1388}
1389
1390template <class Impl>
1391int
1392FullO3CPU<Impl>::getFreeTid()
1393{
1394 for (int i=0; i < numThreads; i++) {
1395 if (!tids[i]) {
1396 tids[i] = true;
1397 return i;
1398 }
1399 }
1400
1401 return -1;
1402}
1403
1404template <class Impl>
1405void
1406FullO3CPU<Impl>::doContextSwitch()
1407{
1408 if (contextSwitch) {
1409
1410 //ADD CODE TO DEACTIVE THREAD HERE (???)
1411
1412 for (int tid=0; tid < cpuWaitList.size(); tid++) {
1413 activateWhenReady(tid);
1414 }
1415
1416 if (cpuWaitList.size() == 0)
1417 contextSwitch = true;
1418 }
1419}
1420
1421template <class Impl>
1422void
1423FullO3CPU<Impl>::updateThreadPriority()
1424{
1425 if (activeThreads.size() > 1)
1426 {
1427 //DEFAULT TO ROUND ROBIN SCHEME
1428 //e.g. Move highest priority to end of thread list
1429 list<unsigned>::iterator list_begin = activeThreads.begin();
1430 list<unsigned>::iterator list_end = activeThreads.end();
1431
1432 unsigned high_thread = *list_begin;
1433
1434 activeThreads.erase(list_begin);
1435
1436 activeThreads.push_back(high_thread);
1437 }
1438}
1439
1440// Forward declaration of FullO3CPU.
1441template class FullO3CPU<O3CPUImpl>;
| 973 dcachePort->setPeer(peer);
974 } else {
975 peer = dcachePort->getPeer();
976 }
977 peer->setPeer(dcachePort);
978}
979
980template <class Impl>
981uint64_t
982FullO3CPU<Impl>::readIntReg(int reg_idx)
983{
984 return regFile.readIntReg(reg_idx);
985}
986
987template <class Impl>
988FloatReg
989FullO3CPU<Impl>::readFloatReg(int reg_idx, int width)
990{
991 return regFile.readFloatReg(reg_idx, width);
992}
993
994template <class Impl>
995FloatReg
996FullO3CPU<Impl>::readFloatReg(int reg_idx)
997{
998 return regFile.readFloatReg(reg_idx);
999}
1000
1001template <class Impl>
1002FloatRegBits
1003FullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width)
1004{
1005 return regFile.readFloatRegBits(reg_idx, width);
1006}
1007
1008template <class Impl>
1009FloatRegBits
1010FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
1011{
1012 return regFile.readFloatRegBits(reg_idx);
1013}
1014
1015template <class Impl>
1016void
1017FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
1018{
1019 regFile.setIntReg(reg_idx, val);
1020}
1021
1022template <class Impl>
1023void
1024FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width)
1025{
1026 regFile.setFloatReg(reg_idx, val, width);
1027}
1028
1029template <class Impl>
1030void
1031FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
1032{
1033 regFile.setFloatReg(reg_idx, val);
1034}
1035
1036template <class Impl>
1037void
1038FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width)
1039{
1040 regFile.setFloatRegBits(reg_idx, val, width);
1041}
1042
1043template <class Impl>
1044void
1045FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
1046{
1047 regFile.setFloatRegBits(reg_idx, val);
1048}
1049
1050template <class Impl>
1051uint64_t
1052FullO3CPU<Impl>::readArchIntReg(int reg_idx, unsigned tid)
1053{
1054 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1055
1056 return regFile.readIntReg(phys_reg);
1057}
1058
1059template <class Impl>
1060float
1061FullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, unsigned tid)
1062{
1063 int idx = reg_idx + TheISA::FP_Base_DepTag;
1064 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1065
1066 return regFile.readFloatReg(phys_reg);
1067}
1068
1069template <class Impl>
1070double
1071FullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, unsigned tid)
1072{
1073 int idx = reg_idx + TheISA::FP_Base_DepTag;
1074 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1075
1076 return regFile.readFloatReg(phys_reg, 64);
1077}
1078
1079template <class Impl>
1080uint64_t
1081FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, unsigned tid)
1082{
1083 int idx = reg_idx + TheISA::FP_Base_DepTag;
1084 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1085
1086 return regFile.readFloatRegBits(phys_reg);
1087}
1088
1089template <class Impl>
1090void
1091FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, unsigned tid)
1092{
1093 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1094
1095 regFile.setIntReg(phys_reg, val);
1096}
1097
1098template <class Impl>
1099void
1100FullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, unsigned tid)
1101{
1102 int idx = reg_idx + TheISA::FP_Base_DepTag;
1103 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1104
1105 regFile.setFloatReg(phys_reg, val);
1106}
1107
1108template <class Impl>
1109void
1110FullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, unsigned tid)
1111{
1112 int idx = reg_idx + TheISA::FP_Base_DepTag;
1113 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1114
1115 regFile.setFloatReg(phys_reg, val, 64);
1116}
1117
1118template <class Impl>
1119void
1120FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid)
1121{
1122 int idx = reg_idx + TheISA::FP_Base_DepTag;
1123 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1124
1125 regFile.setFloatRegBits(phys_reg, val);
1126}
1127
1128template <class Impl>
1129uint64_t
1130FullO3CPU<Impl>::readPC(unsigned tid)
1131{
1132 return commit.readPC(tid);
1133}
1134
1135template <class Impl>
1136void
1137FullO3CPU<Impl>::setPC(Addr new_PC,unsigned tid)
1138{
1139 commit.setPC(new_PC, tid);
1140}
1141
1142template <class Impl>
1143uint64_t
1144FullO3CPU<Impl>::readNextPC(unsigned tid)
1145{
1146 return commit.readNextPC(tid);
1147}
1148
1149template <class Impl>
1150void
1151FullO3CPU<Impl>::setNextPC(uint64_t val,unsigned tid)
1152{
1153 commit.setNextPC(val, tid);
1154}
1155
1156template <class Impl>
1157uint64_t
1158FullO3CPU<Impl>::readNextNPC(unsigned tid)
1159{
1160 return commit.readNextNPC(tid);
1161}
1162
1163template <class Impl>
1164void
1165FullO3CPU<Impl>::setNextNPC(uint64_t val,unsigned tid)
1166{
1167 commit.setNextNPC(val, tid);
1168}
1169
1170template <class Impl>
1171typename FullO3CPU<Impl>::ListIt
1172FullO3CPU<Impl>::addInst(DynInstPtr &inst)
1173{
1174 instList.push_back(inst);
1175
1176 return --(instList.end());
1177}
1178
1179template <class Impl>
1180void
1181FullO3CPU<Impl>::instDone(unsigned tid)
1182{
1183 // Keep an instruction count.
1184 thread[tid]->numInst++;
1185 thread[tid]->numInsts++;
1186 committedInsts[tid]++;
1187 totalCommittedInsts++;
1188
1189 // Check for instruction-count-based events.
1190 comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1191}
1192
1193template <class Impl>
1194void
1195FullO3CPU<Impl>::addToRemoveList(DynInstPtr &inst)
1196{
1197 removeInstsThisCycle = true;
1198
1199 removeList.push(inst->getInstListIt());
1200}
1201
1202template <class Impl>
1203void
1204FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
1205{
1206 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %#x "
1207 "[sn:%lli]\n",
1208 inst->threadNumber, inst->readPC(), inst->seqNum);
1209
1210 removeInstsThisCycle = true;
1211
1212 // Remove the front instruction.
1213 removeList.push(inst->getInstListIt());
1214}
1215
1216template <class Impl>
1217void
1218FullO3CPU<Impl>::removeInstsNotInROB(unsigned tid,
1219 bool squash_delay_slot,
1220 const InstSeqNum &delay_slot_seq_num)
1221{
1222 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1223 " list.\n", tid);
1224
1225 ListIt end_it;
1226
1227 bool rob_empty = false;
1228
1229 if (instList.empty()) {
1230 return;
1231 } else if (rob.isEmpty(/*tid*/)) {
1232 DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1233 end_it = instList.begin();
1234 rob_empty = true;
1235 } else {
1236 end_it = (rob.readTailInst(tid))->getInstListIt();
1237 DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1238 }
1239
1240 removeInstsThisCycle = true;
1241
1242 ListIt inst_it = instList.end();
1243
1244 inst_it--;
1245
1246 // Walk through the instruction list, removing any instructions
1247 // that were inserted after the given instruction iterator, end_it.
1248 while (inst_it != end_it) {
1249 assert(!instList.empty());
1250
1251#if ISA_HAS_DELAY_SLOT
1252 if(!squash_delay_slot &&
1253 delay_slot_seq_num >= (*inst_it)->seqNum) {
1254 break;
1255 }
1256#endif
1257 squashInstIt(inst_it, tid);
1258
1259 inst_it--;
1260 }
1261
1262 // If the ROB was empty, then we actually need to remove the first
1263 // instruction as well.
1264 if (rob_empty) {
1265 squashInstIt(inst_it, tid);
1266 }
1267}
1268
1269template <class Impl>
1270void
1271FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num,
1272 unsigned tid)
1273{
1274 assert(!instList.empty());
1275
1276 removeInstsThisCycle = true;
1277
1278 ListIt inst_iter = instList.end();
1279
1280 inst_iter--;
1281
1282 DPRINTF(O3CPU, "Deleting instructions from instruction "
1283 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1284 tid, seq_num, (*inst_iter)->seqNum);
1285
1286 while ((*inst_iter)->seqNum > seq_num) {
1287
1288 bool break_loop = (inst_iter == instList.begin());
1289
1290 squashInstIt(inst_iter, tid);
1291
1292 inst_iter--;
1293
1294 if (break_loop)
1295 break;
1296 }
1297}
1298
1299template <class Impl>
1300inline void
1301FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, const unsigned &tid)
1302{
1303 if ((*instIt)->threadNumber == tid) {
1304 DPRINTF(O3CPU, "Squashing instruction, "
1305 "[tid:%i] [sn:%lli] PC %#x\n",
1306 (*instIt)->threadNumber,
1307 (*instIt)->seqNum,
1308 (*instIt)->readPC());
1309
1310 // Mark it as squashed.
1311 (*instIt)->setSquashed();
1312
1313 // @todo: Formulate a consistent method for deleting
1314 // instructions from the instruction list
1315 // Remove the instruction from the list.
1316 removeList.push(instIt);
1317 }
1318}
1319
1320template <class Impl>
1321void
1322FullO3CPU<Impl>::cleanUpRemovedInsts()
1323{
1324 while (!removeList.empty()) {
1325 DPRINTF(O3CPU, "Removing instruction, "
1326 "[tid:%i] [sn:%lli] PC %#x\n",
1327 (*removeList.front())->threadNumber,
1328 (*removeList.front())->seqNum,
1329 (*removeList.front())->readPC());
1330
1331 instList.erase(removeList.front());
1332
1333 removeList.pop();
1334 }
1335
1336 removeInstsThisCycle = false;
1337}
1338/*
1339template <class Impl>
1340void
1341FullO3CPU<Impl>::removeAllInsts()
1342{
1343 instList.clear();
1344}
1345*/
1346template <class Impl>
1347void
1348FullO3CPU<Impl>::dumpInsts()
1349{
1350 int num = 0;
1351
1352 ListIt inst_list_it = instList.begin();
1353
1354 cprintf("Dumping Instruction List\n");
1355
1356 while (inst_list_it != instList.end()) {
1357 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1358 "Squashed:%i\n\n",
1359 num, (*inst_list_it)->readPC(), (*inst_list_it)->threadNumber,
1360 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1361 (*inst_list_it)->isSquashed());
1362 inst_list_it++;
1363 ++num;
1364 }
1365}
1366/*
1367template <class Impl>
1368void
1369FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
1370{
1371 iew.wakeDependents(inst);
1372}
1373*/
1374template <class Impl>
1375void
1376FullO3CPU<Impl>::wakeCPU()
1377{
1378 if (activityRec.active() || tickEvent.scheduled()) {
1379 DPRINTF(Activity, "CPU already running.\n");
1380 return;
1381 }
1382
1383 DPRINTF(Activity, "Waking up CPU\n");
1384
1385 idleCycles += (curTick - 1) - lastRunningCycle;
1386
1387 tickEvent.schedule(curTick);
1388}
1389
1390template <class Impl>
1391int
1392FullO3CPU<Impl>::getFreeTid()
1393{
1394 for (int i=0; i < numThreads; i++) {
1395 if (!tids[i]) {
1396 tids[i] = true;
1397 return i;
1398 }
1399 }
1400
1401 return -1;
1402}
1403
1404template <class Impl>
1405void
1406FullO3CPU<Impl>::doContextSwitch()
1407{
1408 if (contextSwitch) {
1409
1410 //ADD CODE TO DEACTIVE THREAD HERE (???)
1411
1412 for (int tid=0; tid < cpuWaitList.size(); tid++) {
1413 activateWhenReady(tid);
1414 }
1415
1416 if (cpuWaitList.size() == 0)
1417 contextSwitch = true;
1418 }
1419}
1420
1421template <class Impl>
1422void
1423FullO3CPU<Impl>::updateThreadPriority()
1424{
1425 if (activeThreads.size() > 1)
1426 {
1427 //DEFAULT TO ROUND ROBIN SCHEME
1428 //e.g. Move highest priority to end of thread list
1429 list<unsigned>::iterator list_begin = activeThreads.begin();
1430 list<unsigned>::iterator list_end = activeThreads.end();
1431
1432 unsigned high_thread = *list_begin;
1433
1434 activeThreads.erase(list_begin);
1435
1436 activeThreads.push_back(high_thread);
1437 }
1438}
1439
1440// Forward declaration of FullO3CPU.
1441template class FullO3CPU<O3CPUImpl>;
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