36#include "sim/system.hh"
37#else
38#include "sim/process.hh"
39#endif
40
41#include "cpu/activity.hh"
42#include "cpu/simple_thread.hh"
43#include "cpu/thread_context.hh"
44#include "cpu/o3/isa_specific.hh"
45#include "cpu/o3/cpu.hh"
46
47#include "sim/root.hh"
48#include "sim/stat_control.hh"
49
50#if USE_CHECKER
51#include "cpu/checker/cpu.hh"
52#endif
53
54using namespace std;
55using namespace TheISA;
56
57BaseO3CPU::BaseO3CPU(Params *params)
58 : BaseCPU(params), cpu_id(0)
59{
60}
61
62void
63BaseO3CPU::regStats()
64{
65 BaseCPU::regStats();
66}
67
68template <class Impl>
69FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
70 : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
71{
72}
73
74template <class Impl>
75void
76FullO3CPU<Impl>::TickEvent::process()
77{
78 cpu->tick();
79}
80
81template <class Impl>
82const char *
83FullO3CPU<Impl>::TickEvent::description()
84{
85 return "FullO3CPU tick event";
86}
87
88template <class Impl>
89FullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent()
90 : Event(&mainEventQueue, CPU_Tick_Pri)
91{
92}
93
94template <class Impl>
95void
96FullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num,
97 FullO3CPU<Impl> *thread_cpu)
98{
99 tid = thread_num;
100 cpu = thread_cpu;
101}
102
103template <class Impl>
104void
105FullO3CPU<Impl>::ActivateThreadEvent::process()
106{
107 cpu->activateThread(tid);
108}
109
110template <class Impl>
111const char *
112FullO3CPU<Impl>::ActivateThreadEvent::description()
113{
114 return "FullO3CPU \"Activate Thread\" event";
115}
116
117template <class Impl>
118FullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent()
119 : Event(&mainEventQueue, CPU_Tick_Pri)
120{
121}
122
123template <class Impl>
124void
125FullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num,
126 FullO3CPU<Impl> *thread_cpu)
127{
128 tid = thread_num;
129 cpu = thread_cpu;
130}
131
132template <class Impl>
133void
134FullO3CPU<Impl>::DeallocateContextEvent::process()
135{
136 cpu->deactivateThread(tid);
137 cpu->removeThread(tid);
138}
139
140template <class Impl>
141const char *
142FullO3CPU<Impl>::DeallocateContextEvent::description()
143{
144 return "FullO3CPU \"Deallocate Context\" event";
145}
146
147template <class Impl>
148FullO3CPU<Impl>::FullO3CPU(Params *params)
149 : BaseO3CPU(params),
150 tickEvent(this),
151 removeInstsThisCycle(false),
152 fetch(params),
153 decode(params),
154 rename(params),
155 iew(params),
156 commit(params),
157
158 regFile(params->numPhysIntRegs, params->numPhysFloatRegs),
159
160 freeList(params->numberOfThreads,
161 TheISA::NumIntRegs, params->numPhysIntRegs,
162 TheISA::NumFloatRegs, params->numPhysFloatRegs),
163
164 rob(params->numROBEntries, params->squashWidth,
165 params->smtROBPolicy, params->smtROBThreshold,
166 params->numberOfThreads),
167
168 scoreboard(params->numberOfThreads,
169 TheISA::NumIntRegs, params->numPhysIntRegs,
170 TheISA::NumFloatRegs, params->numPhysFloatRegs,
171 TheISA::NumMiscRegs * number_of_threads,
172 TheISA::ZeroReg),
173
174 timeBuffer(params->backComSize, params->forwardComSize),
175 fetchQueue(params->backComSize, params->forwardComSize),
176 decodeQueue(params->backComSize, params->forwardComSize),
177 renameQueue(params->backComSize, params->forwardComSize),
178 iewQueue(params->backComSize, params->forwardComSize),
179 activityRec(NumStages,
180 params->backComSize + params->forwardComSize,
181 params->activity),
182
183 globalSeqNum(1),
184#if FULL_SYSTEM
185 system(params->system),
186 physmem(system->physmem),
187#endif // FULL_SYSTEM
188 mem(params->mem),
189 drainCount(0),
190 deferRegistration(params->deferRegistration),
191 numThreads(number_of_threads)
192{
193 _status = Idle;
194
195 checker = NULL;
196
197 if (params->checker) {
198#if USE_CHECKER
199 BaseCPU *temp_checker = params->checker;
200 checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
201 checker->setMemory(mem);
202#if FULL_SYSTEM
203 checker->setSystem(params->system);
204#endif
205#else
206 panic("Checker enabled but not compiled in!");
207#endif // USE_CHECKER
208 }
209
210#if !FULL_SYSTEM
211 thread.resize(number_of_threads);
212 tids.resize(number_of_threads);
213#endif
214
215 // The stages also need their CPU pointer setup. However this
216 // must be done at the upper level CPU because they have pointers
217 // to the upper level CPU, and not this FullO3CPU.
218
219 // Set up Pointers to the activeThreads list for each stage
220 fetch.setActiveThreads(&activeThreads);
221 decode.setActiveThreads(&activeThreads);
222 rename.setActiveThreads(&activeThreads);
223 iew.setActiveThreads(&activeThreads);
224 commit.setActiveThreads(&activeThreads);
225
226 // Give each of the stages the time buffer they will use.
227 fetch.setTimeBuffer(&timeBuffer);
228 decode.setTimeBuffer(&timeBuffer);
229 rename.setTimeBuffer(&timeBuffer);
230 iew.setTimeBuffer(&timeBuffer);
231 commit.setTimeBuffer(&timeBuffer);
232
233 // Also setup each of the stages' queues.
234 fetch.setFetchQueue(&fetchQueue);
235 decode.setFetchQueue(&fetchQueue);
236 commit.setFetchQueue(&fetchQueue);
237 decode.setDecodeQueue(&decodeQueue);
238 rename.setDecodeQueue(&decodeQueue);
239 rename.setRenameQueue(&renameQueue);
240 iew.setRenameQueue(&renameQueue);
241 iew.setIEWQueue(&iewQueue);
242 commit.setIEWQueue(&iewQueue);
243 commit.setRenameQueue(&renameQueue);
244
245 commit.setIEWStage(&iew);
246 rename.setIEWStage(&iew);
247 rename.setCommitStage(&commit);
248
249#if !FULL_SYSTEM
250 int active_threads = params->workload.size();
251
252 if (active_threads > Impl::MaxThreads) {
253 panic("Workload Size too large. Increase the 'MaxThreads'"
254 "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or "
255 "edit your workload size.");
256 }
257#else
258 int active_threads = 1;
259#endif
260
261 //Make Sure That this a Valid Architeture
262 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs);
263 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
264
265 rename.setScoreboard(&scoreboard);
266 iew.setScoreboard(&scoreboard);
267
268 // Setup the rename map for whichever stages need it.
269 PhysRegIndex lreg_idx = 0;
270 PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs
271
272 for (int tid=0; tid < numThreads; tid++) {
273 bool bindRegs = (tid <= active_threads - 1);
274
275 commitRenameMap[tid].init(TheISA::NumIntRegs,
276 params->numPhysIntRegs,
277 lreg_idx, //Index for Logical. Regs
278
279 TheISA::NumFloatRegs,
280 params->numPhysFloatRegs,
281 freg_idx, //Index for Float Regs
282
283 TheISA::NumMiscRegs,
284
285 TheISA::ZeroReg,
286 TheISA::ZeroReg,
287
288 tid,
289 false);
290
291 renameMap[tid].init(TheISA::NumIntRegs,
292 params->numPhysIntRegs,
293 lreg_idx, //Index for Logical. Regs
294
295 TheISA::NumFloatRegs,
296 params->numPhysFloatRegs,
297 freg_idx, //Index for Float Regs
298
299 TheISA::NumMiscRegs,
300
301 TheISA::ZeroReg,
302 TheISA::ZeroReg,
303
304 tid,
305 bindRegs);
306 }
307
308 rename.setRenameMap(renameMap);
309 commit.setRenameMap(commitRenameMap);
310
311 // Give renameMap & rename stage access to the freeList;
312 for (int i=0; i < numThreads; i++) {
313 renameMap[i].setFreeList(&freeList);
314 }
315 rename.setFreeList(&freeList);
316
317 // Setup the ROB for whichever stages need it.
318 commit.setROB(&rob);
319
320 lastRunningCycle = curTick;
321
322 lastActivatedCycle = -1;
323
324 // Give renameMap & rename stage access to the freeList;
325 //for (int i=0; i < numThreads; i++) {
326 //globalSeqNum[i] = 1;
327 //}
328
329 contextSwitch = false;
330}
331
332template <class Impl>
333FullO3CPU<Impl>::~FullO3CPU()
334{
335}
336
337template <class Impl>
338void
339FullO3CPU<Impl>::fullCPURegStats()
340{
341 BaseO3CPU::regStats();
342
343 // Register any of the O3CPU's stats here.
344 timesIdled
345 .name(name() + ".timesIdled")
346 .desc("Number of times that the entire CPU went into an idle state and"
347 " unscheduled itself")
348 .prereq(timesIdled);
349
350 idleCycles
351 .name(name() + ".idleCycles")
352 .desc("Total number of cycles that the CPU has spent unscheduled due "
353 "to idling")
354 .prereq(idleCycles);
355
356 // Number of Instructions simulated
357 // --------------------------------
358 // Should probably be in Base CPU but need templated
359 // MaxThreads so put in here instead
360 committedInsts
361 .init(numThreads)
362 .name(name() + ".committedInsts")
363 .desc("Number of Instructions Simulated");
364
365 totalCommittedInsts
366 .name(name() + ".committedInsts_total")
367 .desc("Number of Instructions Simulated");
368
369 cpi
370 .name(name() + ".cpi")
371 .desc("CPI: Cycles Per Instruction")
372 .precision(6);
373 cpi = simTicks / committedInsts;
374
375 totalCpi
376 .name(name() + ".cpi_total")
377 .desc("CPI: Total CPI of All Threads")
378 .precision(6);
379 totalCpi = simTicks / totalCommittedInsts;
380
381 ipc
382 .name(name() + ".ipc")
383 .desc("IPC: Instructions Per Cycle")
384 .precision(6);
385 ipc = committedInsts / simTicks;
386
387 totalIpc
388 .name(name() + ".ipc_total")
389 .desc("IPC: Total IPC of All Threads")
390 .precision(6);
391 totalIpc = totalCommittedInsts / simTicks;
392
393}
394
395template <class Impl>
396Port *
397FullO3CPU<Impl>::getPort(const std::string &if_name, int idx)
398{
399 if (if_name == "dcache_port")
400 return iew.getDcachePort();
401 else if (if_name == "icache_port")
402 return fetch.getIcachePort();
403 else
404 panic("No Such Port\n");
405}
406
407template <class Impl>
408void
409FullO3CPU<Impl>::tick()
410{
411 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
412
413 ++numCycles;
414
415// activity = false;
416
417 //Tick each of the stages
418 fetch.tick();
419
420 decode.tick();
421
422 rename.tick();
423
424 iew.tick();
425
426 commit.tick();
427
428#if !FULL_SYSTEM
429 doContextSwitch();
430#endif
431
432 // Now advance the time buffers
433 timeBuffer.advance();
434
435 fetchQueue.advance();
436 decodeQueue.advance();
437 renameQueue.advance();
438 iewQueue.advance();
439
440 activityRec.advance();
441
442 if (removeInstsThisCycle) {
443 cleanUpRemovedInsts();
444 }
445
446 if (!tickEvent.scheduled()) {
447 if (_status == SwitchedOut ||
448 getState() == SimObject::Drained) {
449 // increment stat
450 lastRunningCycle = curTick;
451 } else if (!activityRec.active()) {
452 lastRunningCycle = curTick;
453 timesIdled++;
454 } else {
455 tickEvent.schedule(curTick + cycles(1));
456 }
457 }
458
459#if !FULL_SYSTEM
460 updateThreadPriority();
461#endif
462
463}
464
465template <class Impl>
466void
467FullO3CPU<Impl>::init()
468{
469 if (!deferRegistration) {
470 registerThreadContexts();
471 }
472
473 // Set inSyscall so that the CPU doesn't squash when initially
474 // setting up registers.
475 for (int i = 0; i < number_of_threads; ++i)
476 thread[i]->inSyscall = true;
477
478 for (int tid=0; tid < number_of_threads; tid++) {
479#if FULL_SYSTEM
480 ThreadContext *src_tc = threadContexts[tid];
481#else
482 ThreadContext *src_tc = thread[tid]->getTC();
483#endif
484 // Threads start in the Suspended State
485 if (src_tc->status() != ThreadContext::Suspended) {
486 continue;
487 }
488
489#if FULL_SYSTEM
490 TheISA::initCPU(src_tc, src_tc->readCpuId());
491#endif
492 }
493
494 // Clear inSyscall.
495 for (int i = 0; i < number_of_threads; ++i)
496 thread[i]->inSyscall = false;
497
498 // Initialize stages.
499 fetch.initStage();
500 iew.initStage();
501 rename.initStage();
502 commit.initStage();
503
504 commit.setThreads(thread);
505}
506
507template <class Impl>
508void
509FullO3CPU<Impl>::activateThread(unsigned tid)
510{
511 list<unsigned>::iterator isActive = find(
512 activeThreads.begin(), activeThreads.end(), tid);
513
514 if (isActive == activeThreads.end()) {
515 DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n",
516 tid);
517
518 activeThreads.push_back(tid);
519 }
520}
521
522template <class Impl>
523void
524FullO3CPU<Impl>::deactivateThread(unsigned tid)
525{
526 //Remove From Active List, if Active
527 list<unsigned>::iterator thread_it =
528 find(activeThreads.begin(), activeThreads.end(), tid);
529
530 if (thread_it != activeThreads.end()) {
531 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
532 tid);
533 activeThreads.erase(thread_it);
534 }
535}
536
537template <class Impl>
538void
539FullO3CPU<Impl>::activateContext(int tid, int delay)
540{
541 // Needs to set each stage to running as well.
542 if (delay){
543 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate "
544 "on cycle %d\n", tid, curTick + cycles(delay));
545 scheduleActivateThreadEvent(tid, delay);
546 } else {
547 activateThread(tid);
548 }
549
550 if(lastActivatedCycle < curTick) {
551 scheduleTickEvent(delay);
552
553 // Be sure to signal that there's some activity so the CPU doesn't
554 // deschedule itself.
555 activityRec.activity();
556 fetch.wakeFromQuiesce();
557
558 lastActivatedCycle = curTick;
559
560 _status = Running;
561 }
562}
563
564template <class Impl>
565void
566FullO3CPU<Impl>::deallocateContext(int tid, int delay)
567{
568 // Schedule removal of thread data from CPU
569 if (delay){
570 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate "
571 "on cycle %d\n", tid, curTick + cycles(delay));
572 scheduleDeallocateContextEvent(tid, delay);
573 } else {
574 deactivateThread(tid);
575 removeThread(tid);
576 }
577}
578
579template <class Impl>
580void
581FullO3CPU<Impl>::suspendContext(int tid)
582{
583 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
584 deactivateThread(tid);
585 if (activeThreads.size() == 0)
586 unscheduleTickEvent();
587 _status = Idle;
588}
589
590template <class Impl>
591void
592FullO3CPU<Impl>::haltContext(int tid)
593{
594 //For now, this is the same as deallocate
595 DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
596 deallocateContext(tid, 1);
597}
598
599template <class Impl>
600void
601FullO3CPU<Impl>::insertThread(unsigned tid)
602{
603 DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
604 // Will change now that the PC and thread state is internal to the CPU
605 // and not in the ThreadContext.
606#if FULL_SYSTEM
607 ThreadContext *src_tc = system->threadContexts[tid];
608#else
609 ThreadContext *src_tc = tcBase(tid);
610#endif
611
612 //Bind Int Regs to Rename Map
613 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
614 PhysRegIndex phys_reg = freeList.getIntReg();
615
616 renameMap[tid].setEntry(ireg,phys_reg);
617 scoreboard.setReg(phys_reg);
618 }
619
620 //Bind Float Regs to Rename Map
621 for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
622 PhysRegIndex phys_reg = freeList.getFloatReg();
623
624 renameMap[tid].setEntry(freg,phys_reg);
625 scoreboard.setReg(phys_reg);
626 }
627
628 //Copy Thread Data Into RegFile
629 //this->copyFromTC(tid);
630
631 //Set PC/NPC/NNPC
632 setPC(src_tc->readPC(), tid);
633 setNextPC(src_tc->readNextPC(), tid);
634#if ISA_HAS_DELAY_SLOT
635 setNextNPC(src_tc->readNextNPC(), tid);
636#endif
637
638 src_tc->setStatus(ThreadContext::Active);
639
640 activateContext(tid,1);
641
642 //Reset ROB/IQ/LSQ Entries
643 commit.rob->resetEntries();
644 iew.resetEntries();
645}
646
647template <class Impl>
648void
649FullO3CPU<Impl>::removeThread(unsigned tid)
650{
651 DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
652
653 // Copy Thread Data From RegFile
654 // If thread is suspended, it might be re-allocated
655 //this->copyToTC(tid);
656
657 // Unbind Int Regs from Rename Map
658 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
659 PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
660
661 scoreboard.unsetReg(phys_reg);
662 freeList.addReg(phys_reg);
663 }
664
665 // Unbind Float Regs from Rename Map
666 for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
667 PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
668
669 scoreboard.unsetReg(phys_reg);
670 freeList.addReg(phys_reg);
671 }
672
673 // Squash Throughout Pipeline
674 InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum;
675 fetch.squash(0, squash_seq_num, true, tid);
676 decode.squash(tid);
677 rename.squash(squash_seq_num, tid);
678 iew.squash(tid);
679 commit.rob->squash(squash_seq_num, tid);
680
681 assert(iew.ldstQueue.getCount(tid) == 0);
682
683 // Reset ROB/IQ/LSQ Entries
684 if (activeThreads.size() >= 1) {
685 commit.rob->resetEntries();
686 iew.resetEntries();
687 }
688}
689
690
691template <class Impl>
692void
693FullO3CPU<Impl>::activateWhenReady(int tid)
694{
695 DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming"
696 "(e.g. PhysRegs/ROB/IQ/LSQ) \n",
697 tid);
698
699 bool ready = true;
700
701 if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) {
702 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
703 "Phys. Int. Regs.\n",
704 tid);
705 ready = false;
706 } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) {
707 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
708 "Phys. Float. Regs.\n",
709 tid);
710 ready = false;
711 } else if (commit.rob->numFreeEntries() >=
712 commit.rob->entryAmount(activeThreads.size() + 1)) {
713 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
714 "ROB entries.\n",
715 tid);
716 ready = false;
717 } else if (iew.instQueue.numFreeEntries() >=
718 iew.instQueue.entryAmount(activeThreads.size() + 1)) {
719 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
720 "IQ entries.\n",
721 tid);
722 ready = false;
723 } else if (iew.ldstQueue.numFreeEntries() >=
724 iew.ldstQueue.entryAmount(activeThreads.size() + 1)) {
725 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
726 "LSQ entries.\n",
727 tid);
728 ready = false;
729 }
730
731 if (ready) {
732 insertThread(tid);
733
734 contextSwitch = false;
735
736 cpuWaitList.remove(tid);
737 } else {
738 suspendContext(tid);
739
740 //blocks fetch
741 contextSwitch = true;
742
743 //@todo: dont always add to waitlist
744 //do waitlist
745 cpuWaitList.push_back(tid);
746 }
747}
748
749template <class Impl>
750void
751FullO3CPU<Impl>::serialize(std::ostream &os)
752{
753 SimObject::State so_state = SimObject::getState();
754 SERIALIZE_ENUM(so_state);
755 BaseCPU::serialize(os);
756 nameOut(os, csprintf("%s.tickEvent", name()));
757 tickEvent.serialize(os);
758
759 // Use SimpleThread's ability to checkpoint to make it easier to
760 // write out the registers. Also make this static so it doesn't
761 // get instantiated multiple times (causes a panic in statistics).
762 static SimpleThread temp;
763
764 for (int i = 0; i < thread.size(); i++) {
765 nameOut(os, csprintf("%s.xc.%i", name(), i));
766 temp.copyTC(thread[i]->getTC());
767 temp.serialize(os);
768 }
769}
770
771template <class Impl>
772void
773FullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion)
774{
775 SimObject::State so_state;
776 UNSERIALIZE_ENUM(so_state);
777 BaseCPU::unserialize(cp, section);
778 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
779
780 // Use SimpleThread's ability to checkpoint to make it easier to
781 // read in the registers. Also make this static so it doesn't
782 // get instantiated multiple times (causes a panic in statistics).
783 static SimpleThread temp;
784
785 for (int i = 0; i < thread.size(); i++) {
786 temp.copyTC(thread[i]->getTC());
787 temp.unserialize(cp, csprintf("%s.xc.%i", section, i));
788 thread[i]->getTC()->copyArchRegs(temp.getTC());
789 }
790}
791
792template <class Impl>
793unsigned int
794FullO3CPU<Impl>::drain(Event *drain_event)
795{
| 37#include "sim/system.hh"
38#else
39#include "sim/process.hh"
40#endif
41
42#include "cpu/activity.hh"
43#include "cpu/simple_thread.hh"
44#include "cpu/thread_context.hh"
45#include "cpu/o3/isa_specific.hh"
46#include "cpu/o3/cpu.hh"
47
48#include "sim/root.hh"
49#include "sim/stat_control.hh"
50
51#if USE_CHECKER
52#include "cpu/checker/cpu.hh"
53#endif
54
55using namespace std;
56using namespace TheISA;
57
58BaseO3CPU::BaseO3CPU(Params *params)
59 : BaseCPU(params), cpu_id(0)
60{
61}
62
63void
64BaseO3CPU::regStats()
65{
66 BaseCPU::regStats();
67}
68
69template <class Impl>
70FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
71 : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
72{
73}
74
75template <class Impl>
76void
77FullO3CPU<Impl>::TickEvent::process()
78{
79 cpu->tick();
80}
81
82template <class Impl>
83const char *
84FullO3CPU<Impl>::TickEvent::description()
85{
86 return "FullO3CPU tick event";
87}
88
89template <class Impl>
90FullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent()
91 : Event(&mainEventQueue, CPU_Tick_Pri)
92{
93}
94
95template <class Impl>
96void
97FullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num,
98 FullO3CPU<Impl> *thread_cpu)
99{
100 tid = thread_num;
101 cpu = thread_cpu;
102}
103
104template <class Impl>
105void
106FullO3CPU<Impl>::ActivateThreadEvent::process()
107{
108 cpu->activateThread(tid);
109}
110
111template <class Impl>
112const char *
113FullO3CPU<Impl>::ActivateThreadEvent::description()
114{
115 return "FullO3CPU \"Activate Thread\" event";
116}
117
118template <class Impl>
119FullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent()
120 : Event(&mainEventQueue, CPU_Tick_Pri)
121{
122}
123
124template <class Impl>
125void
126FullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num,
127 FullO3CPU<Impl> *thread_cpu)
128{
129 tid = thread_num;
130 cpu = thread_cpu;
131}
132
133template <class Impl>
134void
135FullO3CPU<Impl>::DeallocateContextEvent::process()
136{
137 cpu->deactivateThread(tid);
138 cpu->removeThread(tid);
139}
140
141template <class Impl>
142const char *
143FullO3CPU<Impl>::DeallocateContextEvent::description()
144{
145 return "FullO3CPU \"Deallocate Context\" event";
146}
147
148template <class Impl>
149FullO3CPU<Impl>::FullO3CPU(Params *params)
150 : BaseO3CPU(params),
151 tickEvent(this),
152 removeInstsThisCycle(false),
153 fetch(params),
154 decode(params),
155 rename(params),
156 iew(params),
157 commit(params),
158
159 regFile(params->numPhysIntRegs, params->numPhysFloatRegs),
160
161 freeList(params->numberOfThreads,
162 TheISA::NumIntRegs, params->numPhysIntRegs,
163 TheISA::NumFloatRegs, params->numPhysFloatRegs),
164
165 rob(params->numROBEntries, params->squashWidth,
166 params->smtROBPolicy, params->smtROBThreshold,
167 params->numberOfThreads),
168
169 scoreboard(params->numberOfThreads,
170 TheISA::NumIntRegs, params->numPhysIntRegs,
171 TheISA::NumFloatRegs, params->numPhysFloatRegs,
172 TheISA::NumMiscRegs * number_of_threads,
173 TheISA::ZeroReg),
174
175 timeBuffer(params->backComSize, params->forwardComSize),
176 fetchQueue(params->backComSize, params->forwardComSize),
177 decodeQueue(params->backComSize, params->forwardComSize),
178 renameQueue(params->backComSize, params->forwardComSize),
179 iewQueue(params->backComSize, params->forwardComSize),
180 activityRec(NumStages,
181 params->backComSize + params->forwardComSize,
182 params->activity),
183
184 globalSeqNum(1),
185#if FULL_SYSTEM
186 system(params->system),
187 physmem(system->physmem),
188#endif // FULL_SYSTEM
189 mem(params->mem),
190 drainCount(0),
191 deferRegistration(params->deferRegistration),
192 numThreads(number_of_threads)
193{
194 _status = Idle;
195
196 checker = NULL;
197
198 if (params->checker) {
199#if USE_CHECKER
200 BaseCPU *temp_checker = params->checker;
201 checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
202 checker->setMemory(mem);
203#if FULL_SYSTEM
204 checker->setSystem(params->system);
205#endif
206#else
207 panic("Checker enabled but not compiled in!");
208#endif // USE_CHECKER
209 }
210
211#if !FULL_SYSTEM
212 thread.resize(number_of_threads);
213 tids.resize(number_of_threads);
214#endif
215
216 // The stages also need their CPU pointer setup. However this
217 // must be done at the upper level CPU because they have pointers
218 // to the upper level CPU, and not this FullO3CPU.
219
220 // Set up Pointers to the activeThreads list for each stage
221 fetch.setActiveThreads(&activeThreads);
222 decode.setActiveThreads(&activeThreads);
223 rename.setActiveThreads(&activeThreads);
224 iew.setActiveThreads(&activeThreads);
225 commit.setActiveThreads(&activeThreads);
226
227 // Give each of the stages the time buffer they will use.
228 fetch.setTimeBuffer(&timeBuffer);
229 decode.setTimeBuffer(&timeBuffer);
230 rename.setTimeBuffer(&timeBuffer);
231 iew.setTimeBuffer(&timeBuffer);
232 commit.setTimeBuffer(&timeBuffer);
233
234 // Also setup each of the stages' queues.
235 fetch.setFetchQueue(&fetchQueue);
236 decode.setFetchQueue(&fetchQueue);
237 commit.setFetchQueue(&fetchQueue);
238 decode.setDecodeQueue(&decodeQueue);
239 rename.setDecodeQueue(&decodeQueue);
240 rename.setRenameQueue(&renameQueue);
241 iew.setRenameQueue(&renameQueue);
242 iew.setIEWQueue(&iewQueue);
243 commit.setIEWQueue(&iewQueue);
244 commit.setRenameQueue(&renameQueue);
245
246 commit.setIEWStage(&iew);
247 rename.setIEWStage(&iew);
248 rename.setCommitStage(&commit);
249
250#if !FULL_SYSTEM
251 int active_threads = params->workload.size();
252
253 if (active_threads > Impl::MaxThreads) {
254 panic("Workload Size too large. Increase the 'MaxThreads'"
255 "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or "
256 "edit your workload size.");
257 }
258#else
259 int active_threads = 1;
260#endif
261
262 //Make Sure That this a Valid Architeture
263 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs);
264 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
265
266 rename.setScoreboard(&scoreboard);
267 iew.setScoreboard(&scoreboard);
268
269 // Setup the rename map for whichever stages need it.
270 PhysRegIndex lreg_idx = 0;
271 PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs
272
273 for (int tid=0; tid < numThreads; tid++) {
274 bool bindRegs = (tid <= active_threads - 1);
275
276 commitRenameMap[tid].init(TheISA::NumIntRegs,
277 params->numPhysIntRegs,
278 lreg_idx, //Index for Logical. Regs
279
280 TheISA::NumFloatRegs,
281 params->numPhysFloatRegs,
282 freg_idx, //Index for Float Regs
283
284 TheISA::NumMiscRegs,
285
286 TheISA::ZeroReg,
287 TheISA::ZeroReg,
288
289 tid,
290 false);
291
292 renameMap[tid].init(TheISA::NumIntRegs,
293 params->numPhysIntRegs,
294 lreg_idx, //Index for Logical. Regs
295
296 TheISA::NumFloatRegs,
297 params->numPhysFloatRegs,
298 freg_idx, //Index for Float Regs
299
300 TheISA::NumMiscRegs,
301
302 TheISA::ZeroReg,
303 TheISA::ZeroReg,
304
305 tid,
306 bindRegs);
307 }
308
309 rename.setRenameMap(renameMap);
310 commit.setRenameMap(commitRenameMap);
311
312 // Give renameMap & rename stage access to the freeList;
313 for (int i=0; i < numThreads; i++) {
314 renameMap[i].setFreeList(&freeList);
315 }
316 rename.setFreeList(&freeList);
317
318 // Setup the ROB for whichever stages need it.
319 commit.setROB(&rob);
320
321 lastRunningCycle = curTick;
322
323 lastActivatedCycle = -1;
324
325 // Give renameMap & rename stage access to the freeList;
326 //for (int i=0; i < numThreads; i++) {
327 //globalSeqNum[i] = 1;
328 //}
329
330 contextSwitch = false;
331}
332
333template <class Impl>
334FullO3CPU<Impl>::~FullO3CPU()
335{
336}
337
338template <class Impl>
339void
340FullO3CPU<Impl>::fullCPURegStats()
341{
342 BaseO3CPU::regStats();
343
344 // Register any of the O3CPU's stats here.
345 timesIdled
346 .name(name() + ".timesIdled")
347 .desc("Number of times that the entire CPU went into an idle state and"
348 " unscheduled itself")
349 .prereq(timesIdled);
350
351 idleCycles
352 .name(name() + ".idleCycles")
353 .desc("Total number of cycles that the CPU has spent unscheduled due "
354 "to idling")
355 .prereq(idleCycles);
356
357 // Number of Instructions simulated
358 // --------------------------------
359 // Should probably be in Base CPU but need templated
360 // MaxThreads so put in here instead
361 committedInsts
362 .init(numThreads)
363 .name(name() + ".committedInsts")
364 .desc("Number of Instructions Simulated");
365
366 totalCommittedInsts
367 .name(name() + ".committedInsts_total")
368 .desc("Number of Instructions Simulated");
369
370 cpi
371 .name(name() + ".cpi")
372 .desc("CPI: Cycles Per Instruction")
373 .precision(6);
374 cpi = simTicks / committedInsts;
375
376 totalCpi
377 .name(name() + ".cpi_total")
378 .desc("CPI: Total CPI of All Threads")
379 .precision(6);
380 totalCpi = simTicks / totalCommittedInsts;
381
382 ipc
383 .name(name() + ".ipc")
384 .desc("IPC: Instructions Per Cycle")
385 .precision(6);
386 ipc = committedInsts / simTicks;
387
388 totalIpc
389 .name(name() + ".ipc_total")
390 .desc("IPC: Total IPC of All Threads")
391 .precision(6);
392 totalIpc = totalCommittedInsts / simTicks;
393
394}
395
396template <class Impl>
397Port *
398FullO3CPU<Impl>::getPort(const std::string &if_name, int idx)
399{
400 if (if_name == "dcache_port")
401 return iew.getDcachePort();
402 else if (if_name == "icache_port")
403 return fetch.getIcachePort();
404 else
405 panic("No Such Port\n");
406}
407
408template <class Impl>
409void
410FullO3CPU<Impl>::tick()
411{
412 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
413
414 ++numCycles;
415
416// activity = false;
417
418 //Tick each of the stages
419 fetch.tick();
420
421 decode.tick();
422
423 rename.tick();
424
425 iew.tick();
426
427 commit.tick();
428
429#if !FULL_SYSTEM
430 doContextSwitch();
431#endif
432
433 // Now advance the time buffers
434 timeBuffer.advance();
435
436 fetchQueue.advance();
437 decodeQueue.advance();
438 renameQueue.advance();
439 iewQueue.advance();
440
441 activityRec.advance();
442
443 if (removeInstsThisCycle) {
444 cleanUpRemovedInsts();
445 }
446
447 if (!tickEvent.scheduled()) {
448 if (_status == SwitchedOut ||
449 getState() == SimObject::Drained) {
450 // increment stat
451 lastRunningCycle = curTick;
452 } else if (!activityRec.active()) {
453 lastRunningCycle = curTick;
454 timesIdled++;
455 } else {
456 tickEvent.schedule(curTick + cycles(1));
457 }
458 }
459
460#if !FULL_SYSTEM
461 updateThreadPriority();
462#endif
463
464}
465
466template <class Impl>
467void
468FullO3CPU<Impl>::init()
469{
470 if (!deferRegistration) {
471 registerThreadContexts();
472 }
473
474 // Set inSyscall so that the CPU doesn't squash when initially
475 // setting up registers.
476 for (int i = 0; i < number_of_threads; ++i)
477 thread[i]->inSyscall = true;
478
479 for (int tid=0; tid < number_of_threads; tid++) {
480#if FULL_SYSTEM
481 ThreadContext *src_tc = threadContexts[tid];
482#else
483 ThreadContext *src_tc = thread[tid]->getTC();
484#endif
485 // Threads start in the Suspended State
486 if (src_tc->status() != ThreadContext::Suspended) {
487 continue;
488 }
489
490#if FULL_SYSTEM
491 TheISA::initCPU(src_tc, src_tc->readCpuId());
492#endif
493 }
494
495 // Clear inSyscall.
496 for (int i = 0; i < number_of_threads; ++i)
497 thread[i]->inSyscall = false;
498
499 // Initialize stages.
500 fetch.initStage();
501 iew.initStage();
502 rename.initStage();
503 commit.initStage();
504
505 commit.setThreads(thread);
506}
507
508template <class Impl>
509void
510FullO3CPU<Impl>::activateThread(unsigned tid)
511{
512 list<unsigned>::iterator isActive = find(
513 activeThreads.begin(), activeThreads.end(), tid);
514
515 if (isActive == activeThreads.end()) {
516 DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n",
517 tid);
518
519 activeThreads.push_back(tid);
520 }
521}
522
523template <class Impl>
524void
525FullO3CPU<Impl>::deactivateThread(unsigned tid)
526{
527 //Remove From Active List, if Active
528 list<unsigned>::iterator thread_it =
529 find(activeThreads.begin(), activeThreads.end(), tid);
530
531 if (thread_it != activeThreads.end()) {
532 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
533 tid);
534 activeThreads.erase(thread_it);
535 }
536}
537
538template <class Impl>
539void
540FullO3CPU<Impl>::activateContext(int tid, int delay)
541{
542 // Needs to set each stage to running as well.
543 if (delay){
544 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate "
545 "on cycle %d\n", tid, curTick + cycles(delay));
546 scheduleActivateThreadEvent(tid, delay);
547 } else {
548 activateThread(tid);
549 }
550
551 if(lastActivatedCycle < curTick) {
552 scheduleTickEvent(delay);
553
554 // Be sure to signal that there's some activity so the CPU doesn't
555 // deschedule itself.
556 activityRec.activity();
557 fetch.wakeFromQuiesce();
558
559 lastActivatedCycle = curTick;
560
561 _status = Running;
562 }
563}
564
565template <class Impl>
566void
567FullO3CPU<Impl>::deallocateContext(int tid, int delay)
568{
569 // Schedule removal of thread data from CPU
570 if (delay){
571 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate "
572 "on cycle %d\n", tid, curTick + cycles(delay));
573 scheduleDeallocateContextEvent(tid, delay);
574 } else {
575 deactivateThread(tid);
576 removeThread(tid);
577 }
578}
579
580template <class Impl>
581void
582FullO3CPU<Impl>::suspendContext(int tid)
583{
584 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
585 deactivateThread(tid);
586 if (activeThreads.size() == 0)
587 unscheduleTickEvent();
588 _status = Idle;
589}
590
591template <class Impl>
592void
593FullO3CPU<Impl>::haltContext(int tid)
594{
595 //For now, this is the same as deallocate
596 DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
597 deallocateContext(tid, 1);
598}
599
600template <class Impl>
601void
602FullO3CPU<Impl>::insertThread(unsigned tid)
603{
604 DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
605 // Will change now that the PC and thread state is internal to the CPU
606 // and not in the ThreadContext.
607#if FULL_SYSTEM
608 ThreadContext *src_tc = system->threadContexts[tid];
609#else
610 ThreadContext *src_tc = tcBase(tid);
611#endif
612
613 //Bind Int Regs to Rename Map
614 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
615 PhysRegIndex phys_reg = freeList.getIntReg();
616
617 renameMap[tid].setEntry(ireg,phys_reg);
618 scoreboard.setReg(phys_reg);
619 }
620
621 //Bind Float Regs to Rename Map
622 for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
623 PhysRegIndex phys_reg = freeList.getFloatReg();
624
625 renameMap[tid].setEntry(freg,phys_reg);
626 scoreboard.setReg(phys_reg);
627 }
628
629 //Copy Thread Data Into RegFile
630 //this->copyFromTC(tid);
631
632 //Set PC/NPC/NNPC
633 setPC(src_tc->readPC(), tid);
634 setNextPC(src_tc->readNextPC(), tid);
635#if ISA_HAS_DELAY_SLOT
636 setNextNPC(src_tc->readNextNPC(), tid);
637#endif
638
639 src_tc->setStatus(ThreadContext::Active);
640
641 activateContext(tid,1);
642
643 //Reset ROB/IQ/LSQ Entries
644 commit.rob->resetEntries();
645 iew.resetEntries();
646}
647
648template <class Impl>
649void
650FullO3CPU<Impl>::removeThread(unsigned tid)
651{
652 DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
653
654 // Copy Thread Data From RegFile
655 // If thread is suspended, it might be re-allocated
656 //this->copyToTC(tid);
657
658 // Unbind Int Regs from Rename Map
659 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
660 PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
661
662 scoreboard.unsetReg(phys_reg);
663 freeList.addReg(phys_reg);
664 }
665
666 // Unbind Float Regs from Rename Map
667 for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
668 PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
669
670 scoreboard.unsetReg(phys_reg);
671 freeList.addReg(phys_reg);
672 }
673
674 // Squash Throughout Pipeline
675 InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum;
676 fetch.squash(0, squash_seq_num, true, tid);
677 decode.squash(tid);
678 rename.squash(squash_seq_num, tid);
679 iew.squash(tid);
680 commit.rob->squash(squash_seq_num, tid);
681
682 assert(iew.ldstQueue.getCount(tid) == 0);
683
684 // Reset ROB/IQ/LSQ Entries
685 if (activeThreads.size() >= 1) {
686 commit.rob->resetEntries();
687 iew.resetEntries();
688 }
689}
690
691
692template <class Impl>
693void
694FullO3CPU<Impl>::activateWhenReady(int tid)
695{
696 DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming"
697 "(e.g. PhysRegs/ROB/IQ/LSQ) \n",
698 tid);
699
700 bool ready = true;
701
702 if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) {
703 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
704 "Phys. Int. Regs.\n",
705 tid);
706 ready = false;
707 } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) {
708 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
709 "Phys. Float. Regs.\n",
710 tid);
711 ready = false;
712 } else if (commit.rob->numFreeEntries() >=
713 commit.rob->entryAmount(activeThreads.size() + 1)) {
714 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
715 "ROB entries.\n",
716 tid);
717 ready = false;
718 } else if (iew.instQueue.numFreeEntries() >=
719 iew.instQueue.entryAmount(activeThreads.size() + 1)) {
720 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
721 "IQ entries.\n",
722 tid);
723 ready = false;
724 } else if (iew.ldstQueue.numFreeEntries() >=
725 iew.ldstQueue.entryAmount(activeThreads.size() + 1)) {
726 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
727 "LSQ entries.\n",
728 tid);
729 ready = false;
730 }
731
732 if (ready) {
733 insertThread(tid);
734
735 contextSwitch = false;
736
737 cpuWaitList.remove(tid);
738 } else {
739 suspendContext(tid);
740
741 //blocks fetch
742 contextSwitch = true;
743
744 //@todo: dont always add to waitlist
745 //do waitlist
746 cpuWaitList.push_back(tid);
747 }
748}
749
750template <class Impl>
751void
752FullO3CPU<Impl>::serialize(std::ostream &os)
753{
754 SimObject::State so_state = SimObject::getState();
755 SERIALIZE_ENUM(so_state);
756 BaseCPU::serialize(os);
757 nameOut(os, csprintf("%s.tickEvent", name()));
758 tickEvent.serialize(os);
759
760 // Use SimpleThread's ability to checkpoint to make it easier to
761 // write out the registers. Also make this static so it doesn't
762 // get instantiated multiple times (causes a panic in statistics).
763 static SimpleThread temp;
764
765 for (int i = 0; i < thread.size(); i++) {
766 nameOut(os, csprintf("%s.xc.%i", name(), i));
767 temp.copyTC(thread[i]->getTC());
768 temp.serialize(os);
769 }
770}
771
772template <class Impl>
773void
774FullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion)
775{
776 SimObject::State so_state;
777 UNSERIALIZE_ENUM(so_state);
778 BaseCPU::unserialize(cp, section);
779 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
780
781 // Use SimpleThread's ability to checkpoint to make it easier to
782 // read in the registers. Also make this static so it doesn't
783 // get instantiated multiple times (causes a panic in statistics).
784 static SimpleThread temp;
785
786 for (int i = 0; i < thread.size(); i++) {
787 temp.copyTC(thread[i]->getTC());
788 temp.unserialize(cp, csprintf("%s.xc.%i", section, i));
789 thread[i]->getTC()->copyArchRegs(temp.getTC());
790 }
791}
792
793template <class Impl>
794unsigned int
795FullO3CPU<Impl>::drain(Event *drain_event)
796{
|
934uint64_t
935FullO3CPU<Impl>::readIntReg(int reg_idx)
936{
937 return regFile.readIntReg(reg_idx);
938}
939
940template <class Impl>
941FloatReg
942FullO3CPU<Impl>::readFloatReg(int reg_idx, int width)
943{
944 return regFile.readFloatReg(reg_idx, width);
945}
946
947template <class Impl>
948FloatReg
949FullO3CPU<Impl>::readFloatReg(int reg_idx)
950{
951 return regFile.readFloatReg(reg_idx);
952}
953
954template <class Impl>
955FloatRegBits
956FullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width)
957{
958 return regFile.readFloatRegBits(reg_idx, width);
959}
960
961template <class Impl>
962FloatRegBits
963FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
964{
965 return regFile.readFloatRegBits(reg_idx);
966}
967
968template <class Impl>
969void
970FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
971{
972 regFile.setIntReg(reg_idx, val);
973}
974
975template <class Impl>
976void
977FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width)
978{
979 regFile.setFloatReg(reg_idx, val, width);
980}
981
982template <class Impl>
983void
984FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
985{
986 regFile.setFloatReg(reg_idx, val);
987}
988
989template <class Impl>
990void
991FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width)
992{
993 regFile.setFloatRegBits(reg_idx, val, width);
994}
995
996template <class Impl>
997void
998FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
999{
1000 regFile.setFloatRegBits(reg_idx, val);
1001}
1002
1003template <class Impl>
1004uint64_t
1005FullO3CPU<Impl>::readArchIntReg(int reg_idx, unsigned tid)
1006{
1007 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1008
1009 return regFile.readIntReg(phys_reg);
1010}
1011
1012template <class Impl>
1013float
1014FullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, unsigned tid)
1015{
1016 int idx = reg_idx + TheISA::FP_Base_DepTag;
1017 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1018
1019 return regFile.readFloatReg(phys_reg);
1020}
1021
1022template <class Impl>
1023double
1024FullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, unsigned tid)
1025{
1026 int idx = reg_idx + TheISA::FP_Base_DepTag;
1027 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1028
1029 return regFile.readFloatReg(phys_reg, 64);
1030}
1031
1032template <class Impl>
1033uint64_t
1034FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, unsigned tid)
1035{
1036 int idx = reg_idx + TheISA::FP_Base_DepTag;
1037 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1038
1039 return regFile.readFloatRegBits(phys_reg);
1040}
1041
1042template <class Impl>
1043void
1044FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, unsigned tid)
1045{
1046 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1047
1048 regFile.setIntReg(phys_reg, val);
1049}
1050
1051template <class Impl>
1052void
1053FullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, unsigned tid)
1054{
1055 int idx = reg_idx + TheISA::FP_Base_DepTag;
1056 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1057
1058 regFile.setFloatReg(phys_reg, val);
1059}
1060
1061template <class Impl>
1062void
1063FullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, unsigned tid)
1064{
1065 int idx = reg_idx + TheISA::FP_Base_DepTag;
1066 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1067
1068 regFile.setFloatReg(phys_reg, val, 64);
1069}
1070
1071template <class Impl>
1072void
1073FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid)
1074{
1075 int idx = reg_idx + TheISA::FP_Base_DepTag;
1076 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1077
1078 regFile.setFloatRegBits(phys_reg, val);
1079}
1080
1081template <class Impl>
1082uint64_t
1083FullO3CPU<Impl>::readPC(unsigned tid)
1084{
1085 return commit.readPC(tid);
1086}
1087
1088template <class Impl>
1089void
1090FullO3CPU<Impl>::setPC(Addr new_PC,unsigned tid)
1091{
1092 commit.setPC(new_PC, tid);
1093}
1094
1095template <class Impl>
1096uint64_t
1097FullO3CPU<Impl>::readNextPC(unsigned tid)
1098{
1099 return commit.readNextPC(tid);
1100}
1101
1102template <class Impl>
1103void
1104FullO3CPU<Impl>::setNextPC(uint64_t val,unsigned tid)
1105{
1106 commit.setNextPC(val, tid);
1107}
1108
1109template <class Impl>
1110uint64_t
1111FullO3CPU<Impl>::readNextNPC(unsigned tid)
1112{
1113 return commit.readNextNPC(tid);
1114}
1115
1116template <class Impl>
1117void
1118FullO3CPU<Impl>::setNextNPC(uint64_t val,unsigned tid)
1119{
1120 commit.setNextNPC(val, tid);
1121}
1122
1123template <class Impl>
1124typename FullO3CPU<Impl>::ListIt
1125FullO3CPU<Impl>::addInst(DynInstPtr &inst)
1126{
1127 instList.push_back(inst);
1128
1129 return --(instList.end());
1130}
1131
1132template <class Impl>
1133void
1134FullO3CPU<Impl>::instDone(unsigned tid)
1135{
1136 // Keep an instruction count.
1137 thread[tid]->numInst++;
1138 thread[tid]->numInsts++;
1139 committedInsts[tid]++;
1140 totalCommittedInsts++;
1141
1142 // Check for instruction-count-based events.
1143 comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1144}
1145
1146template <class Impl>
1147void
1148FullO3CPU<Impl>::addToRemoveList(DynInstPtr &inst)
1149{
1150 removeInstsThisCycle = true;
1151
1152 removeList.push(inst->getInstListIt());
1153}
1154
1155template <class Impl>
1156void
1157FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
1158{
1159 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %#x "
1160 "[sn:%lli]\n",
1161 inst->threadNumber, inst->readPC(), inst->seqNum);
1162
1163 removeInstsThisCycle = true;
1164
1165 // Remove the front instruction.
1166 removeList.push(inst->getInstListIt());
1167}
1168
1169template <class Impl>
1170void
1171FullO3CPU<Impl>::removeInstsNotInROB(unsigned tid,
1172 bool squash_delay_slot,
1173 const InstSeqNum &delay_slot_seq_num)
1174{
1175 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1176 " list.\n", tid);
1177
1178 ListIt end_it;
1179
1180 bool rob_empty = false;
1181
1182 if (instList.empty()) {
1183 return;
1184 } else if (rob.isEmpty(/*tid*/)) {
1185 DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1186 end_it = instList.begin();
1187 rob_empty = true;
1188 } else {
1189 end_it = (rob.readTailInst(tid))->getInstListIt();
1190 DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1191 }
1192
1193 removeInstsThisCycle = true;
1194
1195 ListIt inst_it = instList.end();
1196
1197 inst_it--;
1198
1199 // Walk through the instruction list, removing any instructions
1200 // that were inserted after the given instruction iterator, end_it.
1201 while (inst_it != end_it) {
1202 assert(!instList.empty());
1203
1204#if ISA_HAS_DELAY_SLOT
1205 if(!squash_delay_slot &&
1206 delay_slot_seq_num >= (*inst_it)->seqNum) {
1207 break;
1208 }
1209#endif
1210 squashInstIt(inst_it, tid);
1211
1212 inst_it--;
1213 }
1214
1215 // If the ROB was empty, then we actually need to remove the first
1216 // instruction as well.
1217 if (rob_empty) {
1218 squashInstIt(inst_it, tid);
1219 }
1220}
1221
1222template <class Impl>
1223void
1224FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num,
1225 unsigned tid)
1226{
1227 assert(!instList.empty());
1228
1229 removeInstsThisCycle = true;
1230
1231 ListIt inst_iter = instList.end();
1232
1233 inst_iter--;
1234
1235 DPRINTF(O3CPU, "Deleting instructions from instruction "
1236 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1237 tid, seq_num, (*inst_iter)->seqNum);
1238
1239 while ((*inst_iter)->seqNum > seq_num) {
1240
1241 bool break_loop = (inst_iter == instList.begin());
1242
1243 squashInstIt(inst_iter, tid);
1244
1245 inst_iter--;
1246
1247 if (break_loop)
1248 break;
1249 }
1250}
1251
1252template <class Impl>
1253inline void
1254FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, const unsigned &tid)
1255{
1256 if ((*instIt)->threadNumber == tid) {
1257 DPRINTF(O3CPU, "Squashing instruction, "
1258 "[tid:%i] [sn:%lli] PC %#x\n",
1259 (*instIt)->threadNumber,
1260 (*instIt)->seqNum,
1261 (*instIt)->readPC());
1262
1263 // Mark it as squashed.
1264 (*instIt)->setSquashed();
1265
1266 // @todo: Formulate a consistent method for deleting
1267 // instructions from the instruction list
1268 // Remove the instruction from the list.
1269 removeList.push(instIt);
1270 }
1271}
1272
1273template <class Impl>
1274void
1275FullO3CPU<Impl>::cleanUpRemovedInsts()
1276{
1277 while (!removeList.empty()) {
1278 DPRINTF(O3CPU, "Removing instruction, "
1279 "[tid:%i] [sn:%lli] PC %#x\n",
1280 (*removeList.front())->threadNumber,
1281 (*removeList.front())->seqNum,
1282 (*removeList.front())->readPC());
1283
1284 instList.erase(removeList.front());
1285
1286 removeList.pop();
1287 }
1288
1289 removeInstsThisCycle = false;
1290}
1291/*
1292template <class Impl>
1293void
1294FullO3CPU<Impl>::removeAllInsts()
1295{
1296 instList.clear();
1297}
1298*/
1299template <class Impl>
1300void
1301FullO3CPU<Impl>::dumpInsts()
1302{
1303 int num = 0;
1304
1305 ListIt inst_list_it = instList.begin();
1306
1307 cprintf("Dumping Instruction List\n");
1308
1309 while (inst_list_it != instList.end()) {
1310 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1311 "Squashed:%i\n\n",
1312 num, (*inst_list_it)->readPC(), (*inst_list_it)->threadNumber,
1313 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1314 (*inst_list_it)->isSquashed());
1315 inst_list_it++;
1316 ++num;
1317 }
1318}
1319/*
1320template <class Impl>
1321void
1322FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
1323{
1324 iew.wakeDependents(inst);
1325}
1326*/
1327template <class Impl>
1328void
1329FullO3CPU<Impl>::wakeCPU()
1330{
1331 if (activityRec.active() || tickEvent.scheduled()) {
1332 DPRINTF(Activity, "CPU already running.\n");
1333 return;
1334 }
1335
1336 DPRINTF(Activity, "Waking up CPU\n");
1337
1338 idleCycles += (curTick - 1) - lastRunningCycle;
1339
1340 tickEvent.schedule(curTick);
1341}
1342
1343template <class Impl>
1344int
1345FullO3CPU<Impl>::getFreeTid()
1346{
1347 for (int i=0; i < numThreads; i++) {
1348 if (!tids[i]) {
1349 tids[i] = true;
1350 return i;
1351 }
1352 }
1353
1354 return -1;
1355}
1356
1357template <class Impl>
1358void
1359FullO3CPU<Impl>::doContextSwitch()
1360{
1361 if (contextSwitch) {
1362
1363 //ADD CODE TO DEACTIVE THREAD HERE (???)
1364
1365 for (int tid=0; tid < cpuWaitList.size(); tid++) {
1366 activateWhenReady(tid);
1367 }
1368
1369 if (cpuWaitList.size() == 0)
1370 contextSwitch = true;
1371 }
1372}
1373
1374template <class Impl>
1375void
1376FullO3CPU<Impl>::updateThreadPriority()
1377{
1378 if (activeThreads.size() > 1)
1379 {
1380 //DEFAULT TO ROUND ROBIN SCHEME
1381 //e.g. Move highest priority to end of thread list
1382 list<unsigned>::iterator list_begin = activeThreads.begin();
1383 list<unsigned>::iterator list_end = activeThreads.end();
1384
1385 unsigned high_thread = *list_begin;
1386
1387 activeThreads.erase(list_begin);
1388
1389 activeThreads.push_back(high_thread);
1390 }
1391}
1392
1393// Forward declaration of FullO3CPU.
1394template class FullO3CPU<O3CPUImpl>;
| 977uint64_t
978FullO3CPU<Impl>::readIntReg(int reg_idx)
979{
980 return regFile.readIntReg(reg_idx);
981}
982
983template <class Impl>
984FloatReg
985FullO3CPU<Impl>::readFloatReg(int reg_idx, int width)
986{
987 return regFile.readFloatReg(reg_idx, width);
988}
989
990template <class Impl>
991FloatReg
992FullO3CPU<Impl>::readFloatReg(int reg_idx)
993{
994 return regFile.readFloatReg(reg_idx);
995}
996
997template <class Impl>
998FloatRegBits
999FullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width)
1000{
1001 return regFile.readFloatRegBits(reg_idx, width);
1002}
1003
1004template <class Impl>
1005FloatRegBits
1006FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
1007{
1008 return regFile.readFloatRegBits(reg_idx);
1009}
1010
1011template <class Impl>
1012void
1013FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
1014{
1015 regFile.setIntReg(reg_idx, val);
1016}
1017
1018template <class Impl>
1019void
1020FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width)
1021{
1022 regFile.setFloatReg(reg_idx, val, width);
1023}
1024
1025template <class Impl>
1026void
1027FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
1028{
1029 regFile.setFloatReg(reg_idx, val);
1030}
1031
1032template <class Impl>
1033void
1034FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width)
1035{
1036 regFile.setFloatRegBits(reg_idx, val, width);
1037}
1038
1039template <class Impl>
1040void
1041FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
1042{
1043 regFile.setFloatRegBits(reg_idx, val);
1044}
1045
1046template <class Impl>
1047uint64_t
1048FullO3CPU<Impl>::readArchIntReg(int reg_idx, unsigned tid)
1049{
1050 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1051
1052 return regFile.readIntReg(phys_reg);
1053}
1054
1055template <class Impl>
1056float
1057FullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, unsigned tid)
1058{
1059 int idx = reg_idx + TheISA::FP_Base_DepTag;
1060 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1061
1062 return regFile.readFloatReg(phys_reg);
1063}
1064
1065template <class Impl>
1066double
1067FullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, unsigned tid)
1068{
1069 int idx = reg_idx + TheISA::FP_Base_DepTag;
1070 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1071
1072 return regFile.readFloatReg(phys_reg, 64);
1073}
1074
1075template <class Impl>
1076uint64_t
1077FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, unsigned tid)
1078{
1079 int idx = reg_idx + TheISA::FP_Base_DepTag;
1080 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1081
1082 return regFile.readFloatRegBits(phys_reg);
1083}
1084
1085template <class Impl>
1086void
1087FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, unsigned tid)
1088{
1089 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1090
1091 regFile.setIntReg(phys_reg, val);
1092}
1093
1094template <class Impl>
1095void
1096FullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, unsigned tid)
1097{
1098 int idx = reg_idx + TheISA::FP_Base_DepTag;
1099 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1100
1101 regFile.setFloatReg(phys_reg, val);
1102}
1103
1104template <class Impl>
1105void
1106FullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, unsigned tid)
1107{
1108 int idx = reg_idx + TheISA::FP_Base_DepTag;
1109 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1110
1111 regFile.setFloatReg(phys_reg, val, 64);
1112}
1113
1114template <class Impl>
1115void
1116FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid)
1117{
1118 int idx = reg_idx + TheISA::FP_Base_DepTag;
1119 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1120
1121 regFile.setFloatRegBits(phys_reg, val);
1122}
1123
1124template <class Impl>
1125uint64_t
1126FullO3CPU<Impl>::readPC(unsigned tid)
1127{
1128 return commit.readPC(tid);
1129}
1130
1131template <class Impl>
1132void
1133FullO3CPU<Impl>::setPC(Addr new_PC,unsigned tid)
1134{
1135 commit.setPC(new_PC, tid);
1136}
1137
1138template <class Impl>
1139uint64_t
1140FullO3CPU<Impl>::readNextPC(unsigned tid)
1141{
1142 return commit.readNextPC(tid);
1143}
1144
1145template <class Impl>
1146void
1147FullO3CPU<Impl>::setNextPC(uint64_t val,unsigned tid)
1148{
1149 commit.setNextPC(val, tid);
1150}
1151
1152template <class Impl>
1153uint64_t
1154FullO3CPU<Impl>::readNextNPC(unsigned tid)
1155{
1156 return commit.readNextNPC(tid);
1157}
1158
1159template <class Impl>
1160void
1161FullO3CPU<Impl>::setNextNPC(uint64_t val,unsigned tid)
1162{
1163 commit.setNextNPC(val, tid);
1164}
1165
1166template <class Impl>
1167typename FullO3CPU<Impl>::ListIt
1168FullO3CPU<Impl>::addInst(DynInstPtr &inst)
1169{
1170 instList.push_back(inst);
1171
1172 return --(instList.end());
1173}
1174
1175template <class Impl>
1176void
1177FullO3CPU<Impl>::instDone(unsigned tid)
1178{
1179 // Keep an instruction count.
1180 thread[tid]->numInst++;
1181 thread[tid]->numInsts++;
1182 committedInsts[tid]++;
1183 totalCommittedInsts++;
1184
1185 // Check for instruction-count-based events.
1186 comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1187}
1188
1189template <class Impl>
1190void
1191FullO3CPU<Impl>::addToRemoveList(DynInstPtr &inst)
1192{
1193 removeInstsThisCycle = true;
1194
1195 removeList.push(inst->getInstListIt());
1196}
1197
1198template <class Impl>
1199void
1200FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
1201{
1202 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %#x "
1203 "[sn:%lli]\n",
1204 inst->threadNumber, inst->readPC(), inst->seqNum);
1205
1206 removeInstsThisCycle = true;
1207
1208 // Remove the front instruction.
1209 removeList.push(inst->getInstListIt());
1210}
1211
1212template <class Impl>
1213void
1214FullO3CPU<Impl>::removeInstsNotInROB(unsigned tid,
1215 bool squash_delay_slot,
1216 const InstSeqNum &delay_slot_seq_num)
1217{
1218 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1219 " list.\n", tid);
1220
1221 ListIt end_it;
1222
1223 bool rob_empty = false;
1224
1225 if (instList.empty()) {
1226 return;
1227 } else if (rob.isEmpty(/*tid*/)) {
1228 DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1229 end_it = instList.begin();
1230 rob_empty = true;
1231 } else {
1232 end_it = (rob.readTailInst(tid))->getInstListIt();
1233 DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1234 }
1235
1236 removeInstsThisCycle = true;
1237
1238 ListIt inst_it = instList.end();
1239
1240 inst_it--;
1241
1242 // Walk through the instruction list, removing any instructions
1243 // that were inserted after the given instruction iterator, end_it.
1244 while (inst_it != end_it) {
1245 assert(!instList.empty());
1246
1247#if ISA_HAS_DELAY_SLOT
1248 if(!squash_delay_slot &&
1249 delay_slot_seq_num >= (*inst_it)->seqNum) {
1250 break;
1251 }
1252#endif
1253 squashInstIt(inst_it, tid);
1254
1255 inst_it--;
1256 }
1257
1258 // If the ROB was empty, then we actually need to remove the first
1259 // instruction as well.
1260 if (rob_empty) {
1261 squashInstIt(inst_it, tid);
1262 }
1263}
1264
1265template <class Impl>
1266void
1267FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num,
1268 unsigned tid)
1269{
1270 assert(!instList.empty());
1271
1272 removeInstsThisCycle = true;
1273
1274 ListIt inst_iter = instList.end();
1275
1276 inst_iter--;
1277
1278 DPRINTF(O3CPU, "Deleting instructions from instruction "
1279 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1280 tid, seq_num, (*inst_iter)->seqNum);
1281
1282 while ((*inst_iter)->seqNum > seq_num) {
1283
1284 bool break_loop = (inst_iter == instList.begin());
1285
1286 squashInstIt(inst_iter, tid);
1287
1288 inst_iter--;
1289
1290 if (break_loop)
1291 break;
1292 }
1293}
1294
1295template <class Impl>
1296inline void
1297FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, const unsigned &tid)
1298{
1299 if ((*instIt)->threadNumber == tid) {
1300 DPRINTF(O3CPU, "Squashing instruction, "
1301 "[tid:%i] [sn:%lli] PC %#x\n",
1302 (*instIt)->threadNumber,
1303 (*instIt)->seqNum,
1304 (*instIt)->readPC());
1305
1306 // Mark it as squashed.
1307 (*instIt)->setSquashed();
1308
1309 // @todo: Formulate a consistent method for deleting
1310 // instructions from the instruction list
1311 // Remove the instruction from the list.
1312 removeList.push(instIt);
1313 }
1314}
1315
1316template <class Impl>
1317void
1318FullO3CPU<Impl>::cleanUpRemovedInsts()
1319{
1320 while (!removeList.empty()) {
1321 DPRINTF(O3CPU, "Removing instruction, "
1322 "[tid:%i] [sn:%lli] PC %#x\n",
1323 (*removeList.front())->threadNumber,
1324 (*removeList.front())->seqNum,
1325 (*removeList.front())->readPC());
1326
1327 instList.erase(removeList.front());
1328
1329 removeList.pop();
1330 }
1331
1332 removeInstsThisCycle = false;
1333}
1334/*
1335template <class Impl>
1336void
1337FullO3CPU<Impl>::removeAllInsts()
1338{
1339 instList.clear();
1340}
1341*/
1342template <class Impl>
1343void
1344FullO3CPU<Impl>::dumpInsts()
1345{
1346 int num = 0;
1347
1348 ListIt inst_list_it = instList.begin();
1349
1350 cprintf("Dumping Instruction List\n");
1351
1352 while (inst_list_it != instList.end()) {
1353 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1354 "Squashed:%i\n\n",
1355 num, (*inst_list_it)->readPC(), (*inst_list_it)->threadNumber,
1356 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1357 (*inst_list_it)->isSquashed());
1358 inst_list_it++;
1359 ++num;
1360 }
1361}
1362/*
1363template <class Impl>
1364void
1365FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
1366{
1367 iew.wakeDependents(inst);
1368}
1369*/
1370template <class Impl>
1371void
1372FullO3CPU<Impl>::wakeCPU()
1373{
1374 if (activityRec.active() || tickEvent.scheduled()) {
1375 DPRINTF(Activity, "CPU already running.\n");
1376 return;
1377 }
1378
1379 DPRINTF(Activity, "Waking up CPU\n");
1380
1381 idleCycles += (curTick - 1) - lastRunningCycle;
1382
1383 tickEvent.schedule(curTick);
1384}
1385
1386template <class Impl>
1387int
1388FullO3CPU<Impl>::getFreeTid()
1389{
1390 for (int i=0; i < numThreads; i++) {
1391 if (!tids[i]) {
1392 tids[i] = true;
1393 return i;
1394 }
1395 }
1396
1397 return -1;
1398}
1399
1400template <class Impl>
1401void
1402FullO3CPU<Impl>::doContextSwitch()
1403{
1404 if (contextSwitch) {
1405
1406 //ADD CODE TO DEACTIVE THREAD HERE (???)
1407
1408 for (int tid=0; tid < cpuWaitList.size(); tid++) {
1409 activateWhenReady(tid);
1410 }
1411
1412 if (cpuWaitList.size() == 0)
1413 contextSwitch = true;
1414 }
1415}
1416
1417template <class Impl>
1418void
1419FullO3CPU<Impl>::updateThreadPriority()
1420{
1421 if (activeThreads.size() > 1)
1422 {
1423 //DEFAULT TO ROUND ROBIN SCHEME
1424 //e.g. Move highest priority to end of thread list
1425 list<unsigned>::iterator list_begin = activeThreads.begin();
1426 list<unsigned>::iterator list_end = activeThreads.end();
1427
1428 unsigned high_thread = *list_begin;
1429
1430 activeThreads.erase(list_begin);
1431
1432 activeThreads.push_back(high_thread);
1433 }
1434}
1435
1436// Forward declaration of FullO3CPU.
1437template class FullO3CPU<O3CPUImpl>;
|