1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#include "config/full_system.hh"
33#include "config/use_checker.hh"
34
35#if FULL_SYSTEM
36#include "sim/system.hh"
37#else
38#include "sim/process.hh"
39#endif
40
41#include "cpu/activity.hh"
42#include "cpu/simple_thread.hh"
43#include "cpu/thread_context.hh"
44#include "cpu/o3/isa_specific.hh"
45#include "cpu/o3/cpu.hh"
46
47#include "sim/root.hh"
48#include "sim/stat_control.hh"
49
50#if USE_CHECKER
51#include "cpu/checker/cpu.hh"
52#endif
53
54using namespace std;
55using namespace TheISA;
56
57BaseO3CPU::BaseO3CPU(Params *params)
58 : BaseCPU(params), cpu_id(0)
59{
60}
61
62void
63BaseO3CPU::regStats()
64{
65 BaseCPU::regStats();
66}
67
68template <class Impl>
69FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
70 : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
71{
72}
73
74template <class Impl>
75void
76FullO3CPU<Impl>::TickEvent::process()
77{
78 cpu->tick();
79}
80
81template <class Impl>
82const char *
83FullO3CPU<Impl>::TickEvent::description()
84{
85 return "FullO3CPU tick event";
86}
87
88template <class Impl>
89FullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent()
90 : Event(&mainEventQueue, CPU_Tick_Pri)
91{
92}
93
94template <class Impl>
95void
96FullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num,
97 FullO3CPU<Impl> *thread_cpu)
98{
99 tid = thread_num;
100 cpu = thread_cpu;
101}
102
103template <class Impl>
104void
105FullO3CPU<Impl>::ActivateThreadEvent::process()
106{
107 cpu->activateThread(tid);
108}
109
110template <class Impl>
111const char *
112FullO3CPU<Impl>::ActivateThreadEvent::description()
113{
114 return "FullO3CPU \"Activate Thread\" event";
115}
116
117template <class Impl>
118FullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent()
119 : Event(&mainEventQueue, CPU_Tick_Pri)
120{
121}
122
123template <class Impl>
124void
125FullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num,
126 FullO3CPU<Impl> *thread_cpu)
127{
128 tid = thread_num;
129 cpu = thread_cpu;
130}
131
132template <class Impl>
133void
134FullO3CPU<Impl>::DeallocateContextEvent::process()
135{
136 cpu->deactivateThread(tid);
137 cpu->removeThread(tid);
138}
139
140template <class Impl>
141const char *
142FullO3CPU<Impl>::DeallocateContextEvent::description()
143{
144 return "FullO3CPU \"Deallocate Context\" event";
145}
146
147template <class Impl>
148FullO3CPU<Impl>::FullO3CPU(Params *params)
149 : BaseO3CPU(params),
150 tickEvent(this),
151 removeInstsThisCycle(false),
152 fetch(params),
153 decode(params),
154 rename(params),
155 iew(params),
156 commit(params),
157
158 regFile(params->numPhysIntRegs, params->numPhysFloatRegs),
159
160 freeList(params->numberOfThreads,
161 TheISA::NumIntRegs, params->numPhysIntRegs,
162 TheISA::NumFloatRegs, params->numPhysFloatRegs),
163
164 rob(params->numROBEntries, params->squashWidth,
165 params->smtROBPolicy, params->smtROBThreshold,
166 params->numberOfThreads),
167
168 scoreboard(params->numberOfThreads,
169 TheISA::NumIntRegs, params->numPhysIntRegs,
170 TheISA::NumFloatRegs, params->numPhysFloatRegs,
171 TheISA::NumMiscRegs * number_of_threads,
172 TheISA::ZeroReg),
173
174 timeBuffer(params->backComSize, params->forwardComSize),
175 fetchQueue(params->backComSize, params->forwardComSize),
176 decodeQueue(params->backComSize, params->forwardComSize),
177 renameQueue(params->backComSize, params->forwardComSize),
178 iewQueue(params->backComSize, params->forwardComSize),
179 activityRec(NumStages,
180 params->backComSize + params->forwardComSize,
181 params->activity),
182
183 globalSeqNum(1),
184
185#if FULL_SYSTEM
186 system(params->system),
187 physmem(system->physmem),
188#endif // FULL_SYSTEM
189 mem(params->mem),
190 drainCount(0),
191 deferRegistration(params->deferRegistration),
192 numThreads(number_of_threads)
193{
194 _status = Idle;
195
196 checker = NULL;
197
198 if (params->checker) {
199#if USE_CHECKER
200 BaseCPU *temp_checker = params->checker;
201 checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
202 checker->setMemory(mem);
203#if FULL_SYSTEM
204 checker->setSystem(params->system);
205#endif
206#else
207 panic("Checker enabled but not compiled in!");
208#endif // USE_CHECKER
209 }
210
211#if !FULL_SYSTEM
212 thread.resize(number_of_threads);
213 tids.resize(number_of_threads);
214#endif
215
216 // The stages also need their CPU pointer setup. However this
217 // must be done at the upper level CPU because they have pointers
218 // to the upper level CPU, and not this FullO3CPU.
219
220 // Set up Pointers to the activeThreads list for each stage
221 fetch.setActiveThreads(&activeThreads);
222 decode.setActiveThreads(&activeThreads);
223 rename.setActiveThreads(&activeThreads);
224 iew.setActiveThreads(&activeThreads);
225 commit.setActiveThreads(&activeThreads);
226
227 // Give each of the stages the time buffer they will use.
228 fetch.setTimeBuffer(&timeBuffer);
229 decode.setTimeBuffer(&timeBuffer);
230 rename.setTimeBuffer(&timeBuffer);
231 iew.setTimeBuffer(&timeBuffer);
232 commit.setTimeBuffer(&timeBuffer);
233
234 // Also setup each of the stages' queues.
235 fetch.setFetchQueue(&fetchQueue);
236 decode.setFetchQueue(&fetchQueue);
237 commit.setFetchQueue(&fetchQueue);
238 decode.setDecodeQueue(&decodeQueue);
239 rename.setDecodeQueue(&decodeQueue);
240 rename.setRenameQueue(&renameQueue);
241 iew.setRenameQueue(&renameQueue);
242 iew.setIEWQueue(&iewQueue);
243 commit.setIEWQueue(&iewQueue);
244 commit.setRenameQueue(&renameQueue);
245
246 commit.setIEWStage(&iew);
247 rename.setIEWStage(&iew);
248 rename.setCommitStage(&commit);
249
250#if !FULL_SYSTEM
251 int active_threads = params->workload.size();
252
253 if (active_threads > Impl::MaxThreads) {
254 panic("Workload Size too large. Increase the 'MaxThreads'"
255 "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or "
256 "edit your workload size.");
257 }
258#else
259 int active_threads = 1;
260#endif
261
262 //Make Sure That this a Valid Architeture
263 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs);
264 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
265
266 rename.setScoreboard(&scoreboard);
267 iew.setScoreboard(&scoreboard);
268
269 // Setup the rename map for whichever stages need it.
270 PhysRegIndex lreg_idx = 0;
271 PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs
272
273 for (int tid=0; tid < numThreads; tid++) {
274 bool bindRegs = (tid <= active_threads - 1);
275
276 commitRenameMap[tid].init(TheISA::NumIntRegs,
277 params->numPhysIntRegs,
278 lreg_idx, //Index for Logical. Regs
279
280 TheISA::NumFloatRegs,
281 params->numPhysFloatRegs,
282 freg_idx, //Index for Float Regs
283
284 TheISA::NumMiscRegs,
285
286 TheISA::ZeroReg,
287 TheISA::ZeroReg,
288
289 tid,
290 false);
291
292 renameMap[tid].init(TheISA::NumIntRegs,
293 params->numPhysIntRegs,
294 lreg_idx, //Index for Logical. Regs
295
296 TheISA::NumFloatRegs,
297 params->numPhysFloatRegs,
298 freg_idx, //Index for Float Regs
299
300 TheISA::NumMiscRegs,
301
302 TheISA::ZeroReg,
303 TheISA::ZeroReg,
304
305 tid,
306 bindRegs);
307 }
308
309 rename.setRenameMap(renameMap);
310 commit.setRenameMap(commitRenameMap);
311
312 // Give renameMap & rename stage access to the freeList;
313 for (int i=0; i < numThreads; i++) {
314 renameMap[i].setFreeList(&freeList);
315 }
316 rename.setFreeList(&freeList);
317
318 // Setup the ROB for whichever stages need it.
319 commit.setROB(&rob);
320
321 lastRunningCycle = curTick;
322
323 lastActivatedCycle = -1;
324
325 contextSwitch = false;
326}
327
328template <class Impl>
329FullO3CPU<Impl>::~FullO3CPU()
330{
331}
332
333template <class Impl>
334void
335FullO3CPU<Impl>::fullCPURegStats()
336{
337 BaseO3CPU::regStats();
338
339 // Register any of the O3CPU's stats here.
340 timesIdled
341 .name(name() + ".timesIdled")
342 .desc("Number of times that the entire CPU went into an idle state and"
343 " unscheduled itself")
344 .prereq(timesIdled);
345
346 idleCycles
347 .name(name() + ".idleCycles")
348 .desc("Total number of cycles that the CPU has spent unscheduled due "
349 "to idling")
350 .prereq(idleCycles);
351
352 // Number of Instructions simulated
353 // --------------------------------
354 // Should probably be in Base CPU but need templated
355 // MaxThreads so put in here instead
356 committedInsts
357 .init(numThreads)
358 .name(name() + ".committedInsts")
359 .desc("Number of Instructions Simulated");
360
361 totalCommittedInsts
362 .name(name() + ".committedInsts_total")
363 .desc("Number of Instructions Simulated");
364
365 cpi
366 .name(name() + ".cpi")
367 .desc("CPI: Cycles Per Instruction")
368 .precision(6);
369 cpi = simTicks / committedInsts;
370
371 totalCpi
372 .name(name() + ".cpi_total")
373 .desc("CPI: Total CPI of All Threads")
374 .precision(6);
375 totalCpi = simTicks / totalCommittedInsts;
376
377 ipc
378 .name(name() + ".ipc")
379 .desc("IPC: Instructions Per Cycle")
380 .precision(6);
381 ipc = committedInsts / simTicks;
382
383 totalIpc
384 .name(name() + ".ipc_total")
385 .desc("IPC: Total IPC of All Threads")
386 .precision(6);
387 totalIpc = totalCommittedInsts / simTicks;
388
389}
390
391template <class Impl>
392Port *
393FullO3CPU<Impl>::getPort(const std::string &if_name, int idx)
394{
395 if (if_name == "dcache_port")
396 return iew.getDcachePort();
397 else if (if_name == "icache_port")
398 return fetch.getIcachePort();
399 else
400 panic("No Such Port\n");
401}
402
403template <class Impl>
404void
405FullO3CPU<Impl>::tick()
406{
407 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
408
409 ++numCycles;
410
411// activity = false;
412
413 //Tick each of the stages
414 fetch.tick();
415
416 decode.tick();
417
418 rename.tick();
419
420 iew.tick();
421
422 commit.tick();
423
424#if !FULL_SYSTEM
425 doContextSwitch();
426#endif
427
428 // Now advance the time buffers
429 timeBuffer.advance();
430
431 fetchQueue.advance();
432 decodeQueue.advance();
433 renameQueue.advance();
434 iewQueue.advance();
435
436 activityRec.advance();
437
438 if (removeInstsThisCycle) {
439 cleanUpRemovedInsts();
440 }
441
442 if (!tickEvent.scheduled()) {
443 if (_status == SwitchedOut ||
444 getState() == SimObject::Drained) {
445 // increment stat
446 lastRunningCycle = curTick;
447 } else if (!activityRec.active()) {
448 lastRunningCycle = curTick;
449 timesIdled++;
450 } else {
451 tickEvent.schedule(curTick + cycles(1));
452 }
453 }
454
455#if !FULL_SYSTEM
456 updateThreadPriority();
457#endif
458
459}
460
461template <class Impl>
462void
463FullO3CPU<Impl>::init()
464{
465 if (!deferRegistration) {
466 registerThreadContexts();
467 }
468
469 // Set inSyscall so that the CPU doesn't squash when initially
470 // setting up registers.
471 for (int i = 0; i < number_of_threads; ++i)
472 thread[i]->inSyscall = true;
473
474 for (int tid=0; tid < number_of_threads; tid++) {
475#if FULL_SYSTEM
476 ThreadContext *src_tc = threadContexts[tid];
477#else
478 ThreadContext *src_tc = thread[tid]->getTC();
479#endif
480 // Threads start in the Suspended State
481 if (src_tc->status() != ThreadContext::Suspended) {
482 continue;
483 }
484
485#if FULL_SYSTEM
486 TheISA::initCPU(src_tc, src_tc->readCpuId());
487#endif
488 }
489
490 // Clear inSyscall.
491 for (int i = 0; i < number_of_threads; ++i)
492 thread[i]->inSyscall = false;
493
494 // Initialize stages.
495 fetch.initStage();
496 iew.initStage();
497 rename.initStage();
498 commit.initStage();
499
500 commit.setThreads(thread);
501}
502
503template <class Impl>
504void
505FullO3CPU<Impl>::activateThread(unsigned tid)
506{
507 list<unsigned>::iterator isActive = find(
508 activeThreads.begin(), activeThreads.end(), tid);
509
510 if (isActive == activeThreads.end()) {
511 DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n",
512 tid);
513
514 activeThreads.push_back(tid);
515 }
516}
517
518template <class Impl>
519void
520FullO3CPU<Impl>::deactivateThread(unsigned tid)
521{
522 //Remove From Active List, if Active
523 list<unsigned>::iterator thread_it =
524 find(activeThreads.begin(), activeThreads.end(), tid);
525
526 if (thread_it != activeThreads.end()) {
527 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
528 tid);
529 activeThreads.erase(thread_it);
530 }
531}
532
533template <class Impl>
534void
535FullO3CPU<Impl>::activateContext(int tid, int delay)
536{
537 // Needs to set each stage to running as well.
538 if (delay){
539 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate "
540 "on cycle %d\n", tid, curTick + cycles(delay));
541 scheduleActivateThreadEvent(tid, delay);
542 } else {
543 activateThread(tid);
544 }
545
546 if(lastActivatedCycle < curTick) {
547 scheduleTickEvent(delay);
548
549 // Be sure to signal that there's some activity so the CPU doesn't
550 // deschedule itself.
551 activityRec.activity();
552 fetch.wakeFromQuiesce();
553
554 lastActivatedCycle = curTick;
555
556 _status = Running;
557 }
558}
559
560template <class Impl>
561void
562FullO3CPU<Impl>::deallocateContext(int tid, int delay)
563{
564 // Schedule removal of thread data from CPU
565 if (delay){
566 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate "
567 "on cycle %d\n", tid, curTick + cycles(delay));
568 scheduleDeallocateContextEvent(tid, delay);
569 } else {
570 deactivateThread(tid);
571 removeThread(tid);
572 }
573}
574
575template <class Impl>
576void
577FullO3CPU<Impl>::suspendContext(int tid)
578{
579 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
| 1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#include "config/full_system.hh"
33#include "config/use_checker.hh"
34
35#if FULL_SYSTEM
36#include "sim/system.hh"
37#else
38#include "sim/process.hh"
39#endif
40
41#include "cpu/activity.hh"
42#include "cpu/simple_thread.hh"
43#include "cpu/thread_context.hh"
44#include "cpu/o3/isa_specific.hh"
45#include "cpu/o3/cpu.hh"
46
47#include "sim/root.hh"
48#include "sim/stat_control.hh"
49
50#if USE_CHECKER
51#include "cpu/checker/cpu.hh"
52#endif
53
54using namespace std;
55using namespace TheISA;
56
57BaseO3CPU::BaseO3CPU(Params *params)
58 : BaseCPU(params), cpu_id(0)
59{
60}
61
62void
63BaseO3CPU::regStats()
64{
65 BaseCPU::regStats();
66}
67
68template <class Impl>
69FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
70 : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
71{
72}
73
74template <class Impl>
75void
76FullO3CPU<Impl>::TickEvent::process()
77{
78 cpu->tick();
79}
80
81template <class Impl>
82const char *
83FullO3CPU<Impl>::TickEvent::description()
84{
85 return "FullO3CPU tick event";
86}
87
88template <class Impl>
89FullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent()
90 : Event(&mainEventQueue, CPU_Tick_Pri)
91{
92}
93
94template <class Impl>
95void
96FullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num,
97 FullO3CPU<Impl> *thread_cpu)
98{
99 tid = thread_num;
100 cpu = thread_cpu;
101}
102
103template <class Impl>
104void
105FullO3CPU<Impl>::ActivateThreadEvent::process()
106{
107 cpu->activateThread(tid);
108}
109
110template <class Impl>
111const char *
112FullO3CPU<Impl>::ActivateThreadEvent::description()
113{
114 return "FullO3CPU \"Activate Thread\" event";
115}
116
117template <class Impl>
118FullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent()
119 : Event(&mainEventQueue, CPU_Tick_Pri)
120{
121}
122
123template <class Impl>
124void
125FullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num,
126 FullO3CPU<Impl> *thread_cpu)
127{
128 tid = thread_num;
129 cpu = thread_cpu;
130}
131
132template <class Impl>
133void
134FullO3CPU<Impl>::DeallocateContextEvent::process()
135{
136 cpu->deactivateThread(tid);
137 cpu->removeThread(tid);
138}
139
140template <class Impl>
141const char *
142FullO3CPU<Impl>::DeallocateContextEvent::description()
143{
144 return "FullO3CPU \"Deallocate Context\" event";
145}
146
147template <class Impl>
148FullO3CPU<Impl>::FullO3CPU(Params *params)
149 : BaseO3CPU(params),
150 tickEvent(this),
151 removeInstsThisCycle(false),
152 fetch(params),
153 decode(params),
154 rename(params),
155 iew(params),
156 commit(params),
157
158 regFile(params->numPhysIntRegs, params->numPhysFloatRegs),
159
160 freeList(params->numberOfThreads,
161 TheISA::NumIntRegs, params->numPhysIntRegs,
162 TheISA::NumFloatRegs, params->numPhysFloatRegs),
163
164 rob(params->numROBEntries, params->squashWidth,
165 params->smtROBPolicy, params->smtROBThreshold,
166 params->numberOfThreads),
167
168 scoreboard(params->numberOfThreads,
169 TheISA::NumIntRegs, params->numPhysIntRegs,
170 TheISA::NumFloatRegs, params->numPhysFloatRegs,
171 TheISA::NumMiscRegs * number_of_threads,
172 TheISA::ZeroReg),
173
174 timeBuffer(params->backComSize, params->forwardComSize),
175 fetchQueue(params->backComSize, params->forwardComSize),
176 decodeQueue(params->backComSize, params->forwardComSize),
177 renameQueue(params->backComSize, params->forwardComSize),
178 iewQueue(params->backComSize, params->forwardComSize),
179 activityRec(NumStages,
180 params->backComSize + params->forwardComSize,
181 params->activity),
182
183 globalSeqNum(1),
184
185#if FULL_SYSTEM
186 system(params->system),
187 physmem(system->physmem),
188#endif // FULL_SYSTEM
189 mem(params->mem),
190 drainCount(0),
191 deferRegistration(params->deferRegistration),
192 numThreads(number_of_threads)
193{
194 _status = Idle;
195
196 checker = NULL;
197
198 if (params->checker) {
199#if USE_CHECKER
200 BaseCPU *temp_checker = params->checker;
201 checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
202 checker->setMemory(mem);
203#if FULL_SYSTEM
204 checker->setSystem(params->system);
205#endif
206#else
207 panic("Checker enabled but not compiled in!");
208#endif // USE_CHECKER
209 }
210
211#if !FULL_SYSTEM
212 thread.resize(number_of_threads);
213 tids.resize(number_of_threads);
214#endif
215
216 // The stages also need their CPU pointer setup. However this
217 // must be done at the upper level CPU because they have pointers
218 // to the upper level CPU, and not this FullO3CPU.
219
220 // Set up Pointers to the activeThreads list for each stage
221 fetch.setActiveThreads(&activeThreads);
222 decode.setActiveThreads(&activeThreads);
223 rename.setActiveThreads(&activeThreads);
224 iew.setActiveThreads(&activeThreads);
225 commit.setActiveThreads(&activeThreads);
226
227 // Give each of the stages the time buffer they will use.
228 fetch.setTimeBuffer(&timeBuffer);
229 decode.setTimeBuffer(&timeBuffer);
230 rename.setTimeBuffer(&timeBuffer);
231 iew.setTimeBuffer(&timeBuffer);
232 commit.setTimeBuffer(&timeBuffer);
233
234 // Also setup each of the stages' queues.
235 fetch.setFetchQueue(&fetchQueue);
236 decode.setFetchQueue(&fetchQueue);
237 commit.setFetchQueue(&fetchQueue);
238 decode.setDecodeQueue(&decodeQueue);
239 rename.setDecodeQueue(&decodeQueue);
240 rename.setRenameQueue(&renameQueue);
241 iew.setRenameQueue(&renameQueue);
242 iew.setIEWQueue(&iewQueue);
243 commit.setIEWQueue(&iewQueue);
244 commit.setRenameQueue(&renameQueue);
245
246 commit.setIEWStage(&iew);
247 rename.setIEWStage(&iew);
248 rename.setCommitStage(&commit);
249
250#if !FULL_SYSTEM
251 int active_threads = params->workload.size();
252
253 if (active_threads > Impl::MaxThreads) {
254 panic("Workload Size too large. Increase the 'MaxThreads'"
255 "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or "
256 "edit your workload size.");
257 }
258#else
259 int active_threads = 1;
260#endif
261
262 //Make Sure That this a Valid Architeture
263 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs);
264 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
265
266 rename.setScoreboard(&scoreboard);
267 iew.setScoreboard(&scoreboard);
268
269 // Setup the rename map for whichever stages need it.
270 PhysRegIndex lreg_idx = 0;
271 PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs
272
273 for (int tid=0; tid < numThreads; tid++) {
274 bool bindRegs = (tid <= active_threads - 1);
275
276 commitRenameMap[tid].init(TheISA::NumIntRegs,
277 params->numPhysIntRegs,
278 lreg_idx, //Index for Logical. Regs
279
280 TheISA::NumFloatRegs,
281 params->numPhysFloatRegs,
282 freg_idx, //Index for Float Regs
283
284 TheISA::NumMiscRegs,
285
286 TheISA::ZeroReg,
287 TheISA::ZeroReg,
288
289 tid,
290 false);
291
292 renameMap[tid].init(TheISA::NumIntRegs,
293 params->numPhysIntRegs,
294 lreg_idx, //Index for Logical. Regs
295
296 TheISA::NumFloatRegs,
297 params->numPhysFloatRegs,
298 freg_idx, //Index for Float Regs
299
300 TheISA::NumMiscRegs,
301
302 TheISA::ZeroReg,
303 TheISA::ZeroReg,
304
305 tid,
306 bindRegs);
307 }
308
309 rename.setRenameMap(renameMap);
310 commit.setRenameMap(commitRenameMap);
311
312 // Give renameMap & rename stage access to the freeList;
313 for (int i=0; i < numThreads; i++) {
314 renameMap[i].setFreeList(&freeList);
315 }
316 rename.setFreeList(&freeList);
317
318 // Setup the ROB for whichever stages need it.
319 commit.setROB(&rob);
320
321 lastRunningCycle = curTick;
322
323 lastActivatedCycle = -1;
324
325 contextSwitch = false;
326}
327
328template <class Impl>
329FullO3CPU<Impl>::~FullO3CPU()
330{
331}
332
333template <class Impl>
334void
335FullO3CPU<Impl>::fullCPURegStats()
336{
337 BaseO3CPU::regStats();
338
339 // Register any of the O3CPU's stats here.
340 timesIdled
341 .name(name() + ".timesIdled")
342 .desc("Number of times that the entire CPU went into an idle state and"
343 " unscheduled itself")
344 .prereq(timesIdled);
345
346 idleCycles
347 .name(name() + ".idleCycles")
348 .desc("Total number of cycles that the CPU has spent unscheduled due "
349 "to idling")
350 .prereq(idleCycles);
351
352 // Number of Instructions simulated
353 // --------------------------------
354 // Should probably be in Base CPU but need templated
355 // MaxThreads so put in here instead
356 committedInsts
357 .init(numThreads)
358 .name(name() + ".committedInsts")
359 .desc("Number of Instructions Simulated");
360
361 totalCommittedInsts
362 .name(name() + ".committedInsts_total")
363 .desc("Number of Instructions Simulated");
364
365 cpi
366 .name(name() + ".cpi")
367 .desc("CPI: Cycles Per Instruction")
368 .precision(6);
369 cpi = simTicks / committedInsts;
370
371 totalCpi
372 .name(name() + ".cpi_total")
373 .desc("CPI: Total CPI of All Threads")
374 .precision(6);
375 totalCpi = simTicks / totalCommittedInsts;
376
377 ipc
378 .name(name() + ".ipc")
379 .desc("IPC: Instructions Per Cycle")
380 .precision(6);
381 ipc = committedInsts / simTicks;
382
383 totalIpc
384 .name(name() + ".ipc_total")
385 .desc("IPC: Total IPC of All Threads")
386 .precision(6);
387 totalIpc = totalCommittedInsts / simTicks;
388
389}
390
391template <class Impl>
392Port *
393FullO3CPU<Impl>::getPort(const std::string &if_name, int idx)
394{
395 if (if_name == "dcache_port")
396 return iew.getDcachePort();
397 else if (if_name == "icache_port")
398 return fetch.getIcachePort();
399 else
400 panic("No Such Port\n");
401}
402
403template <class Impl>
404void
405FullO3CPU<Impl>::tick()
406{
407 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
408
409 ++numCycles;
410
411// activity = false;
412
413 //Tick each of the stages
414 fetch.tick();
415
416 decode.tick();
417
418 rename.tick();
419
420 iew.tick();
421
422 commit.tick();
423
424#if !FULL_SYSTEM
425 doContextSwitch();
426#endif
427
428 // Now advance the time buffers
429 timeBuffer.advance();
430
431 fetchQueue.advance();
432 decodeQueue.advance();
433 renameQueue.advance();
434 iewQueue.advance();
435
436 activityRec.advance();
437
438 if (removeInstsThisCycle) {
439 cleanUpRemovedInsts();
440 }
441
442 if (!tickEvent.scheduled()) {
443 if (_status == SwitchedOut ||
444 getState() == SimObject::Drained) {
445 // increment stat
446 lastRunningCycle = curTick;
447 } else if (!activityRec.active()) {
448 lastRunningCycle = curTick;
449 timesIdled++;
450 } else {
451 tickEvent.schedule(curTick + cycles(1));
452 }
453 }
454
455#if !FULL_SYSTEM
456 updateThreadPriority();
457#endif
458
459}
460
461template <class Impl>
462void
463FullO3CPU<Impl>::init()
464{
465 if (!deferRegistration) {
466 registerThreadContexts();
467 }
468
469 // Set inSyscall so that the CPU doesn't squash when initially
470 // setting up registers.
471 for (int i = 0; i < number_of_threads; ++i)
472 thread[i]->inSyscall = true;
473
474 for (int tid=0; tid < number_of_threads; tid++) {
475#if FULL_SYSTEM
476 ThreadContext *src_tc = threadContexts[tid];
477#else
478 ThreadContext *src_tc = thread[tid]->getTC();
479#endif
480 // Threads start in the Suspended State
481 if (src_tc->status() != ThreadContext::Suspended) {
482 continue;
483 }
484
485#if FULL_SYSTEM
486 TheISA::initCPU(src_tc, src_tc->readCpuId());
487#endif
488 }
489
490 // Clear inSyscall.
491 for (int i = 0; i < number_of_threads; ++i)
492 thread[i]->inSyscall = false;
493
494 // Initialize stages.
495 fetch.initStage();
496 iew.initStage();
497 rename.initStage();
498 commit.initStage();
499
500 commit.setThreads(thread);
501}
502
503template <class Impl>
504void
505FullO3CPU<Impl>::activateThread(unsigned tid)
506{
507 list<unsigned>::iterator isActive = find(
508 activeThreads.begin(), activeThreads.end(), tid);
509
510 if (isActive == activeThreads.end()) {
511 DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n",
512 tid);
513
514 activeThreads.push_back(tid);
515 }
516}
517
518template <class Impl>
519void
520FullO3CPU<Impl>::deactivateThread(unsigned tid)
521{
522 //Remove From Active List, if Active
523 list<unsigned>::iterator thread_it =
524 find(activeThreads.begin(), activeThreads.end(), tid);
525
526 if (thread_it != activeThreads.end()) {
527 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
528 tid);
529 activeThreads.erase(thread_it);
530 }
531}
532
533template <class Impl>
534void
535FullO3CPU<Impl>::activateContext(int tid, int delay)
536{
537 // Needs to set each stage to running as well.
538 if (delay){
539 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate "
540 "on cycle %d\n", tid, curTick + cycles(delay));
541 scheduleActivateThreadEvent(tid, delay);
542 } else {
543 activateThread(tid);
544 }
545
546 if(lastActivatedCycle < curTick) {
547 scheduleTickEvent(delay);
548
549 // Be sure to signal that there's some activity so the CPU doesn't
550 // deschedule itself.
551 activityRec.activity();
552 fetch.wakeFromQuiesce();
553
554 lastActivatedCycle = curTick;
555
556 _status = Running;
557 }
558}
559
560template <class Impl>
561void
562FullO3CPU<Impl>::deallocateContext(int tid, int delay)
563{
564 // Schedule removal of thread data from CPU
565 if (delay){
566 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate "
567 "on cycle %d\n", tid, curTick + cycles(delay));
568 scheduleDeallocateContextEvent(tid, delay);
569 } else {
570 deactivateThread(tid);
571 removeThread(tid);
572 }
573}
574
575template <class Impl>
576void
577FullO3CPU<Impl>::suspendContext(int tid)
578{
579 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
|
581 if (activeThreads.size() == 0)
582 unscheduleTickEvent();
583 _status = Idle;
584}
585
586template <class Impl>
587void
588FullO3CPU<Impl>::haltContext(int tid)
589{
590 //For now, this is the same as deallocate
591 DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
592 deallocateContext(tid, 1);
593}
594
595template <class Impl>
596void
597FullO3CPU<Impl>::insertThread(unsigned tid)
598{
599 DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
600 // Will change now that the PC and thread state is internal to the CPU
601 // and not in the ThreadContext.
602#if FULL_SYSTEM
603 ThreadContext *src_tc = system->threadContexts[tid];
604#else
605 ThreadContext *src_tc = tcBase(tid);
606#endif
607
608 //Bind Int Regs to Rename Map
609 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
610 PhysRegIndex phys_reg = freeList.getIntReg();
611
612 renameMap[tid].setEntry(ireg,phys_reg);
613 scoreboard.setReg(phys_reg);
614 }
615
616 //Bind Float Regs to Rename Map
617 for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
618 PhysRegIndex phys_reg = freeList.getFloatReg();
619
620 renameMap[tid].setEntry(freg,phys_reg);
621 scoreboard.setReg(phys_reg);
622 }
623
624 //Copy Thread Data Into RegFile
625 //this->copyFromTC(tid);
626
627 //Set PC/NPC/NNPC
628 setPC(src_tc->readPC(), tid);
629 setNextPC(src_tc->readNextPC(), tid);
630#if THE_ISA != ALPHA_ISA
631 setNextNPC(src_tc->readNextNPC(), tid);
632#endif
633
634 src_tc->setStatus(ThreadContext::Active);
635
636 activateContext(tid,1);
637
638 //Reset ROB/IQ/LSQ Entries
639 commit.rob->resetEntries();
640 iew.resetEntries();
641}
642
643template <class Impl>
644void
645FullO3CPU<Impl>::removeThread(unsigned tid)
646{
647 DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
648
649 // Copy Thread Data From RegFile
650 // If thread is suspended, it might be re-allocated
651 //this->copyToTC(tid);
652
653 // Unbind Int Regs from Rename Map
654 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
655 PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
656
657 scoreboard.unsetReg(phys_reg);
658 freeList.addReg(phys_reg);
659 }
660
661 // Unbind Float Regs from Rename Map
662 for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
663 PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
664
665 scoreboard.unsetReg(phys_reg);
666 freeList.addReg(phys_reg);
667 }
668
669 // Squash Throughout Pipeline
670 fetch.squash(0,tid);
671 decode.squash(tid);
672 rename.squash(tid);
673 iew.squash(tid);
674 commit.rob->squash(commit.rob->readHeadInst(tid)->seqNum, tid);
675
676 assert(iew.ldstQueue.getCount(tid) == 0);
677
678 // Reset ROB/IQ/LSQ Entries
679 if (activeThreads.size() >= 1) {
680 commit.rob->resetEntries();
681 iew.resetEntries();
682 }
683}
684
685
686template <class Impl>
687void
688FullO3CPU<Impl>::activateWhenReady(int tid)
689{
690 DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming"
691 "(e.g. PhysRegs/ROB/IQ/LSQ) \n",
692 tid);
693
694 bool ready = true;
695
696 if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) {
697 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
698 "Phys. Int. Regs.\n",
699 tid);
700 ready = false;
701 } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) {
702 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
703 "Phys. Float. Regs.\n",
704 tid);
705 ready = false;
706 } else if (commit.rob->numFreeEntries() >=
707 commit.rob->entryAmount(activeThreads.size() + 1)) {
708 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
709 "ROB entries.\n",
710 tid);
711 ready = false;
712 } else if (iew.instQueue.numFreeEntries() >=
713 iew.instQueue.entryAmount(activeThreads.size() + 1)) {
714 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
715 "IQ entries.\n",
716 tid);
717 ready = false;
718 } else if (iew.ldstQueue.numFreeEntries() >=
719 iew.ldstQueue.entryAmount(activeThreads.size() + 1)) {
720 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
721 "LSQ entries.\n",
722 tid);
723 ready = false;
724 }
725
726 if (ready) {
727 insertThread(tid);
728
729 contextSwitch = false;
730
731 cpuWaitList.remove(tid);
732 } else {
733 suspendContext(tid);
734
735 //blocks fetch
736 contextSwitch = true;
737
738 //@todo: dont always add to waitlist
739 //do waitlist
740 cpuWaitList.push_back(tid);
741 }
742}
743
744template <class Impl>
745void
746FullO3CPU<Impl>::serialize(std::ostream &os)
747{
748 SERIALIZE_ENUM(_status);
749 BaseCPU::serialize(os);
750 nameOut(os, csprintf("%s.tickEvent", name()));
751 tickEvent.serialize(os);
752
753 // Use SimpleThread's ability to checkpoint to make it easier to
754 // write out the registers. Also make this static so it doesn't
755 // get instantiated multiple times (causes a panic in statistics).
756 static SimpleThread temp;
757
758 for (int i = 0; i < thread.size(); i++) {
759 nameOut(os, csprintf("%s.xc.%i", name(), i));
760 temp.copyTC(thread[i]->getTC());
761 temp.serialize(os);
762 }
763}
764
765template <class Impl>
766void
767FullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion)
768{
769 UNSERIALIZE_ENUM(_status);
770 BaseCPU::unserialize(cp, section);
771 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
772
773 // Use SimpleThread's ability to checkpoint to make it easier to
774 // read in the registers. Also make this static so it doesn't
775 // get instantiated multiple times (causes a panic in statistics).
776 static SimpleThread temp;
777
778 for (int i = 0; i < thread.size(); i++) {
779 temp.copyTC(thread[i]->getTC());
780 temp.unserialize(cp, csprintf("%s.xc.%i", section, i));
781 thread[i]->getTC()->copyArchRegs(temp.getTC());
782 }
783}
784
785template <class Impl>
786unsigned int
787FullO3CPU<Impl>::drain(Event *drain_event)
788{
789 drainCount = 0;
790 fetch.drain();
791 decode.drain();
792 rename.drain();
793 iew.drain();
794 commit.drain();
795
796 // Wake the CPU and record activity so everything can drain out if
797 // the CPU was not able to immediately drain.
798 if (getState() != SimObject::Drained) {
799 // A bit of a hack...set the drainEvent after all the drain()
800 // calls have been made, that way if all of the stages drain
801 // immediately, the signalDrained() function knows not to call
802 // process on the drain event.
803 drainEvent = drain_event;
804
805 wakeCPU();
806 activityRec.activity();
807
808 return 1;
809 } else {
810 return 0;
811 }
812}
813
814template <class Impl>
815void
816FullO3CPU<Impl>::resume()
817{
818 assert(system->getMemoryMode() == System::Timing);
819 fetch.resume();
820 decode.resume();
821 rename.resume();
822 iew.resume();
823 commit.resume();
824
825 changeState(SimObject::Running);
826
827 if (_status == SwitchedOut || _status == Idle)
828 return;
829
830 if (!tickEvent.scheduled())
831 tickEvent.schedule(curTick);
832 _status = Running;
833}
834
835template <class Impl>
836void
837FullO3CPU<Impl>::signalDrained()
838{
839 if (++drainCount == NumStages) {
840 if (tickEvent.scheduled())
841 tickEvent.squash();
842
843 changeState(SimObject::Drained);
844
845 if (drainEvent) {
846 drainEvent->process();
847 drainEvent = NULL;
848 }
849 }
850 assert(drainCount <= 5);
851}
852
853template <class Impl>
854void
855FullO3CPU<Impl>::switchOut()
856{
857 fetch.switchOut();
858 rename.switchOut();
859 commit.switchOut();
860 instList.clear();
861 while (!removeList.empty()) {
862 removeList.pop();
863 }
864
865 _status = SwitchedOut;
866#if USE_CHECKER
867 if (checker)
868 checker->switchOut();
869#endif
870}
871
872template <class Impl>
873void
874FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
875{
876 // Flush out any old data from the time buffers.
877 for (int i = 0; i < timeBuffer.getSize(); ++i) {
878 timeBuffer.advance();
879 fetchQueue.advance();
880 decodeQueue.advance();
881 renameQueue.advance();
882 iewQueue.advance();
883 }
884
885 activityRec.reset();
886
887 BaseCPU::takeOverFrom(oldCPU);
888
889 fetch.takeOverFrom();
890 decode.takeOverFrom();
891 rename.takeOverFrom();
892 iew.takeOverFrom();
893 commit.takeOverFrom();
894
895 assert(!tickEvent.scheduled());
896
897 // @todo: Figure out how to properly select the tid to put onto
898 // the active threads list.
899 int tid = 0;
900
901 list<unsigned>::iterator isActive = find(
902 activeThreads.begin(), activeThreads.end(), tid);
903
904 if (isActive == activeThreads.end()) {
905 //May Need to Re-code this if the delay variable is the delay
906 //needed for thread to activate
907 DPRINTF(O3CPU, "Adding Thread %i to active threads list\n",
908 tid);
909
910 activeThreads.push_back(tid);
911 }
912
913 // Set all statuses to active, schedule the CPU's tick event.
914 // @todo: Fix up statuses so this is handled properly
915 for (int i = 0; i < threadContexts.size(); ++i) {
916 ThreadContext *tc = threadContexts[i];
917 if (tc->status() == ThreadContext::Active && _status != Running) {
918 _status = Running;
919 tickEvent.schedule(curTick);
920 }
921 }
922 if (!tickEvent.scheduled())
923 tickEvent.schedule(curTick);
924}
925
926template <class Impl>
927uint64_t
928FullO3CPU<Impl>::readIntReg(int reg_idx)
929{
930 return regFile.readIntReg(reg_idx);
931}
932
933template <class Impl>
934FloatReg
935FullO3CPU<Impl>::readFloatReg(int reg_idx, int width)
936{
937 return regFile.readFloatReg(reg_idx, width);
938}
939
940template <class Impl>
941FloatReg
942FullO3CPU<Impl>::readFloatReg(int reg_idx)
943{
944 return regFile.readFloatReg(reg_idx);
945}
946
947template <class Impl>
948FloatRegBits
949FullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width)
950{
951 return regFile.readFloatRegBits(reg_idx, width);
952}
953
954template <class Impl>
955FloatRegBits
956FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
957{
958 return regFile.readFloatRegBits(reg_idx);
959}
960
961template <class Impl>
962void
963FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
964{
965 regFile.setIntReg(reg_idx, val);
966}
967
968template <class Impl>
969void
970FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width)
971{
972 regFile.setFloatReg(reg_idx, val, width);
973}
974
975template <class Impl>
976void
977FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
978{
979 regFile.setFloatReg(reg_idx, val);
980}
981
982template <class Impl>
983void
984FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width)
985{
986 regFile.setFloatRegBits(reg_idx, val, width);
987}
988
989template <class Impl>
990void
991FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
992{
993 regFile.setFloatRegBits(reg_idx, val);
994}
995
996template <class Impl>
997uint64_t
998FullO3CPU<Impl>::readArchIntReg(int reg_idx, unsigned tid)
999{
1000 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1001
1002 return regFile.readIntReg(phys_reg);
1003}
1004
1005template <class Impl>
1006float
1007FullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, unsigned tid)
1008{
1009 int idx = reg_idx + TheISA::FP_Base_DepTag;
1010 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1011
1012 return regFile.readFloatReg(phys_reg);
1013}
1014
1015template <class Impl>
1016double
1017FullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, unsigned tid)
1018{
1019 int idx = reg_idx + TheISA::FP_Base_DepTag;
1020 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1021
1022 return regFile.readFloatReg(phys_reg, 64);
1023}
1024
1025template <class Impl>
1026uint64_t
1027FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, unsigned tid)
1028{
1029 int idx = reg_idx + TheISA::FP_Base_DepTag;
1030 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1031
1032 return regFile.readFloatRegBits(phys_reg);
1033}
1034
1035template <class Impl>
1036void
1037FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, unsigned tid)
1038{
1039 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1040
1041 regFile.setIntReg(phys_reg, val);
1042}
1043
1044template <class Impl>
1045void
1046FullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, unsigned tid)
1047{
1048 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1049
1050 regFile.setFloatReg(phys_reg, val);
1051}
1052
1053template <class Impl>
1054void
1055FullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, unsigned tid)
1056{
1057 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1058
1059 regFile.setFloatReg(phys_reg, val, 64);
1060}
1061
1062template <class Impl>
1063void
1064FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid)
1065{
1066 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1067
1068 regFile.setFloatRegBits(phys_reg, val);
1069}
1070
1071template <class Impl>
1072uint64_t
1073FullO3CPU<Impl>::readPC(unsigned tid)
1074{
1075 return commit.readPC(tid);
1076}
1077
1078template <class Impl>
1079void
1080FullO3CPU<Impl>::setPC(Addr new_PC,unsigned tid)
1081{
1082 commit.setPC(new_PC, tid);
1083}
1084
1085template <class Impl>
1086uint64_t
1087FullO3CPU<Impl>::readNextPC(unsigned tid)
1088{
1089 return commit.readNextPC(tid);
1090}
1091
1092template <class Impl>
1093void
1094FullO3CPU<Impl>::setNextPC(uint64_t val,unsigned tid)
1095{
1096 commit.setNextPC(val, tid);
1097}
1098
1099#if THE_ISA != ALPHA_ISA
1100template <class Impl>
1101uint64_t
1102FullO3CPU<Impl>::readNextNPC(unsigned tid)
1103{
1104 return commit.readNextNPC(tid);
1105}
1106
1107template <class Impl>
1108void
1109FullO3CPU<Impl>::setNextNNPC(uint64_t val,unsigned tid)
1110{
1111 commit.setNextNPC(val, tid);
1112}
1113#endif
1114
1115template <class Impl>
1116typename FullO3CPU<Impl>::ListIt
1117FullO3CPU<Impl>::addInst(DynInstPtr &inst)
1118{
1119 instList.push_back(inst);
1120
1121 return --(instList.end());
1122}
1123
1124template <class Impl>
1125void
1126FullO3CPU<Impl>::instDone(unsigned tid)
1127{
1128 // Keep an instruction count.
1129 thread[tid]->numInst++;
1130 thread[tid]->numInsts++;
1131 committedInsts[tid]++;
1132 totalCommittedInsts++;
1133
1134 // Check for instruction-count-based events.
1135 comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1136}
1137
1138template <class Impl>
1139void
1140FullO3CPU<Impl>::addToRemoveList(DynInstPtr &inst)
1141{
1142 removeInstsThisCycle = true;
1143
1144 removeList.push(inst->getInstListIt());
1145}
1146
1147template <class Impl>
1148void
1149FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
1150{
1151 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %#x "
1152 "[sn:%lli]\n",
1153 inst->threadNumber, inst->readPC(), inst->seqNum);
1154
1155 removeInstsThisCycle = true;
1156
1157 // Remove the front instruction.
1158 removeList.push(inst->getInstListIt());
1159}
1160
1161template <class Impl>
1162void
1163FullO3CPU<Impl>::removeInstsNotInROB(unsigned tid)
1164{
1165 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1166 " list.\n", tid);
1167
1168 ListIt end_it;
1169
1170 bool rob_empty = false;
1171
1172 if (instList.empty()) {
1173 return;
1174 } else if (rob.isEmpty(/*tid*/)) {
1175 DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1176 end_it = instList.begin();
1177 rob_empty = true;
1178 } else {
1179 end_it = (rob.readTailInst(tid))->getInstListIt();
1180 DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1181 }
1182
1183 removeInstsThisCycle = true;
1184
1185 ListIt inst_it = instList.end();
1186
1187 inst_it--;
1188
1189 // Walk through the instruction list, removing any instructions
1190 // that were inserted after the given instruction iterator, end_it.
1191 while (inst_it != end_it) {
1192 assert(!instList.empty());
1193
1194 squashInstIt(inst_it, tid);
1195
1196 inst_it--;
1197 }
1198
1199 // If the ROB was empty, then we actually need to remove the first
1200 // instruction as well.
1201 if (rob_empty) {
1202 squashInstIt(inst_it, tid);
1203 }
1204}
1205
1206template <class Impl>
1207void
1208FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num,
1209 unsigned tid)
1210{
1211 assert(!instList.empty());
1212
1213 removeInstsThisCycle = true;
1214
1215 ListIt inst_iter = instList.end();
1216
1217 inst_iter--;
1218
1219 DPRINTF(O3CPU, "Deleting instructions from instruction "
1220 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1221 tid, seq_num, (*inst_iter)->seqNum);
1222
1223 while ((*inst_iter)->seqNum > seq_num) {
1224
1225 bool break_loop = (inst_iter == instList.begin());
1226
1227 squashInstIt(inst_iter, tid);
1228
1229 inst_iter--;
1230
1231 if (break_loop)
1232 break;
1233 }
1234}
1235
1236template <class Impl>
1237inline void
1238FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, const unsigned &tid)
1239{
1240 if ((*instIt)->threadNumber == tid) {
1241 DPRINTF(O3CPU, "Squashing instruction, "
1242 "[tid:%i] [sn:%lli] PC %#x\n",
1243 (*instIt)->threadNumber,
1244 (*instIt)->seqNum,
1245 (*instIt)->readPC());
1246
1247 // Mark it as squashed.
1248 (*instIt)->setSquashed();
1249
1250 // @todo: Formulate a consistent method for deleting
1251 // instructions from the instruction list
1252 // Remove the instruction from the list.
1253 removeList.push(instIt);
1254 }
1255}
1256
1257template <class Impl>
1258void
1259FullO3CPU<Impl>::cleanUpRemovedInsts()
1260{
1261 while (!removeList.empty()) {
1262 DPRINTF(O3CPU, "Removing instruction, "
1263 "[tid:%i] [sn:%lli] PC %#x\n",
1264 (*removeList.front())->threadNumber,
1265 (*removeList.front())->seqNum,
1266 (*removeList.front())->readPC());
1267
1268 instList.erase(removeList.front());
1269
1270 removeList.pop();
1271 }
1272
1273 removeInstsThisCycle = false;
1274}
1275/*
1276template <class Impl>
1277void
1278FullO3CPU<Impl>::removeAllInsts()
1279{
1280 instList.clear();
1281}
1282*/
1283template <class Impl>
1284void
1285FullO3CPU<Impl>::dumpInsts()
1286{
1287 int num = 0;
1288
1289 ListIt inst_list_it = instList.begin();
1290
1291 cprintf("Dumping Instruction List\n");
1292
1293 while (inst_list_it != instList.end()) {
1294 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1295 "Squashed:%i\n\n",
1296 num, (*inst_list_it)->readPC(), (*inst_list_it)->threadNumber,
1297 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1298 (*inst_list_it)->isSquashed());
1299 inst_list_it++;
1300 ++num;
1301 }
1302}
1303/*
1304template <class Impl>
1305void
1306FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
1307{
1308 iew.wakeDependents(inst);
1309}
1310*/
1311template <class Impl>
1312void
1313FullO3CPU<Impl>::wakeCPU()
1314{
1315 if (activityRec.active() || tickEvent.scheduled()) {
1316 DPRINTF(Activity, "CPU already running.\n");
1317 return;
1318 }
1319
1320 DPRINTF(Activity, "Waking up CPU\n");
1321
1322 idleCycles += (curTick - 1) - lastRunningCycle;
1323
1324 tickEvent.schedule(curTick);
1325}
1326
1327template <class Impl>
1328int
1329FullO3CPU<Impl>::getFreeTid()
1330{
1331 for (int i=0; i < numThreads; i++) {
1332 if (!tids[i]) {
1333 tids[i] = true;
1334 return i;
1335 }
1336 }
1337
1338 return -1;
1339}
1340
1341template <class Impl>
1342void
1343FullO3CPU<Impl>::doContextSwitch()
1344{
1345 if (contextSwitch) {
1346
1347 //ADD CODE TO DEACTIVE THREAD HERE (???)
1348
1349 for (int tid=0; tid < cpuWaitList.size(); tid++) {
1350 activateWhenReady(tid);
1351 }
1352
1353 if (cpuWaitList.size() == 0)
1354 contextSwitch = true;
1355 }
1356}
1357
1358template <class Impl>
1359void
1360FullO3CPU<Impl>::updateThreadPriority()
1361{
1362 if (activeThreads.size() > 1)
1363 {
1364 //DEFAULT TO ROUND ROBIN SCHEME
1365 //e.g. Move highest priority to end of thread list
1366 list<unsigned>::iterator list_begin = activeThreads.begin();
1367 list<unsigned>::iterator list_end = activeThreads.end();
1368
1369 unsigned high_thread = *list_begin;
1370
1371 activeThreads.erase(list_begin);
1372
1373 activeThreads.push_back(high_thread);
1374 }
1375}
1376
1377// Forward declaration of FullO3CPU.
1378template class FullO3CPU<O3CPUImpl>;
| 581 if (activeThreads.size() == 0)
582 unscheduleTickEvent();
583 _status = Idle;
584}
585
586template <class Impl>
587void
588FullO3CPU<Impl>::haltContext(int tid)
589{
590 //For now, this is the same as deallocate
591 DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
592 deallocateContext(tid, 1);
593}
594
595template <class Impl>
596void
597FullO3CPU<Impl>::insertThread(unsigned tid)
598{
599 DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
600 // Will change now that the PC and thread state is internal to the CPU
601 // and not in the ThreadContext.
602#if FULL_SYSTEM
603 ThreadContext *src_tc = system->threadContexts[tid];
604#else
605 ThreadContext *src_tc = tcBase(tid);
606#endif
607
608 //Bind Int Regs to Rename Map
609 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
610 PhysRegIndex phys_reg = freeList.getIntReg();
611
612 renameMap[tid].setEntry(ireg,phys_reg);
613 scoreboard.setReg(phys_reg);
614 }
615
616 //Bind Float Regs to Rename Map
617 for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
618 PhysRegIndex phys_reg = freeList.getFloatReg();
619
620 renameMap[tid].setEntry(freg,phys_reg);
621 scoreboard.setReg(phys_reg);
622 }
623
624 //Copy Thread Data Into RegFile
625 //this->copyFromTC(tid);
626
627 //Set PC/NPC/NNPC
628 setPC(src_tc->readPC(), tid);
629 setNextPC(src_tc->readNextPC(), tid);
630#if THE_ISA != ALPHA_ISA
631 setNextNPC(src_tc->readNextNPC(), tid);
632#endif
633
634 src_tc->setStatus(ThreadContext::Active);
635
636 activateContext(tid,1);
637
638 //Reset ROB/IQ/LSQ Entries
639 commit.rob->resetEntries();
640 iew.resetEntries();
641}
642
643template <class Impl>
644void
645FullO3CPU<Impl>::removeThread(unsigned tid)
646{
647 DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
648
649 // Copy Thread Data From RegFile
650 // If thread is suspended, it might be re-allocated
651 //this->copyToTC(tid);
652
653 // Unbind Int Regs from Rename Map
654 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
655 PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
656
657 scoreboard.unsetReg(phys_reg);
658 freeList.addReg(phys_reg);
659 }
660
661 // Unbind Float Regs from Rename Map
662 for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
663 PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
664
665 scoreboard.unsetReg(phys_reg);
666 freeList.addReg(phys_reg);
667 }
668
669 // Squash Throughout Pipeline
670 fetch.squash(0,tid);
671 decode.squash(tid);
672 rename.squash(tid);
673 iew.squash(tid);
674 commit.rob->squash(commit.rob->readHeadInst(tid)->seqNum, tid);
675
676 assert(iew.ldstQueue.getCount(tid) == 0);
677
678 // Reset ROB/IQ/LSQ Entries
679 if (activeThreads.size() >= 1) {
680 commit.rob->resetEntries();
681 iew.resetEntries();
682 }
683}
684
685
686template <class Impl>
687void
688FullO3CPU<Impl>::activateWhenReady(int tid)
689{
690 DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming"
691 "(e.g. PhysRegs/ROB/IQ/LSQ) \n",
692 tid);
693
694 bool ready = true;
695
696 if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) {
697 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
698 "Phys. Int. Regs.\n",
699 tid);
700 ready = false;
701 } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) {
702 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
703 "Phys. Float. Regs.\n",
704 tid);
705 ready = false;
706 } else if (commit.rob->numFreeEntries() >=
707 commit.rob->entryAmount(activeThreads.size() + 1)) {
708 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
709 "ROB entries.\n",
710 tid);
711 ready = false;
712 } else if (iew.instQueue.numFreeEntries() >=
713 iew.instQueue.entryAmount(activeThreads.size() + 1)) {
714 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
715 "IQ entries.\n",
716 tid);
717 ready = false;
718 } else if (iew.ldstQueue.numFreeEntries() >=
719 iew.ldstQueue.entryAmount(activeThreads.size() + 1)) {
720 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
721 "LSQ entries.\n",
722 tid);
723 ready = false;
724 }
725
726 if (ready) {
727 insertThread(tid);
728
729 contextSwitch = false;
730
731 cpuWaitList.remove(tid);
732 } else {
733 suspendContext(tid);
734
735 //blocks fetch
736 contextSwitch = true;
737
738 //@todo: dont always add to waitlist
739 //do waitlist
740 cpuWaitList.push_back(tid);
741 }
742}
743
744template <class Impl>
745void
746FullO3CPU<Impl>::serialize(std::ostream &os)
747{
748 SERIALIZE_ENUM(_status);
749 BaseCPU::serialize(os);
750 nameOut(os, csprintf("%s.tickEvent", name()));
751 tickEvent.serialize(os);
752
753 // Use SimpleThread's ability to checkpoint to make it easier to
754 // write out the registers. Also make this static so it doesn't
755 // get instantiated multiple times (causes a panic in statistics).
756 static SimpleThread temp;
757
758 for (int i = 0; i < thread.size(); i++) {
759 nameOut(os, csprintf("%s.xc.%i", name(), i));
760 temp.copyTC(thread[i]->getTC());
761 temp.serialize(os);
762 }
763}
764
765template <class Impl>
766void
767FullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion)
768{
769 UNSERIALIZE_ENUM(_status);
770 BaseCPU::unserialize(cp, section);
771 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
772
773 // Use SimpleThread's ability to checkpoint to make it easier to
774 // read in the registers. Also make this static so it doesn't
775 // get instantiated multiple times (causes a panic in statistics).
776 static SimpleThread temp;
777
778 for (int i = 0; i < thread.size(); i++) {
779 temp.copyTC(thread[i]->getTC());
780 temp.unserialize(cp, csprintf("%s.xc.%i", section, i));
781 thread[i]->getTC()->copyArchRegs(temp.getTC());
782 }
783}
784
785template <class Impl>
786unsigned int
787FullO3CPU<Impl>::drain(Event *drain_event)
788{
789 drainCount = 0;
790 fetch.drain();
791 decode.drain();
792 rename.drain();
793 iew.drain();
794 commit.drain();
795
796 // Wake the CPU and record activity so everything can drain out if
797 // the CPU was not able to immediately drain.
798 if (getState() != SimObject::Drained) {
799 // A bit of a hack...set the drainEvent after all the drain()
800 // calls have been made, that way if all of the stages drain
801 // immediately, the signalDrained() function knows not to call
802 // process on the drain event.
803 drainEvent = drain_event;
804
805 wakeCPU();
806 activityRec.activity();
807
808 return 1;
809 } else {
810 return 0;
811 }
812}
813
814template <class Impl>
815void
816FullO3CPU<Impl>::resume()
817{
818 assert(system->getMemoryMode() == System::Timing);
819 fetch.resume();
820 decode.resume();
821 rename.resume();
822 iew.resume();
823 commit.resume();
824
825 changeState(SimObject::Running);
826
827 if (_status == SwitchedOut || _status == Idle)
828 return;
829
830 if (!tickEvent.scheduled())
831 tickEvent.schedule(curTick);
832 _status = Running;
833}
834
835template <class Impl>
836void
837FullO3CPU<Impl>::signalDrained()
838{
839 if (++drainCount == NumStages) {
840 if (tickEvent.scheduled())
841 tickEvent.squash();
842
843 changeState(SimObject::Drained);
844
845 if (drainEvent) {
846 drainEvent->process();
847 drainEvent = NULL;
848 }
849 }
850 assert(drainCount <= 5);
851}
852
853template <class Impl>
854void
855FullO3CPU<Impl>::switchOut()
856{
857 fetch.switchOut();
858 rename.switchOut();
859 commit.switchOut();
860 instList.clear();
861 while (!removeList.empty()) {
862 removeList.pop();
863 }
864
865 _status = SwitchedOut;
866#if USE_CHECKER
867 if (checker)
868 checker->switchOut();
869#endif
870}
871
872template <class Impl>
873void
874FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
875{
876 // Flush out any old data from the time buffers.
877 for (int i = 0; i < timeBuffer.getSize(); ++i) {
878 timeBuffer.advance();
879 fetchQueue.advance();
880 decodeQueue.advance();
881 renameQueue.advance();
882 iewQueue.advance();
883 }
884
885 activityRec.reset();
886
887 BaseCPU::takeOverFrom(oldCPU);
888
889 fetch.takeOverFrom();
890 decode.takeOverFrom();
891 rename.takeOverFrom();
892 iew.takeOverFrom();
893 commit.takeOverFrom();
894
895 assert(!tickEvent.scheduled());
896
897 // @todo: Figure out how to properly select the tid to put onto
898 // the active threads list.
899 int tid = 0;
900
901 list<unsigned>::iterator isActive = find(
902 activeThreads.begin(), activeThreads.end(), tid);
903
904 if (isActive == activeThreads.end()) {
905 //May Need to Re-code this if the delay variable is the delay
906 //needed for thread to activate
907 DPRINTF(O3CPU, "Adding Thread %i to active threads list\n",
908 tid);
909
910 activeThreads.push_back(tid);
911 }
912
913 // Set all statuses to active, schedule the CPU's tick event.
914 // @todo: Fix up statuses so this is handled properly
915 for (int i = 0; i < threadContexts.size(); ++i) {
916 ThreadContext *tc = threadContexts[i];
917 if (tc->status() == ThreadContext::Active && _status != Running) {
918 _status = Running;
919 tickEvent.schedule(curTick);
920 }
921 }
922 if (!tickEvent.scheduled())
923 tickEvent.schedule(curTick);
924}
925
926template <class Impl>
927uint64_t
928FullO3CPU<Impl>::readIntReg(int reg_idx)
929{
930 return regFile.readIntReg(reg_idx);
931}
932
933template <class Impl>
934FloatReg
935FullO3CPU<Impl>::readFloatReg(int reg_idx, int width)
936{
937 return regFile.readFloatReg(reg_idx, width);
938}
939
940template <class Impl>
941FloatReg
942FullO3CPU<Impl>::readFloatReg(int reg_idx)
943{
944 return regFile.readFloatReg(reg_idx);
945}
946
947template <class Impl>
948FloatRegBits
949FullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width)
950{
951 return regFile.readFloatRegBits(reg_idx, width);
952}
953
954template <class Impl>
955FloatRegBits
956FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
957{
958 return regFile.readFloatRegBits(reg_idx);
959}
960
961template <class Impl>
962void
963FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
964{
965 regFile.setIntReg(reg_idx, val);
966}
967
968template <class Impl>
969void
970FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width)
971{
972 regFile.setFloatReg(reg_idx, val, width);
973}
974
975template <class Impl>
976void
977FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
978{
979 regFile.setFloatReg(reg_idx, val);
980}
981
982template <class Impl>
983void
984FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width)
985{
986 regFile.setFloatRegBits(reg_idx, val, width);
987}
988
989template <class Impl>
990void
991FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
992{
993 regFile.setFloatRegBits(reg_idx, val);
994}
995
996template <class Impl>
997uint64_t
998FullO3CPU<Impl>::readArchIntReg(int reg_idx, unsigned tid)
999{
1000 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1001
1002 return regFile.readIntReg(phys_reg);
1003}
1004
1005template <class Impl>
1006float
1007FullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, unsigned tid)
1008{
1009 int idx = reg_idx + TheISA::FP_Base_DepTag;
1010 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1011
1012 return regFile.readFloatReg(phys_reg);
1013}
1014
1015template <class Impl>
1016double
1017FullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, unsigned tid)
1018{
1019 int idx = reg_idx + TheISA::FP_Base_DepTag;
1020 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1021
1022 return regFile.readFloatReg(phys_reg, 64);
1023}
1024
1025template <class Impl>
1026uint64_t
1027FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, unsigned tid)
1028{
1029 int idx = reg_idx + TheISA::FP_Base_DepTag;
1030 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1031
1032 return regFile.readFloatRegBits(phys_reg);
1033}
1034
1035template <class Impl>
1036void
1037FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, unsigned tid)
1038{
1039 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1040
1041 regFile.setIntReg(phys_reg, val);
1042}
1043
1044template <class Impl>
1045void
1046FullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, unsigned tid)
1047{
1048 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1049
1050 regFile.setFloatReg(phys_reg, val);
1051}
1052
1053template <class Impl>
1054void
1055FullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, unsigned tid)
1056{
1057 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1058
1059 regFile.setFloatReg(phys_reg, val, 64);
1060}
1061
1062template <class Impl>
1063void
1064FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid)
1065{
1066 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1067
1068 regFile.setFloatRegBits(phys_reg, val);
1069}
1070
1071template <class Impl>
1072uint64_t
1073FullO3CPU<Impl>::readPC(unsigned tid)
1074{
1075 return commit.readPC(tid);
1076}
1077
1078template <class Impl>
1079void
1080FullO3CPU<Impl>::setPC(Addr new_PC,unsigned tid)
1081{
1082 commit.setPC(new_PC, tid);
1083}
1084
1085template <class Impl>
1086uint64_t
1087FullO3CPU<Impl>::readNextPC(unsigned tid)
1088{
1089 return commit.readNextPC(tid);
1090}
1091
1092template <class Impl>
1093void
1094FullO3CPU<Impl>::setNextPC(uint64_t val,unsigned tid)
1095{
1096 commit.setNextPC(val, tid);
1097}
1098
1099#if THE_ISA != ALPHA_ISA
1100template <class Impl>
1101uint64_t
1102FullO3CPU<Impl>::readNextNPC(unsigned tid)
1103{
1104 return commit.readNextNPC(tid);
1105}
1106
1107template <class Impl>
1108void
1109FullO3CPU<Impl>::setNextNNPC(uint64_t val,unsigned tid)
1110{
1111 commit.setNextNPC(val, tid);
1112}
1113#endif
1114
1115template <class Impl>
1116typename FullO3CPU<Impl>::ListIt
1117FullO3CPU<Impl>::addInst(DynInstPtr &inst)
1118{
1119 instList.push_back(inst);
1120
1121 return --(instList.end());
1122}
1123
1124template <class Impl>
1125void
1126FullO3CPU<Impl>::instDone(unsigned tid)
1127{
1128 // Keep an instruction count.
1129 thread[tid]->numInst++;
1130 thread[tid]->numInsts++;
1131 committedInsts[tid]++;
1132 totalCommittedInsts++;
1133
1134 // Check for instruction-count-based events.
1135 comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1136}
1137
1138template <class Impl>
1139void
1140FullO3CPU<Impl>::addToRemoveList(DynInstPtr &inst)
1141{
1142 removeInstsThisCycle = true;
1143
1144 removeList.push(inst->getInstListIt());
1145}
1146
1147template <class Impl>
1148void
1149FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
1150{
1151 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %#x "
1152 "[sn:%lli]\n",
1153 inst->threadNumber, inst->readPC(), inst->seqNum);
1154
1155 removeInstsThisCycle = true;
1156
1157 // Remove the front instruction.
1158 removeList.push(inst->getInstListIt());
1159}
1160
1161template <class Impl>
1162void
1163FullO3CPU<Impl>::removeInstsNotInROB(unsigned tid)
1164{
1165 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1166 " list.\n", tid);
1167
1168 ListIt end_it;
1169
1170 bool rob_empty = false;
1171
1172 if (instList.empty()) {
1173 return;
1174 } else if (rob.isEmpty(/*tid*/)) {
1175 DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1176 end_it = instList.begin();
1177 rob_empty = true;
1178 } else {
1179 end_it = (rob.readTailInst(tid))->getInstListIt();
1180 DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1181 }
1182
1183 removeInstsThisCycle = true;
1184
1185 ListIt inst_it = instList.end();
1186
1187 inst_it--;
1188
1189 // Walk through the instruction list, removing any instructions
1190 // that were inserted after the given instruction iterator, end_it.
1191 while (inst_it != end_it) {
1192 assert(!instList.empty());
1193
1194 squashInstIt(inst_it, tid);
1195
1196 inst_it--;
1197 }
1198
1199 // If the ROB was empty, then we actually need to remove the first
1200 // instruction as well.
1201 if (rob_empty) {
1202 squashInstIt(inst_it, tid);
1203 }
1204}
1205
1206template <class Impl>
1207void
1208FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num,
1209 unsigned tid)
1210{
1211 assert(!instList.empty());
1212
1213 removeInstsThisCycle = true;
1214
1215 ListIt inst_iter = instList.end();
1216
1217 inst_iter--;
1218
1219 DPRINTF(O3CPU, "Deleting instructions from instruction "
1220 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1221 tid, seq_num, (*inst_iter)->seqNum);
1222
1223 while ((*inst_iter)->seqNum > seq_num) {
1224
1225 bool break_loop = (inst_iter == instList.begin());
1226
1227 squashInstIt(inst_iter, tid);
1228
1229 inst_iter--;
1230
1231 if (break_loop)
1232 break;
1233 }
1234}
1235
1236template <class Impl>
1237inline void
1238FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, const unsigned &tid)
1239{
1240 if ((*instIt)->threadNumber == tid) {
1241 DPRINTF(O3CPU, "Squashing instruction, "
1242 "[tid:%i] [sn:%lli] PC %#x\n",
1243 (*instIt)->threadNumber,
1244 (*instIt)->seqNum,
1245 (*instIt)->readPC());
1246
1247 // Mark it as squashed.
1248 (*instIt)->setSquashed();
1249
1250 // @todo: Formulate a consistent method for deleting
1251 // instructions from the instruction list
1252 // Remove the instruction from the list.
1253 removeList.push(instIt);
1254 }
1255}
1256
1257template <class Impl>
1258void
1259FullO3CPU<Impl>::cleanUpRemovedInsts()
1260{
1261 while (!removeList.empty()) {
1262 DPRINTF(O3CPU, "Removing instruction, "
1263 "[tid:%i] [sn:%lli] PC %#x\n",
1264 (*removeList.front())->threadNumber,
1265 (*removeList.front())->seqNum,
1266 (*removeList.front())->readPC());
1267
1268 instList.erase(removeList.front());
1269
1270 removeList.pop();
1271 }
1272
1273 removeInstsThisCycle = false;
1274}
1275/*
1276template <class Impl>
1277void
1278FullO3CPU<Impl>::removeAllInsts()
1279{
1280 instList.clear();
1281}
1282*/
1283template <class Impl>
1284void
1285FullO3CPU<Impl>::dumpInsts()
1286{
1287 int num = 0;
1288
1289 ListIt inst_list_it = instList.begin();
1290
1291 cprintf("Dumping Instruction List\n");
1292
1293 while (inst_list_it != instList.end()) {
1294 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1295 "Squashed:%i\n\n",
1296 num, (*inst_list_it)->readPC(), (*inst_list_it)->threadNumber,
1297 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1298 (*inst_list_it)->isSquashed());
1299 inst_list_it++;
1300 ++num;
1301 }
1302}
1303/*
1304template <class Impl>
1305void
1306FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
1307{
1308 iew.wakeDependents(inst);
1309}
1310*/
1311template <class Impl>
1312void
1313FullO3CPU<Impl>::wakeCPU()
1314{
1315 if (activityRec.active() || tickEvent.scheduled()) {
1316 DPRINTF(Activity, "CPU already running.\n");
1317 return;
1318 }
1319
1320 DPRINTF(Activity, "Waking up CPU\n");
1321
1322 idleCycles += (curTick - 1) - lastRunningCycle;
1323
1324 tickEvent.schedule(curTick);
1325}
1326
1327template <class Impl>
1328int
1329FullO3CPU<Impl>::getFreeTid()
1330{
1331 for (int i=0; i < numThreads; i++) {
1332 if (!tids[i]) {
1333 tids[i] = true;
1334 return i;
1335 }
1336 }
1337
1338 return -1;
1339}
1340
1341template <class Impl>
1342void
1343FullO3CPU<Impl>::doContextSwitch()
1344{
1345 if (contextSwitch) {
1346
1347 //ADD CODE TO DEACTIVE THREAD HERE (???)
1348
1349 for (int tid=0; tid < cpuWaitList.size(); tid++) {
1350 activateWhenReady(tid);
1351 }
1352
1353 if (cpuWaitList.size() == 0)
1354 contextSwitch = true;
1355 }
1356}
1357
1358template <class Impl>
1359void
1360FullO3CPU<Impl>::updateThreadPriority()
1361{
1362 if (activeThreads.size() > 1)
1363 {
1364 //DEFAULT TO ROUND ROBIN SCHEME
1365 //e.g. Move highest priority to end of thread list
1366 list<unsigned>::iterator list_begin = activeThreads.begin();
1367 list<unsigned>::iterator list_end = activeThreads.end();
1368
1369 unsigned high_thread = *list_begin;
1370
1371 activeThreads.erase(list_begin);
1372
1373 activeThreads.push_back(high_thread);
1374 }
1375}
1376
1377// Forward declaration of FullO3CPU.
1378template class FullO3CPU<O3CPUImpl>;
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