1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#include "config/full_system.hh"
33#include "config/use_checker.hh"
34
35#if FULL_SYSTEM
36#include "sim/system.hh"
37#else
38#include "sim/process.hh"
39#endif
40
41#include "cpu/activity.hh"
42#include "cpu/simple_thread.hh"
43#include "cpu/thread_context.hh"
44#include "cpu/o3/isa_specific.hh"
45#include "cpu/o3/cpu.hh"
46
47#include "sim/root.hh"
48#include "sim/stat_control.hh"
49
50#if USE_CHECKER
51#include "cpu/checker/cpu.hh"
52#endif
53
54using namespace std;
55using namespace TheISA;
56
57BaseO3CPU::BaseO3CPU(Params *params)
58 : BaseCPU(params), cpu_id(0)
59{
60}
61
62void
63BaseO3CPU::regStats()
64{
65 BaseCPU::regStats();
66}
67
68template <class Impl>
69FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
70 : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
71{
72}
73
74template <class Impl>
75void
76FullO3CPU<Impl>::TickEvent::process()
77{
78 cpu->tick();
79}
80
81template <class Impl>
82const char *
83FullO3CPU<Impl>::TickEvent::description()
84{
85 return "FullO3CPU tick event";
86}
87
88template <class Impl>
| 1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#include "config/full_system.hh"
33#include "config/use_checker.hh"
34
35#if FULL_SYSTEM
36#include "sim/system.hh"
37#else
38#include "sim/process.hh"
39#endif
40
41#include "cpu/activity.hh"
42#include "cpu/simple_thread.hh"
43#include "cpu/thread_context.hh"
44#include "cpu/o3/isa_specific.hh"
45#include "cpu/o3/cpu.hh"
46
47#include "sim/root.hh"
48#include "sim/stat_control.hh"
49
50#if USE_CHECKER
51#include "cpu/checker/cpu.hh"
52#endif
53
54using namespace std;
55using namespace TheISA;
56
57BaseO3CPU::BaseO3CPU(Params *params)
58 : BaseCPU(params), cpu_id(0)
59{
60}
61
62void
63BaseO3CPU::regStats()
64{
65 BaseCPU::regStats();
66}
67
68template <class Impl>
69FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
70 : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
71{
72}
73
74template <class Impl>
75void
76FullO3CPU<Impl>::TickEvent::process()
77{
78 cpu->tick();
79}
80
81template <class Impl>
82const char *
83FullO3CPU<Impl>::TickEvent::description()
84{
85 return "FullO3CPU tick event";
86}
87
88template <class Impl>
|
| 89FullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent()
90 : Event(&mainEventQueue, CPU_Tick_Pri)
91{
92}
93
94template <class Impl>
95void
96FullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num,
97 FullO3CPU<Impl> *thread_cpu)
98{
99 tid = thread_num;
100 cpu = thread_cpu;
101}
102
103template <class Impl>
104void
105FullO3CPU<Impl>::ActivateThreadEvent::process()
106{
107 cpu->activateThread(tid);
108}
109
110template <class Impl>
111const char *
112FullO3CPU<Impl>::ActivateThreadEvent::description()
113{
114 return "FullO3CPU \"Activate Thread\" event";
115}
116
117template <class Impl>
|
89FullO3CPU<Impl>::FullO3CPU(Params *params)
90 : BaseO3CPU(params),
91 tickEvent(this),
92 removeInstsThisCycle(false),
93 fetch(params),
94 decode(params),
95 rename(params),
96 iew(params),
97 commit(params),
98
99 regFile(params->numPhysIntRegs, params->numPhysFloatRegs),
100
101 freeList(params->numberOfThreads,//number of activeThreads
102 TheISA::NumIntRegs, params->numPhysIntRegs,
103 TheISA::NumFloatRegs, params->numPhysFloatRegs),
104
105 rob(params->numROBEntries, params->squashWidth,
106 params->smtROBPolicy, params->smtROBThreshold,
107 params->numberOfThreads),
108
109 scoreboard(params->numberOfThreads,//number of activeThreads
110 TheISA::NumIntRegs, params->numPhysIntRegs,
111 TheISA::NumFloatRegs, params->numPhysFloatRegs,
112 TheISA::NumMiscRegs * number_of_threads,
113 TheISA::ZeroReg),
114
115 // For now just have these time buffers be pretty big.
116 // @todo: Make these time buffer sizes parameters or derived
117 // from latencies
118 timeBuffer(5, 5),
119 fetchQueue(5, 5),
120 decodeQueue(5, 5),
121 renameQueue(5, 5),
122 iewQueue(5, 5),
123 activityRec(NumStages, 10, params->activity),
124
125 globalSeqNum(1),
126
127#if FULL_SYSTEM
128 system(params->system),
129 physmem(system->physmem),
130#endif // FULL_SYSTEM
131 mem(params->mem),
132 switchCount(0),
133 deferRegistration(params->deferRegistration),
134 numThreads(number_of_threads)
135{
136 _status = Idle;
137
138 checker = NULL;
139
140 if (params->checker) {
141#if USE_CHECKER
142 BaseCPU *temp_checker = params->checker;
143 checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
144 checker->setMemory(mem);
145#if FULL_SYSTEM
146 checker->setSystem(params->system);
147#endif
148#else
149 panic("Checker enabled but not compiled in!");
150#endif // USE_CHECKER
151 }
152
153#if !FULL_SYSTEM
154 thread.resize(number_of_threads);
155 tids.resize(number_of_threads);
156#endif
157
158 // The stages also need their CPU pointer setup. However this
159 // must be done at the upper level CPU because they have pointers
160 // to the upper level CPU, and not this FullO3CPU.
161
162 // Set up Pointers to the activeThreads list for each stage
163 fetch.setActiveThreads(&activeThreads);
164 decode.setActiveThreads(&activeThreads);
165 rename.setActiveThreads(&activeThreads);
166 iew.setActiveThreads(&activeThreads);
167 commit.setActiveThreads(&activeThreads);
168
169 // Give each of the stages the time buffer they will use.
170 fetch.setTimeBuffer(&timeBuffer);
171 decode.setTimeBuffer(&timeBuffer);
172 rename.setTimeBuffer(&timeBuffer);
173 iew.setTimeBuffer(&timeBuffer);
174 commit.setTimeBuffer(&timeBuffer);
175
176 // Also setup each of the stages' queues.
177 fetch.setFetchQueue(&fetchQueue);
178 decode.setFetchQueue(&fetchQueue);
179 commit.setFetchQueue(&fetchQueue);
180 decode.setDecodeQueue(&decodeQueue);
181 rename.setDecodeQueue(&decodeQueue);
182 rename.setRenameQueue(&renameQueue);
183 iew.setRenameQueue(&renameQueue);
184 iew.setIEWQueue(&iewQueue);
185 commit.setIEWQueue(&iewQueue);
186 commit.setRenameQueue(&renameQueue);
187
188 commit.setFetchStage(&fetch);
189 commit.setIEWStage(&iew);
190 rename.setIEWStage(&iew);
191 rename.setCommitStage(&commit);
192
193#if !FULL_SYSTEM
194 int active_threads = params->workload.size();
195#else
196 int active_threads = 1;
197#endif
198
199 //Make Sure That this a Valid Architeture
200 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs);
201 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
202
203 rename.setScoreboard(&scoreboard);
204 iew.setScoreboard(&scoreboard);
205
206 // Setup the rename map for whichever stages need it.
207 PhysRegIndex lreg_idx = 0;
208 PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs
209
210 for (int tid=0; tid < numThreads; tid++) {
211 bool bindRegs = (tid <= active_threads - 1);
212
213 commitRenameMap[tid].init(TheISA::NumIntRegs,
214 params->numPhysIntRegs,
215 lreg_idx, //Index for Logical. Regs
216
217 TheISA::NumFloatRegs,
218 params->numPhysFloatRegs,
219 freg_idx, //Index for Float Regs
220
221 TheISA::NumMiscRegs,
222
223 TheISA::ZeroReg,
224 TheISA::ZeroReg,
225
226 tid,
227 false);
228
229 renameMap[tid].init(TheISA::NumIntRegs,
230 params->numPhysIntRegs,
231 lreg_idx, //Index for Logical. Regs
232
233 TheISA::NumFloatRegs,
234 params->numPhysFloatRegs,
235 freg_idx, //Index for Float Regs
236
237 TheISA::NumMiscRegs,
238
239 TheISA::ZeroReg,
240 TheISA::ZeroReg,
241
242 tid,
243 bindRegs);
244 }
245
246 rename.setRenameMap(renameMap);
247 commit.setRenameMap(commitRenameMap);
248
249 // Give renameMap & rename stage access to the freeList;
250 for (int i=0; i < numThreads; i++) {
251 renameMap[i].setFreeList(&freeList);
252 }
253 rename.setFreeList(&freeList);
254
255 // Setup the ROB for whichever stages need it.
256 commit.setROB(&rob);
257
258 lastRunningCycle = curTick;
259
| 118FullO3CPU<Impl>::FullO3CPU(Params *params)
119 : BaseO3CPU(params),
120 tickEvent(this),
121 removeInstsThisCycle(false),
122 fetch(params),
123 decode(params),
124 rename(params),
125 iew(params),
126 commit(params),
127
128 regFile(params->numPhysIntRegs, params->numPhysFloatRegs),
129
130 freeList(params->numberOfThreads,//number of activeThreads
131 TheISA::NumIntRegs, params->numPhysIntRegs,
132 TheISA::NumFloatRegs, params->numPhysFloatRegs),
133
134 rob(params->numROBEntries, params->squashWidth,
135 params->smtROBPolicy, params->smtROBThreshold,
136 params->numberOfThreads),
137
138 scoreboard(params->numberOfThreads,//number of activeThreads
139 TheISA::NumIntRegs, params->numPhysIntRegs,
140 TheISA::NumFloatRegs, params->numPhysFloatRegs,
141 TheISA::NumMiscRegs * number_of_threads,
142 TheISA::ZeroReg),
143
144 // For now just have these time buffers be pretty big.
145 // @todo: Make these time buffer sizes parameters or derived
146 // from latencies
147 timeBuffer(5, 5),
148 fetchQueue(5, 5),
149 decodeQueue(5, 5),
150 renameQueue(5, 5),
151 iewQueue(5, 5),
152 activityRec(NumStages, 10, params->activity),
153
154 globalSeqNum(1),
155
156#if FULL_SYSTEM
157 system(params->system),
158 physmem(system->physmem),
159#endif // FULL_SYSTEM
160 mem(params->mem),
161 switchCount(0),
162 deferRegistration(params->deferRegistration),
163 numThreads(number_of_threads)
164{
165 _status = Idle;
166
167 checker = NULL;
168
169 if (params->checker) {
170#if USE_CHECKER
171 BaseCPU *temp_checker = params->checker;
172 checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
173 checker->setMemory(mem);
174#if FULL_SYSTEM
175 checker->setSystem(params->system);
176#endif
177#else
178 panic("Checker enabled but not compiled in!");
179#endif // USE_CHECKER
180 }
181
182#if !FULL_SYSTEM
183 thread.resize(number_of_threads);
184 tids.resize(number_of_threads);
185#endif
186
187 // The stages also need their CPU pointer setup. However this
188 // must be done at the upper level CPU because they have pointers
189 // to the upper level CPU, and not this FullO3CPU.
190
191 // Set up Pointers to the activeThreads list for each stage
192 fetch.setActiveThreads(&activeThreads);
193 decode.setActiveThreads(&activeThreads);
194 rename.setActiveThreads(&activeThreads);
195 iew.setActiveThreads(&activeThreads);
196 commit.setActiveThreads(&activeThreads);
197
198 // Give each of the stages the time buffer they will use.
199 fetch.setTimeBuffer(&timeBuffer);
200 decode.setTimeBuffer(&timeBuffer);
201 rename.setTimeBuffer(&timeBuffer);
202 iew.setTimeBuffer(&timeBuffer);
203 commit.setTimeBuffer(&timeBuffer);
204
205 // Also setup each of the stages' queues.
206 fetch.setFetchQueue(&fetchQueue);
207 decode.setFetchQueue(&fetchQueue);
208 commit.setFetchQueue(&fetchQueue);
209 decode.setDecodeQueue(&decodeQueue);
210 rename.setDecodeQueue(&decodeQueue);
211 rename.setRenameQueue(&renameQueue);
212 iew.setRenameQueue(&renameQueue);
213 iew.setIEWQueue(&iewQueue);
214 commit.setIEWQueue(&iewQueue);
215 commit.setRenameQueue(&renameQueue);
216
217 commit.setFetchStage(&fetch);
218 commit.setIEWStage(&iew);
219 rename.setIEWStage(&iew);
220 rename.setCommitStage(&commit);
221
222#if !FULL_SYSTEM
223 int active_threads = params->workload.size();
224#else
225 int active_threads = 1;
226#endif
227
228 //Make Sure That this a Valid Architeture
229 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs);
230 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
231
232 rename.setScoreboard(&scoreboard);
233 iew.setScoreboard(&scoreboard);
234
235 // Setup the rename map for whichever stages need it.
236 PhysRegIndex lreg_idx = 0;
237 PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs
238
239 for (int tid=0; tid < numThreads; tid++) {
240 bool bindRegs = (tid <= active_threads - 1);
241
242 commitRenameMap[tid].init(TheISA::NumIntRegs,
243 params->numPhysIntRegs,
244 lreg_idx, //Index for Logical. Regs
245
246 TheISA::NumFloatRegs,
247 params->numPhysFloatRegs,
248 freg_idx, //Index for Float Regs
249
250 TheISA::NumMiscRegs,
251
252 TheISA::ZeroReg,
253 TheISA::ZeroReg,
254
255 tid,
256 false);
257
258 renameMap[tid].init(TheISA::NumIntRegs,
259 params->numPhysIntRegs,
260 lreg_idx, //Index for Logical. Regs
261
262 TheISA::NumFloatRegs,
263 params->numPhysFloatRegs,
264 freg_idx, //Index for Float Regs
265
266 TheISA::NumMiscRegs,
267
268 TheISA::ZeroReg,
269 TheISA::ZeroReg,
270
271 tid,
272 bindRegs);
273 }
274
275 rename.setRenameMap(renameMap);
276 commit.setRenameMap(commitRenameMap);
277
278 // Give renameMap & rename stage access to the freeList;
279 for (int i=0; i < numThreads; i++) {
280 renameMap[i].setFreeList(&freeList);
281 }
282 rename.setFreeList(&freeList);
283
284 // Setup the ROB for whichever stages need it.
285 commit.setROB(&rob);
286
287 lastRunningCycle = curTick;
288
|
| 289 lastActivatedCycle = -1;
290
|
260 contextSwitch = false;
261}
262
263template <class Impl>
264FullO3CPU<Impl>::~FullO3CPU()
265{
266}
267
268template <class Impl>
269void
270FullO3CPU<Impl>::fullCPURegStats()
271{
272 BaseO3CPU::regStats();
273
274 // Register any of the O3CPU's stats here.
275 timesIdled
276 .name(name() + ".timesIdled")
277 .desc("Number of times that the entire CPU went into an idle state and"
278 " unscheduled itself")
279 .prereq(timesIdled);
280
281 idleCycles
282 .name(name() + ".idleCycles")
283 .desc("Total number of cycles that the CPU has spent unscheduled due "
284 "to idling")
285 .prereq(idleCycles);
286
287 // Number of Instructions simulated
288 // --------------------------------
289 // Should probably be in Base CPU but need templated
290 // MaxThreads so put in here instead
291 committedInsts
292 .init(numThreads)
293 .name(name() + ".committedInsts")
294 .desc("Number of Instructions Simulated");
295
296 totalCommittedInsts
297 .name(name() + ".committedInsts_total")
298 .desc("Number of Instructions Simulated");
299
300 cpi
301 .name(name() + ".cpi")
302 .desc("CPI: Cycles Per Instruction")
303 .precision(6);
304 cpi = simTicks / committedInsts;
305
306 totalCpi
307 .name(name() + ".cpi_total")
308 .desc("CPI: Total CPI of All Threads")
309 .precision(6);
310 totalCpi = simTicks / totalCommittedInsts;
311
312 ipc
313 .name(name() + ".ipc")
314 .desc("IPC: Instructions Per Cycle")
315 .precision(6);
316 ipc = committedInsts / simTicks;
317
318 totalIpc
319 .name(name() + ".ipc_total")
320 .desc("IPC: Total IPC of All Threads")
321 .precision(6);
322 totalIpc = totalCommittedInsts / simTicks;
323
324}
325
326template <class Impl>
327void
328FullO3CPU<Impl>::tick()
329{
330 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
331
332 ++numCycles;
333
334// activity = false;
335
336 //Tick each of the stages
337 fetch.tick();
338
339 decode.tick();
340
341 rename.tick();
342
343 iew.tick();
344
345 commit.tick();
346
347#if !FULL_SYSTEM
348 doContextSwitch();
349#endif
350
351 // Now advance the time buffers
352 timeBuffer.advance();
353
354 fetchQueue.advance();
355 decodeQueue.advance();
356 renameQueue.advance();
357 iewQueue.advance();
358
359 activityRec.advance();
360
361 if (removeInstsThisCycle) {
362 cleanUpRemovedInsts();
363 }
364
365 if (!tickEvent.scheduled()) {
366 if (_status == SwitchedOut) {
367 // increment stat
368 lastRunningCycle = curTick;
369 } else if (!activityRec.active()) {
370 lastRunningCycle = curTick;
371 timesIdled++;
372 } else {
373 tickEvent.schedule(curTick + cycles(1));
374 }
375 }
376
377#if !FULL_SYSTEM
378 updateThreadPriority();
379#endif
380
381}
382
383template <class Impl>
384void
385FullO3CPU<Impl>::init()
386{
387 if (!deferRegistration) {
388 registerThreadContexts();
389 }
390
391 // Set inSyscall so that the CPU doesn't squash when initially
392 // setting up registers.
393 for (int i = 0; i < number_of_threads; ++i)
394 thread[i]->inSyscall = true;
395
396 for (int tid=0; tid < number_of_threads; tid++) {
397#if FULL_SYSTEM
398 ThreadContext *src_tc = threadContexts[tid];
399#else
400 ThreadContext *src_tc = thread[tid]->getTC();
401#endif
402 // Threads start in the Suspended State
403 if (src_tc->status() != ThreadContext::Suspended) {
404 continue;
405 }
406
407#if FULL_SYSTEM
408 TheISA::initCPU(src_tc, src_tc->readCpuId());
409#endif
410 }
411
412 // Clear inSyscall.
413 for (int i = 0; i < number_of_threads; ++i)
414 thread[i]->inSyscall = false;
415
416 // Initialize stages.
417 fetch.initStage();
418 iew.initStage();
419 rename.initStage();
420 commit.initStage();
421
422 commit.setThreads(thread);
423}
424
425template <class Impl>
426void
427FullO3CPU<Impl>::insertThread(unsigned tid)
428{
429 DPRINTF(O3CPU,"[tid:%i] Initializing thread data");
430 // Will change now that the PC and thread state is internal to the CPU
431 // and not in the ThreadContext.
432#if 0
433#if FULL_SYSTEM
434 ThreadContext *src_tc = system->threadContexts[tid];
435#else
436 ThreadContext *src_tc = thread[tid];
437#endif
438
439 //Bind Int Regs to Rename Map
440 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
441 PhysRegIndex phys_reg = freeList.getIntReg();
442
443 renameMap[tid].setEntry(ireg,phys_reg);
444 scoreboard.setReg(phys_reg);
445 }
446
447 //Bind Float Regs to Rename Map
448 for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
449 PhysRegIndex phys_reg = freeList.getFloatReg();
450
451 renameMap[tid].setEntry(freg,phys_reg);
452 scoreboard.setReg(phys_reg);
453 }
454
455 //Copy Thread Data Into RegFile
456 this->copyFromTC(tid);
457
458 //Set PC/NPC
459 regFile.pc[tid] = src_tc->readPC();
460 regFile.npc[tid] = src_tc->readNextPC();
461
462 src_tc->setStatus(ThreadContext::Active);
463
464 activateContext(tid,1);
465
466 //Reset ROB/IQ/LSQ Entries
467 commit.rob->resetEntries();
468 iew.resetEntries();
469#endif
470}
471
472template <class Impl>
473void
474FullO3CPU<Impl>::removeThread(unsigned tid)
475{
476 DPRINTF(O3CPU,"[tid:%i] Removing thread data");
477#if 0
478 //Unbind Int Regs from Rename Map
479 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
480 PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
481
482 scoreboard.unsetReg(phys_reg);
483 freeList.addReg(phys_reg);
484 }
485
486 //Unbind Float Regs from Rename Map
487 for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
488 PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
489
490 scoreboard.unsetReg(phys_reg);
491 freeList.addReg(phys_reg);
492 }
493
494 //Copy Thread Data From RegFile
495 /* Fix Me:
496 * Do we really need to do this if we are removing a thread
497 * in the sense that it's finished (exiting)? If the thread is just
498 * being suspended we might...
499 */
500// this->copyToTC(tid);
501
502 //Squash Throughout Pipeline
503 fetch.squash(0,tid);
504 decode.squash(tid);
505 rename.squash(tid);
506
507 assert(iew.ldstQueue.getCount(tid) == 0);
508
509 //Reset ROB/IQ/LSQ Entries
510 if (activeThreads.size() >= 1) {
511 commit.rob->resetEntries();
512 iew.resetEntries();
513 }
514#endif
515}
516
517
518template <class Impl>
519void
520FullO3CPU<Impl>::activateWhenReady(int tid)
521{
522 DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming"
523 "(e.g. PhysRegs/ROB/IQ/LSQ) \n",
524 tid);
525
526 bool ready = true;
527
528 if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) {
529 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
530 "Phys. Int. Regs.\n",
531 tid);
532 ready = false;
533 } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) {
534 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
535 "Phys. Float. Regs.\n",
536 tid);
537 ready = false;
538 } else if (commit.rob->numFreeEntries() >=
539 commit.rob->entryAmount(activeThreads.size() + 1)) {
540 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
541 "ROB entries.\n",
542 tid);
543 ready = false;
544 } else if (iew.instQueue.numFreeEntries() >=
545 iew.instQueue.entryAmount(activeThreads.size() + 1)) {
546 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
547 "IQ entries.\n",
548 tid);
549 ready = false;
550 } else if (iew.ldstQueue.numFreeEntries() >=
551 iew.ldstQueue.entryAmount(activeThreads.size() + 1)) {
552 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
553 "LSQ entries.\n",
554 tid);
555 ready = false;
556 }
557
558 if (ready) {
559 insertThread(tid);
560
561 contextSwitch = false;
562
563 cpuWaitList.remove(tid);
564 } else {
565 suspendContext(tid);
566
567 //blocks fetch
568 contextSwitch = true;
569
570 //do waitlist
571 cpuWaitList.push_back(tid);
572 }
573}
574
575template <class Impl>
576void
| 291 contextSwitch = false;
292}
293
294template <class Impl>
295FullO3CPU<Impl>::~FullO3CPU()
296{
297}
298
299template <class Impl>
300void
301FullO3CPU<Impl>::fullCPURegStats()
302{
303 BaseO3CPU::regStats();
304
305 // Register any of the O3CPU's stats here.
306 timesIdled
307 .name(name() + ".timesIdled")
308 .desc("Number of times that the entire CPU went into an idle state and"
309 " unscheduled itself")
310 .prereq(timesIdled);
311
312 idleCycles
313 .name(name() + ".idleCycles")
314 .desc("Total number of cycles that the CPU has spent unscheduled due "
315 "to idling")
316 .prereq(idleCycles);
317
318 // Number of Instructions simulated
319 // --------------------------------
320 // Should probably be in Base CPU but need templated
321 // MaxThreads so put in here instead
322 committedInsts
323 .init(numThreads)
324 .name(name() + ".committedInsts")
325 .desc("Number of Instructions Simulated");
326
327 totalCommittedInsts
328 .name(name() + ".committedInsts_total")
329 .desc("Number of Instructions Simulated");
330
331 cpi
332 .name(name() + ".cpi")
333 .desc("CPI: Cycles Per Instruction")
334 .precision(6);
335 cpi = simTicks / committedInsts;
336
337 totalCpi
338 .name(name() + ".cpi_total")
339 .desc("CPI: Total CPI of All Threads")
340 .precision(6);
341 totalCpi = simTicks / totalCommittedInsts;
342
343 ipc
344 .name(name() + ".ipc")
345 .desc("IPC: Instructions Per Cycle")
346 .precision(6);
347 ipc = committedInsts / simTicks;
348
349 totalIpc
350 .name(name() + ".ipc_total")
351 .desc("IPC: Total IPC of All Threads")
352 .precision(6);
353 totalIpc = totalCommittedInsts / simTicks;
354
355}
356
357template <class Impl>
358void
359FullO3CPU<Impl>::tick()
360{
361 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
362
363 ++numCycles;
364
365// activity = false;
366
367 //Tick each of the stages
368 fetch.tick();
369
370 decode.tick();
371
372 rename.tick();
373
374 iew.tick();
375
376 commit.tick();
377
378#if !FULL_SYSTEM
379 doContextSwitch();
380#endif
381
382 // Now advance the time buffers
383 timeBuffer.advance();
384
385 fetchQueue.advance();
386 decodeQueue.advance();
387 renameQueue.advance();
388 iewQueue.advance();
389
390 activityRec.advance();
391
392 if (removeInstsThisCycle) {
393 cleanUpRemovedInsts();
394 }
395
396 if (!tickEvent.scheduled()) {
397 if (_status == SwitchedOut) {
398 // increment stat
399 lastRunningCycle = curTick;
400 } else if (!activityRec.active()) {
401 lastRunningCycle = curTick;
402 timesIdled++;
403 } else {
404 tickEvent.schedule(curTick + cycles(1));
405 }
406 }
407
408#if !FULL_SYSTEM
409 updateThreadPriority();
410#endif
411
412}
413
414template <class Impl>
415void
416FullO3CPU<Impl>::init()
417{
418 if (!deferRegistration) {
419 registerThreadContexts();
420 }
421
422 // Set inSyscall so that the CPU doesn't squash when initially
423 // setting up registers.
424 for (int i = 0; i < number_of_threads; ++i)
425 thread[i]->inSyscall = true;
426
427 for (int tid=0; tid < number_of_threads; tid++) {
428#if FULL_SYSTEM
429 ThreadContext *src_tc = threadContexts[tid];
430#else
431 ThreadContext *src_tc = thread[tid]->getTC();
432#endif
433 // Threads start in the Suspended State
434 if (src_tc->status() != ThreadContext::Suspended) {
435 continue;
436 }
437
438#if FULL_SYSTEM
439 TheISA::initCPU(src_tc, src_tc->readCpuId());
440#endif
441 }
442
443 // Clear inSyscall.
444 for (int i = 0; i < number_of_threads; ++i)
445 thread[i]->inSyscall = false;
446
447 // Initialize stages.
448 fetch.initStage();
449 iew.initStage();
450 rename.initStage();
451 commit.initStage();
452
453 commit.setThreads(thread);
454}
455
456template <class Impl>
457void
458FullO3CPU<Impl>::insertThread(unsigned tid)
459{
460 DPRINTF(O3CPU,"[tid:%i] Initializing thread data");
461 // Will change now that the PC and thread state is internal to the CPU
462 // and not in the ThreadContext.
463#if 0
464#if FULL_SYSTEM
465 ThreadContext *src_tc = system->threadContexts[tid];
466#else
467 ThreadContext *src_tc = thread[tid];
468#endif
469
470 //Bind Int Regs to Rename Map
471 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
472 PhysRegIndex phys_reg = freeList.getIntReg();
473
474 renameMap[tid].setEntry(ireg,phys_reg);
475 scoreboard.setReg(phys_reg);
476 }
477
478 //Bind Float Regs to Rename Map
479 for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
480 PhysRegIndex phys_reg = freeList.getFloatReg();
481
482 renameMap[tid].setEntry(freg,phys_reg);
483 scoreboard.setReg(phys_reg);
484 }
485
486 //Copy Thread Data Into RegFile
487 this->copyFromTC(tid);
488
489 //Set PC/NPC
490 regFile.pc[tid] = src_tc->readPC();
491 regFile.npc[tid] = src_tc->readNextPC();
492
493 src_tc->setStatus(ThreadContext::Active);
494
495 activateContext(tid,1);
496
497 //Reset ROB/IQ/LSQ Entries
498 commit.rob->resetEntries();
499 iew.resetEntries();
500#endif
501}
502
503template <class Impl>
504void
505FullO3CPU<Impl>::removeThread(unsigned tid)
506{
507 DPRINTF(O3CPU,"[tid:%i] Removing thread data");
508#if 0
509 //Unbind Int Regs from Rename Map
510 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
511 PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
512
513 scoreboard.unsetReg(phys_reg);
514 freeList.addReg(phys_reg);
515 }
516
517 //Unbind Float Regs from Rename Map
518 for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
519 PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
520
521 scoreboard.unsetReg(phys_reg);
522 freeList.addReg(phys_reg);
523 }
524
525 //Copy Thread Data From RegFile
526 /* Fix Me:
527 * Do we really need to do this if we are removing a thread
528 * in the sense that it's finished (exiting)? If the thread is just
529 * being suspended we might...
530 */
531// this->copyToTC(tid);
532
533 //Squash Throughout Pipeline
534 fetch.squash(0,tid);
535 decode.squash(tid);
536 rename.squash(tid);
537
538 assert(iew.ldstQueue.getCount(tid) == 0);
539
540 //Reset ROB/IQ/LSQ Entries
541 if (activeThreads.size() >= 1) {
542 commit.rob->resetEntries();
543 iew.resetEntries();
544 }
545#endif
546}
547
548
549template <class Impl>
550void
551FullO3CPU<Impl>::activateWhenReady(int tid)
552{
553 DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming"
554 "(e.g. PhysRegs/ROB/IQ/LSQ) \n",
555 tid);
556
557 bool ready = true;
558
559 if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) {
560 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
561 "Phys. Int. Regs.\n",
562 tid);
563 ready = false;
564 } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) {
565 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
566 "Phys. Float. Regs.\n",
567 tid);
568 ready = false;
569 } else if (commit.rob->numFreeEntries() >=
570 commit.rob->entryAmount(activeThreads.size() + 1)) {
571 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
572 "ROB entries.\n",
573 tid);
574 ready = false;
575 } else if (iew.instQueue.numFreeEntries() >=
576 iew.instQueue.entryAmount(activeThreads.size() + 1)) {
577 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
578 "IQ entries.\n",
579 tid);
580 ready = false;
581 } else if (iew.ldstQueue.numFreeEntries() >=
582 iew.ldstQueue.entryAmount(activeThreads.size() + 1)) {
583 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
584 "LSQ entries.\n",
585 tid);
586 ready = false;
587 }
588
589 if (ready) {
590 insertThread(tid);
591
592 contextSwitch = false;
593
594 cpuWaitList.remove(tid);
595 } else {
596 suspendContext(tid);
597
598 //blocks fetch
599 contextSwitch = true;
600
601 //do waitlist
602 cpuWaitList.push_back(tid);
603 }
604}
605
606template <class Impl>
607void
|
577FullO3CPU<Impl>::activateContext(int tid, int delay)
| 608FullO3CPU<Impl>::activateThread(unsigned int tid)
|
578{
| 609{
|
579 // Needs to set each stage to running as well.
| |
580 list<unsigned>::iterator isActive = find(
581 activeThreads.begin(), activeThreads.end(), tid);
582
583 if (isActive == activeThreads.end()) {
| 610 list<unsigned>::iterator isActive = find(
611 activeThreads.begin(), activeThreads.end(), tid);
612
613 if (isActive == activeThreads.end()) {
|
584 //May Need to Re-code this if the delay variable is the
585 //delay needed for thread to activate
586 DPRINTF(O3CPU, "Adding Thread %i to active threads list\n",
| 614 DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n",
|
587 tid);
588
589 activeThreads.push_back(tid);
590 }
| 615 tid);
616
617 activeThreads.push_back(tid);
618 }
|
| 619}
|
591
| 620
|
592 assert(_status == Idle || _status == SwitchedOut);
| |
593
| 621
|
594 scheduleTickEvent(delay);
| 622template <class Impl>
623void
624FullO3CPU<Impl>::activateContext(int tid, int delay)
625{
626 // Needs to set each stage to running as well.
627 if (delay){
628 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate "
629 "on cycle %d\n", tid, curTick + cycles(delay));
630 scheduleActivateThreadEvent(tid, delay);
631 } else {
632 activateThread(tid);
633 }
|
595
| 634
|
596 // Be sure to signal that there's some activity so the CPU doesn't
597 // deschedule itself.
598 activityRec.activity();
599 fetch.wakeFromQuiesce();
| 635 if(lastActivatedCycle < curTick) {
636 scheduleTickEvent(delay);
|
600
| 637
|
601 _status = Running;
| 638 // Be sure to signal that there's some activity so the CPU doesn't
639 // deschedule itself.
640 activityRec.activity();
641 fetch.wakeFromQuiesce();
642
643 lastActivatedCycle = curTick;
644
645 _status = Running;
646 }
|
602}
603
604template <class Impl>
605void
606FullO3CPU<Impl>::suspendContext(int tid)
607{
608 DPRINTF(O3CPU,"[tid: %i]: Suspended ...\n", tid);
609 unscheduleTickEvent();
610 _status = Idle;
611/*
612 //Remove From Active List, if Active
613 list<unsigned>::iterator isActive = find(
614 activeThreads.begin(), activeThreads.end(), tid);
615
616 if (isActive != activeThreads.end()) {
617 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
618 tid);
619 activeThreads.erase(isActive);
620 }
621*/
622}
623
624template <class Impl>
625void
626FullO3CPU<Impl>::deallocateContext(int tid)
627{
628 DPRINTF(O3CPU,"[tid:%i]: Deallocating ...", tid);
629/*
630 //Remove From Active List, if Active
631 list<unsigned>::iterator isActive = find(
632 activeThreads.begin(), activeThreads.end(), tid);
633
634 if (isActive != activeThreads.end()) {
635 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
636 tid);
637 activeThreads.erase(isActive);
638
639 removeThread(tid);
640 }
641*/
642}
643
644template <class Impl>
645void
646FullO3CPU<Impl>::haltContext(int tid)
647{
648 DPRINTF(O3CPU,"[tid:%i]: Halted ...", tid);
649/*
650 //Remove From Active List, if Active
651 list<unsigned>::iterator isActive = find(
652 activeThreads.begin(), activeThreads.end(), tid);
653
654 if (isActive != activeThreads.end()) {
655 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
656 tid);
657 activeThreads.erase(isActive);
658
659 removeThread(tid);
660 }
661*/
662}
663
664template <class Impl>
665void
666FullO3CPU<Impl>::switchOut(Sampler *_sampler)
667{
668 sampler = _sampler;
669 switchCount = 0;
670 fetch.switchOut();
671 decode.switchOut();
672 rename.switchOut();
673 iew.switchOut();
674 commit.switchOut();
675
676 // Wake the CPU and record activity so everything can drain out if
677 // the CPU is currently idle.
678 wakeCPU();
679 activityRec.activity();
680}
681
682template <class Impl>
683void
684FullO3CPU<Impl>::signalSwitched()
685{
686 if (++switchCount == NumStages) {
687 fetch.doSwitchOut();
688 rename.doSwitchOut();
689 commit.doSwitchOut();
690 instList.clear();
691 while (!removeList.empty()) {
692 removeList.pop();
693 }
694
695#if USE_CHECKER
696 if (checker)
697 checker->switchOut(sampler);
698#endif
699
700 if (tickEvent.scheduled())
701 tickEvent.squash();
702 sampler->signalSwitched();
703 _status = SwitchedOut;
704 }
705 assert(switchCount <= 5);
706}
707
708template <class Impl>
709void
710FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
711{
712 // Flush out any old data from the time buffers.
713 for (int i = 0; i < 10; ++i) {
714 timeBuffer.advance();
715 fetchQueue.advance();
716 decodeQueue.advance();
717 renameQueue.advance();
718 iewQueue.advance();
719 }
720
721 activityRec.reset();
722
723 BaseCPU::takeOverFrom(oldCPU);
724
725 fetch.takeOverFrom();
726 decode.takeOverFrom();
727 rename.takeOverFrom();
728 iew.takeOverFrom();
729 commit.takeOverFrom();
730
731 assert(!tickEvent.scheduled());
732
733 // @todo: Figure out how to properly select the tid to put onto
734 // the active threads list.
735 int tid = 0;
736
737 list<unsigned>::iterator isActive = find(
738 activeThreads.begin(), activeThreads.end(), tid);
739
740 if (isActive == activeThreads.end()) {
741 //May Need to Re-code this if the delay variable is the delay
742 //needed for thread to activate
743 DPRINTF(O3CPU, "Adding Thread %i to active threads list\n",
744 tid);
745
746 activeThreads.push_back(tid);
747 }
748
749 // Set all statuses to active, schedule the CPU's tick event.
750 // @todo: Fix up statuses so this is handled properly
751 for (int i = 0; i < threadContexts.size(); ++i) {
752 ThreadContext *tc = threadContexts[i];
753 if (tc->status() == ThreadContext::Active && _status != Running) {
754 _status = Running;
755 tickEvent.schedule(curTick);
756 }
757 }
758 if (!tickEvent.scheduled())
759 tickEvent.schedule(curTick);
760}
761
762template <class Impl>
763uint64_t
764FullO3CPU<Impl>::readIntReg(int reg_idx)
765{
766 return regFile.readIntReg(reg_idx);
767}
768
769template <class Impl>
770FloatReg
771FullO3CPU<Impl>::readFloatReg(int reg_idx, int width)
772{
773 return regFile.readFloatReg(reg_idx, width);
774}
775
776template <class Impl>
777FloatReg
778FullO3CPU<Impl>::readFloatReg(int reg_idx)
779{
780 return regFile.readFloatReg(reg_idx);
781}
782
783template <class Impl>
784FloatRegBits
785FullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width)
786{
787 return regFile.readFloatRegBits(reg_idx, width);
788}
789
790template <class Impl>
791FloatRegBits
792FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
793{
794 return regFile.readFloatRegBits(reg_idx);
795}
796
797template <class Impl>
798void
799FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
800{
801 regFile.setIntReg(reg_idx, val);
802}
803
804template <class Impl>
805void
806FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width)
807{
808 regFile.setFloatReg(reg_idx, val, width);
809}
810
811template <class Impl>
812void
813FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
814{
815 regFile.setFloatReg(reg_idx, val);
816}
817
818template <class Impl>
819void
820FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width)
821{
822 regFile.setFloatRegBits(reg_idx, val, width);
823}
824
825template <class Impl>
826void
827FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
828{
829 regFile.setFloatRegBits(reg_idx, val);
830}
831
832template <class Impl>
833uint64_t
834FullO3CPU<Impl>::readArchIntReg(int reg_idx, unsigned tid)
835{
836 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
837
838 return regFile.readIntReg(phys_reg);
839}
840
841template <class Impl>
842float
843FullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, unsigned tid)
844{
845 int idx = reg_idx + TheISA::FP_Base_DepTag;
846 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
847
848 return regFile.readFloatReg(phys_reg);
849}
850
851template <class Impl>
852double
853FullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, unsigned tid)
854{
855 int idx = reg_idx + TheISA::FP_Base_DepTag;
856 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
857
858 return regFile.readFloatReg(phys_reg, 64);
859}
860
861template <class Impl>
862uint64_t
863FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, unsigned tid)
864{
865 int idx = reg_idx + TheISA::FP_Base_DepTag;
866 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
867
868 return regFile.readFloatRegBits(phys_reg);
869}
870
871template <class Impl>
872void
873FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, unsigned tid)
874{
875 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
876
877 regFile.setIntReg(phys_reg, val);
878}
879
880template <class Impl>
881void
882FullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, unsigned tid)
883{
884 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
885
886 regFile.setFloatReg(phys_reg, val);
887}
888
889template <class Impl>
890void
891FullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, unsigned tid)
892{
893 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
894
895 regFile.setFloatReg(phys_reg, val, 64);
896}
897
898template <class Impl>
899void
900FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid)
901{
902 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
903
904 regFile.setFloatRegBits(phys_reg, val);
905}
906
907template <class Impl>
908uint64_t
909FullO3CPU<Impl>::readPC(unsigned tid)
910{
911 return commit.readPC(tid);
912}
913
914template <class Impl>
915void
916FullO3CPU<Impl>::setPC(Addr new_PC,unsigned tid)
917{
918 commit.setPC(new_PC, tid);
919}
920
921template <class Impl>
922uint64_t
923FullO3CPU<Impl>::readNextPC(unsigned tid)
924{
925 return commit.readNextPC(tid);
926}
927
928template <class Impl>
929void
930FullO3CPU<Impl>::setNextPC(uint64_t val,unsigned tid)
931{
932 commit.setNextPC(val, tid);
933}
934
935#if THE_ISA != ALPHA_ISA
936template <class Impl>
937uint64_t
938FullO3CPU<Impl>::readNextNPC(unsigned tid)
939{
940 return commit.readNextNPC(tid);
941}
942
943template <class Impl>
944void
945FullO3CPU<Impl>::setNextNNPC(uint64_t val,unsigned tid)
946{
947 commit.setNextNPC(val, tid);
948}
949#endif
950
951template <class Impl>
952typename FullO3CPU<Impl>::ListIt
953FullO3CPU<Impl>::addInst(DynInstPtr &inst)
954{
955 instList.push_back(inst);
956
957 return --(instList.end());
958}
959
960template <class Impl>
961void
962FullO3CPU<Impl>::instDone(unsigned tid)
963{
964 // Keep an instruction count.
965 thread[tid]->numInst++;
966 thread[tid]->numInsts++;
967 committedInsts[tid]++;
968 totalCommittedInsts++;
969
970 // Check for instruction-count-based events.
971 comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
972}
973
974template <class Impl>
975void
976FullO3CPU<Impl>::addToRemoveList(DynInstPtr &inst)
977{
978 removeInstsThisCycle = true;
979
980 removeList.push(inst->getInstListIt());
981}
982
983template <class Impl>
984void
985FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
986{
987 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %#x "
988 "[sn:%lli]\n",
989 inst->threadNumber, inst->readPC(), inst->seqNum);
990
991 removeInstsThisCycle = true;
992
993 // Remove the front instruction.
994 removeList.push(inst->getInstListIt());
995}
996
997template <class Impl>
998void
999FullO3CPU<Impl>::removeInstsNotInROB(unsigned tid)
1000{
1001 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1002 " list.\n", tid);
1003
1004 ListIt end_it;
1005
1006 bool rob_empty = false;
1007
1008 if (instList.empty()) {
1009 return;
1010 } else if (rob.isEmpty(/*tid*/)) {
1011 DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1012 end_it = instList.begin();
1013 rob_empty = true;
1014 } else {
1015 end_it = (rob.readTailInst(tid))->getInstListIt();
1016 DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1017 }
1018
1019 removeInstsThisCycle = true;
1020
1021 ListIt inst_it = instList.end();
1022
1023 inst_it--;
1024
1025 // Walk through the instruction list, removing any instructions
1026 // that were inserted after the given instruction iterator, end_it.
1027 while (inst_it != end_it) {
1028 assert(!instList.empty());
1029
1030 squashInstIt(inst_it, tid);
1031
1032 inst_it--;
1033 }
1034
1035 // If the ROB was empty, then we actually need to remove the first
1036 // instruction as well.
1037 if (rob_empty) {
1038 squashInstIt(inst_it, tid);
1039 }
1040}
1041
1042template <class Impl>
1043void
1044FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num,
1045 unsigned tid)
1046{
1047 assert(!instList.empty());
1048
1049 removeInstsThisCycle = true;
1050
1051 ListIt inst_iter = instList.end();
1052
1053 inst_iter--;
1054
1055 DPRINTF(O3CPU, "Deleting instructions from instruction "
1056 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1057 tid, seq_num, (*inst_iter)->seqNum);
1058
1059 while ((*inst_iter)->seqNum > seq_num) {
1060
1061 bool break_loop = (inst_iter == instList.begin());
1062
1063 squashInstIt(inst_iter, tid);
1064
1065 inst_iter--;
1066
1067 if (break_loop)
1068 break;
1069 }
1070}
1071
1072template <class Impl>
1073inline void
1074FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, const unsigned &tid)
1075{
1076 if ((*instIt)->threadNumber == tid) {
1077 DPRINTF(O3CPU, "Squashing instruction, "
1078 "[tid:%i] [sn:%lli] PC %#x\n",
1079 (*instIt)->threadNumber,
1080 (*instIt)->seqNum,
1081 (*instIt)->readPC());
1082
1083 // Mark it as squashed.
1084 (*instIt)->setSquashed();
1085
1086 // @todo: Formulate a consistent method for deleting
1087 // instructions from the instruction list
1088 // Remove the instruction from the list.
1089 removeList.push(instIt);
1090 }
1091}
1092
1093template <class Impl>
1094void
1095FullO3CPU<Impl>::cleanUpRemovedInsts()
1096{
1097 while (!removeList.empty()) {
1098 DPRINTF(O3CPU, "Removing instruction, "
1099 "[tid:%i] [sn:%lli] PC %#x\n",
1100 (*removeList.front())->threadNumber,
1101 (*removeList.front())->seqNum,
1102 (*removeList.front())->readPC());
1103
1104 instList.erase(removeList.front());
1105
1106 removeList.pop();
1107 }
1108
1109 removeInstsThisCycle = false;
1110}
1111/*
1112template <class Impl>
1113void
1114FullO3CPU<Impl>::removeAllInsts()
1115{
1116 instList.clear();
1117}
1118*/
1119template <class Impl>
1120void
1121FullO3CPU<Impl>::dumpInsts()
1122{
1123 int num = 0;
1124
1125 ListIt inst_list_it = instList.begin();
1126
1127 cprintf("Dumping Instruction List\n");
1128
1129 while (inst_list_it != instList.end()) {
1130 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1131 "Squashed:%i\n\n",
1132 num, (*inst_list_it)->readPC(), (*inst_list_it)->threadNumber,
1133 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1134 (*inst_list_it)->isSquashed());
1135 inst_list_it++;
1136 ++num;
1137 }
1138}
1139/*
1140template <class Impl>
1141void
1142FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
1143{
1144 iew.wakeDependents(inst);
1145}
1146*/
1147template <class Impl>
1148void
1149FullO3CPU<Impl>::wakeCPU()
1150{
1151 if (activityRec.active() || tickEvent.scheduled()) {
1152 DPRINTF(Activity, "CPU already running.\n");
1153 return;
1154 }
1155
1156 DPRINTF(Activity, "Waking up CPU\n");
1157
1158 idleCycles += (curTick - 1) - lastRunningCycle;
1159
1160 tickEvent.schedule(curTick);
1161}
1162
1163template <class Impl>
1164int
1165FullO3CPU<Impl>::getFreeTid()
1166{
1167 for (int i=0; i < numThreads; i++) {
1168 if (!tids[i]) {
1169 tids[i] = true;
1170 return i;
1171 }
1172 }
1173
1174 return -1;
1175}
1176
1177template <class Impl>
1178void
1179FullO3CPU<Impl>::doContextSwitch()
1180{
1181 if (contextSwitch) {
1182
1183 //ADD CODE TO DEACTIVE THREAD HERE (???)
1184
1185 for (int tid=0; tid < cpuWaitList.size(); tid++) {
1186 activateWhenReady(tid);
1187 }
1188
1189 if (cpuWaitList.size() == 0)
1190 contextSwitch = true;
1191 }
1192}
1193
1194template <class Impl>
1195void
1196FullO3CPU<Impl>::updateThreadPriority()
1197{
1198 if (activeThreads.size() > 1)
1199 {
1200 //DEFAULT TO ROUND ROBIN SCHEME
1201 //e.g. Move highest priority to end of thread list
1202 list<unsigned>::iterator list_begin = activeThreads.begin();
1203 list<unsigned>::iterator list_end = activeThreads.end();
1204
1205 unsigned high_thread = *list_begin;
1206
1207 activeThreads.erase(list_begin);
1208
1209 activeThreads.push_back(high_thread);
1210 }
1211}
1212
1213// Forward declaration of FullO3CPU.
1214template class FullO3CPU<O3CPUImpl>;
| 647}
648
649template <class Impl>
650void
651FullO3CPU<Impl>::suspendContext(int tid)
652{
653 DPRINTF(O3CPU,"[tid: %i]: Suspended ...\n", tid);
654 unscheduleTickEvent();
655 _status = Idle;
656/*
657 //Remove From Active List, if Active
658 list<unsigned>::iterator isActive = find(
659 activeThreads.begin(), activeThreads.end(), tid);
660
661 if (isActive != activeThreads.end()) {
662 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
663 tid);
664 activeThreads.erase(isActive);
665 }
666*/
667}
668
669template <class Impl>
670void
671FullO3CPU<Impl>::deallocateContext(int tid)
672{
673 DPRINTF(O3CPU,"[tid:%i]: Deallocating ...", tid);
674/*
675 //Remove From Active List, if Active
676 list<unsigned>::iterator isActive = find(
677 activeThreads.begin(), activeThreads.end(), tid);
678
679 if (isActive != activeThreads.end()) {
680 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
681 tid);
682 activeThreads.erase(isActive);
683
684 removeThread(tid);
685 }
686*/
687}
688
689template <class Impl>
690void
691FullO3CPU<Impl>::haltContext(int tid)
692{
693 DPRINTF(O3CPU,"[tid:%i]: Halted ...", tid);
694/*
695 //Remove From Active List, if Active
696 list<unsigned>::iterator isActive = find(
697 activeThreads.begin(), activeThreads.end(), tid);
698
699 if (isActive != activeThreads.end()) {
700 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
701 tid);
702 activeThreads.erase(isActive);
703
704 removeThread(tid);
705 }
706*/
707}
708
709template <class Impl>
710void
711FullO3CPU<Impl>::switchOut(Sampler *_sampler)
712{
713 sampler = _sampler;
714 switchCount = 0;
715 fetch.switchOut();
716 decode.switchOut();
717 rename.switchOut();
718 iew.switchOut();
719 commit.switchOut();
720
721 // Wake the CPU and record activity so everything can drain out if
722 // the CPU is currently idle.
723 wakeCPU();
724 activityRec.activity();
725}
726
727template <class Impl>
728void
729FullO3CPU<Impl>::signalSwitched()
730{
731 if (++switchCount == NumStages) {
732 fetch.doSwitchOut();
733 rename.doSwitchOut();
734 commit.doSwitchOut();
735 instList.clear();
736 while (!removeList.empty()) {
737 removeList.pop();
738 }
739
740#if USE_CHECKER
741 if (checker)
742 checker->switchOut(sampler);
743#endif
744
745 if (tickEvent.scheduled())
746 tickEvent.squash();
747 sampler->signalSwitched();
748 _status = SwitchedOut;
749 }
750 assert(switchCount <= 5);
751}
752
753template <class Impl>
754void
755FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
756{
757 // Flush out any old data from the time buffers.
758 for (int i = 0; i < 10; ++i) {
759 timeBuffer.advance();
760 fetchQueue.advance();
761 decodeQueue.advance();
762 renameQueue.advance();
763 iewQueue.advance();
764 }
765
766 activityRec.reset();
767
768 BaseCPU::takeOverFrom(oldCPU);
769
770 fetch.takeOverFrom();
771 decode.takeOverFrom();
772 rename.takeOverFrom();
773 iew.takeOverFrom();
774 commit.takeOverFrom();
775
776 assert(!tickEvent.scheduled());
777
778 // @todo: Figure out how to properly select the tid to put onto
779 // the active threads list.
780 int tid = 0;
781
782 list<unsigned>::iterator isActive = find(
783 activeThreads.begin(), activeThreads.end(), tid);
784
785 if (isActive == activeThreads.end()) {
786 //May Need to Re-code this if the delay variable is the delay
787 //needed for thread to activate
788 DPRINTF(O3CPU, "Adding Thread %i to active threads list\n",
789 tid);
790
791 activeThreads.push_back(tid);
792 }
793
794 // Set all statuses to active, schedule the CPU's tick event.
795 // @todo: Fix up statuses so this is handled properly
796 for (int i = 0; i < threadContexts.size(); ++i) {
797 ThreadContext *tc = threadContexts[i];
798 if (tc->status() == ThreadContext::Active && _status != Running) {
799 _status = Running;
800 tickEvent.schedule(curTick);
801 }
802 }
803 if (!tickEvent.scheduled())
804 tickEvent.schedule(curTick);
805}
806
807template <class Impl>
808uint64_t
809FullO3CPU<Impl>::readIntReg(int reg_idx)
810{
811 return regFile.readIntReg(reg_idx);
812}
813
814template <class Impl>
815FloatReg
816FullO3CPU<Impl>::readFloatReg(int reg_idx, int width)
817{
818 return regFile.readFloatReg(reg_idx, width);
819}
820
821template <class Impl>
822FloatReg
823FullO3CPU<Impl>::readFloatReg(int reg_idx)
824{
825 return regFile.readFloatReg(reg_idx);
826}
827
828template <class Impl>
829FloatRegBits
830FullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width)
831{
832 return regFile.readFloatRegBits(reg_idx, width);
833}
834
835template <class Impl>
836FloatRegBits
837FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
838{
839 return regFile.readFloatRegBits(reg_idx);
840}
841
842template <class Impl>
843void
844FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
845{
846 regFile.setIntReg(reg_idx, val);
847}
848
849template <class Impl>
850void
851FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width)
852{
853 regFile.setFloatReg(reg_idx, val, width);
854}
855
856template <class Impl>
857void
858FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
859{
860 regFile.setFloatReg(reg_idx, val);
861}
862
863template <class Impl>
864void
865FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width)
866{
867 regFile.setFloatRegBits(reg_idx, val, width);
868}
869
870template <class Impl>
871void
872FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
873{
874 regFile.setFloatRegBits(reg_idx, val);
875}
876
877template <class Impl>
878uint64_t
879FullO3CPU<Impl>::readArchIntReg(int reg_idx, unsigned tid)
880{
881 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
882
883 return regFile.readIntReg(phys_reg);
884}
885
886template <class Impl>
887float
888FullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, unsigned tid)
889{
890 int idx = reg_idx + TheISA::FP_Base_DepTag;
891 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
892
893 return regFile.readFloatReg(phys_reg);
894}
895
896template <class Impl>
897double
898FullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, unsigned tid)
899{
900 int idx = reg_idx + TheISA::FP_Base_DepTag;
901 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
902
903 return regFile.readFloatReg(phys_reg, 64);
904}
905
906template <class Impl>
907uint64_t
908FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, unsigned tid)
909{
910 int idx = reg_idx + TheISA::FP_Base_DepTag;
911 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
912
913 return regFile.readFloatRegBits(phys_reg);
914}
915
916template <class Impl>
917void
918FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, unsigned tid)
919{
920 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
921
922 regFile.setIntReg(phys_reg, val);
923}
924
925template <class Impl>
926void
927FullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, unsigned tid)
928{
929 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
930
931 regFile.setFloatReg(phys_reg, val);
932}
933
934template <class Impl>
935void
936FullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, unsigned tid)
937{
938 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
939
940 regFile.setFloatReg(phys_reg, val, 64);
941}
942
943template <class Impl>
944void
945FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid)
946{
947 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
948
949 regFile.setFloatRegBits(phys_reg, val);
950}
951
952template <class Impl>
953uint64_t
954FullO3CPU<Impl>::readPC(unsigned tid)
955{
956 return commit.readPC(tid);
957}
958
959template <class Impl>
960void
961FullO3CPU<Impl>::setPC(Addr new_PC,unsigned tid)
962{
963 commit.setPC(new_PC, tid);
964}
965
966template <class Impl>
967uint64_t
968FullO3CPU<Impl>::readNextPC(unsigned tid)
969{
970 return commit.readNextPC(tid);
971}
972
973template <class Impl>
974void
975FullO3CPU<Impl>::setNextPC(uint64_t val,unsigned tid)
976{
977 commit.setNextPC(val, tid);
978}
979
980#if THE_ISA != ALPHA_ISA
981template <class Impl>
982uint64_t
983FullO3CPU<Impl>::readNextNPC(unsigned tid)
984{
985 return commit.readNextNPC(tid);
986}
987
988template <class Impl>
989void
990FullO3CPU<Impl>::setNextNNPC(uint64_t val,unsigned tid)
991{
992 commit.setNextNPC(val, tid);
993}
994#endif
995
996template <class Impl>
997typename FullO3CPU<Impl>::ListIt
998FullO3CPU<Impl>::addInst(DynInstPtr &inst)
999{
1000 instList.push_back(inst);
1001
1002 return --(instList.end());
1003}
1004
1005template <class Impl>
1006void
1007FullO3CPU<Impl>::instDone(unsigned tid)
1008{
1009 // Keep an instruction count.
1010 thread[tid]->numInst++;
1011 thread[tid]->numInsts++;
1012 committedInsts[tid]++;
1013 totalCommittedInsts++;
1014
1015 // Check for instruction-count-based events.
1016 comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1017}
1018
1019template <class Impl>
1020void
1021FullO3CPU<Impl>::addToRemoveList(DynInstPtr &inst)
1022{
1023 removeInstsThisCycle = true;
1024
1025 removeList.push(inst->getInstListIt());
1026}
1027
1028template <class Impl>
1029void
1030FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
1031{
1032 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %#x "
1033 "[sn:%lli]\n",
1034 inst->threadNumber, inst->readPC(), inst->seqNum);
1035
1036 removeInstsThisCycle = true;
1037
1038 // Remove the front instruction.
1039 removeList.push(inst->getInstListIt());
1040}
1041
1042template <class Impl>
1043void
1044FullO3CPU<Impl>::removeInstsNotInROB(unsigned tid)
1045{
1046 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1047 " list.\n", tid);
1048
1049 ListIt end_it;
1050
1051 bool rob_empty = false;
1052
1053 if (instList.empty()) {
1054 return;
1055 } else if (rob.isEmpty(/*tid*/)) {
1056 DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1057 end_it = instList.begin();
1058 rob_empty = true;
1059 } else {
1060 end_it = (rob.readTailInst(tid))->getInstListIt();
1061 DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1062 }
1063
1064 removeInstsThisCycle = true;
1065
1066 ListIt inst_it = instList.end();
1067
1068 inst_it--;
1069
1070 // Walk through the instruction list, removing any instructions
1071 // that were inserted after the given instruction iterator, end_it.
1072 while (inst_it != end_it) {
1073 assert(!instList.empty());
1074
1075 squashInstIt(inst_it, tid);
1076
1077 inst_it--;
1078 }
1079
1080 // If the ROB was empty, then we actually need to remove the first
1081 // instruction as well.
1082 if (rob_empty) {
1083 squashInstIt(inst_it, tid);
1084 }
1085}
1086
1087template <class Impl>
1088void
1089FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num,
1090 unsigned tid)
1091{
1092 assert(!instList.empty());
1093
1094 removeInstsThisCycle = true;
1095
1096 ListIt inst_iter = instList.end();
1097
1098 inst_iter--;
1099
1100 DPRINTF(O3CPU, "Deleting instructions from instruction "
1101 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1102 tid, seq_num, (*inst_iter)->seqNum);
1103
1104 while ((*inst_iter)->seqNum > seq_num) {
1105
1106 bool break_loop = (inst_iter == instList.begin());
1107
1108 squashInstIt(inst_iter, tid);
1109
1110 inst_iter--;
1111
1112 if (break_loop)
1113 break;
1114 }
1115}
1116
1117template <class Impl>
1118inline void
1119FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, const unsigned &tid)
1120{
1121 if ((*instIt)->threadNumber == tid) {
1122 DPRINTF(O3CPU, "Squashing instruction, "
1123 "[tid:%i] [sn:%lli] PC %#x\n",
1124 (*instIt)->threadNumber,
1125 (*instIt)->seqNum,
1126 (*instIt)->readPC());
1127
1128 // Mark it as squashed.
1129 (*instIt)->setSquashed();
1130
1131 // @todo: Formulate a consistent method for deleting
1132 // instructions from the instruction list
1133 // Remove the instruction from the list.
1134 removeList.push(instIt);
1135 }
1136}
1137
1138template <class Impl>
1139void
1140FullO3CPU<Impl>::cleanUpRemovedInsts()
1141{
1142 while (!removeList.empty()) {
1143 DPRINTF(O3CPU, "Removing instruction, "
1144 "[tid:%i] [sn:%lli] PC %#x\n",
1145 (*removeList.front())->threadNumber,
1146 (*removeList.front())->seqNum,
1147 (*removeList.front())->readPC());
1148
1149 instList.erase(removeList.front());
1150
1151 removeList.pop();
1152 }
1153
1154 removeInstsThisCycle = false;
1155}
1156/*
1157template <class Impl>
1158void
1159FullO3CPU<Impl>::removeAllInsts()
1160{
1161 instList.clear();
1162}
1163*/
1164template <class Impl>
1165void
1166FullO3CPU<Impl>::dumpInsts()
1167{
1168 int num = 0;
1169
1170 ListIt inst_list_it = instList.begin();
1171
1172 cprintf("Dumping Instruction List\n");
1173
1174 while (inst_list_it != instList.end()) {
1175 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1176 "Squashed:%i\n\n",
1177 num, (*inst_list_it)->readPC(), (*inst_list_it)->threadNumber,
1178 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1179 (*inst_list_it)->isSquashed());
1180 inst_list_it++;
1181 ++num;
1182 }
1183}
1184/*
1185template <class Impl>
1186void
1187FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
1188{
1189 iew.wakeDependents(inst);
1190}
1191*/
1192template <class Impl>
1193void
1194FullO3CPU<Impl>::wakeCPU()
1195{
1196 if (activityRec.active() || tickEvent.scheduled()) {
1197 DPRINTF(Activity, "CPU already running.\n");
1198 return;
1199 }
1200
1201 DPRINTF(Activity, "Waking up CPU\n");
1202
1203 idleCycles += (curTick - 1) - lastRunningCycle;
1204
1205 tickEvent.schedule(curTick);
1206}
1207
1208template <class Impl>
1209int
1210FullO3CPU<Impl>::getFreeTid()
1211{
1212 for (int i=0; i < numThreads; i++) {
1213 if (!tids[i]) {
1214 tids[i] = true;
1215 return i;
1216 }
1217 }
1218
1219 return -1;
1220}
1221
1222template <class Impl>
1223void
1224FullO3CPU<Impl>::doContextSwitch()
1225{
1226 if (contextSwitch) {
1227
1228 //ADD CODE TO DEACTIVE THREAD HERE (???)
1229
1230 for (int tid=0; tid < cpuWaitList.size(); tid++) {
1231 activateWhenReady(tid);
1232 }
1233
1234 if (cpuWaitList.size() == 0)
1235 contextSwitch = true;
1236 }
1237}
1238
1239template <class Impl>
1240void
1241FullO3CPU<Impl>::updateThreadPriority()
1242{
1243 if (activeThreads.size() > 1)
1244 {
1245 //DEFAULT TO ROUND ROBIN SCHEME
1246 //e.g. Move highest priority to end of thread list
1247 list<unsigned>::iterator list_begin = activeThreads.begin();
1248 list<unsigned>::iterator list_end = activeThreads.end();
1249
1250 unsigned high_thread = *list_begin;
1251
1252 activeThreads.erase(list_begin);
1253
1254 activeThreads.push_back(high_thread);
1255 }
1256}
1257
1258// Forward declaration of FullO3CPU.
1259template class FullO3CPU<O3CPUImpl>;
|