1/*
2 * Copyright (c) 2011-2012, 2014, 2016, 2017 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * Copyright (c) 2011 Regents of the University of California
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Kevin Lim
43 * Korey Sewell
44 * Rick Strong
45 */
46
47#include "cpu/o3/cpu.hh"
48
49#include "arch/generic/traits.hh"
50#include "arch/kernel_stats.hh"
51#include "config/the_isa.hh"
52#include "cpu/activity.hh"
53#include "cpu/checker/cpu.hh"
54#include "cpu/checker/thread_context.hh"
55#include "cpu/o3/isa_specific.hh"
56#include "cpu/o3/thread_context.hh"
57#include "cpu/quiesce_event.hh"
58#include "cpu/simple_thread.hh"
59#include "cpu/thread_context.hh"
60#include "debug/Activity.hh"
61#include "debug/Drain.hh"
62#include "debug/O3CPU.hh"
63#include "debug/Quiesce.hh"
64#include "enums/MemoryMode.hh"
65#include "sim/core.hh"
66#include "sim/full_system.hh"
67#include "sim/process.hh"
68#include "sim/stat_control.hh"
69#include "sim/system.hh"
70
71#if THE_ISA == ALPHA_ISA
72#include "arch/alpha/osfpal.hh"
73#include "debug/Activity.hh"
74
75#endif
76
77struct BaseCPUParams;
78
79using namespace TheISA;
80using namespace std;
81
82BaseO3CPU::BaseO3CPU(BaseCPUParams *params)
83 : BaseCPU(params)
84{
85}
86
87void
88BaseO3CPU::regStats()
89{
90 BaseCPU::regStats();
91}
92
93template<class Impl>
94bool
95FullO3CPU<Impl>::IcachePort::recvTimingResp(PacketPtr pkt)
96{
97 DPRINTF(O3CPU, "Fetch unit received timing\n");
98 // We shouldn't ever get a cacheable block in Modified state
99 assert(pkt->req->isUncacheable() ||
100 !(pkt->cacheResponding() && !pkt->hasSharers()));
101 fetch->processCacheCompletion(pkt);
102
103 return true;
104}
105
106template<class Impl>
107void
108FullO3CPU<Impl>::IcachePort::recvReqRetry()
109{
110 fetch->recvReqRetry();
111}
112
113template <class Impl>
114bool
115FullO3CPU<Impl>::DcachePort::recvTimingResp(PacketPtr pkt)
116{
117 return lsq->recvTimingResp(pkt);
118}
119
120template <class Impl>
121void
122FullO3CPU<Impl>::DcachePort::recvTimingSnoopReq(PacketPtr pkt)
123{
124 for (ThreadID tid = 0; tid < cpu->numThreads; tid++) {
125 if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) {
126 cpu->wakeup(tid);
127 }
128 }
129 lsq->recvTimingSnoopReq(pkt);
130}
131
132template <class Impl>
133void
134FullO3CPU<Impl>::DcachePort::recvReqRetry()
135{
136 lsq->recvReqRetry();
137}
138
139template <class Impl>
140FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
141 : BaseO3CPU(params),
142 itb(params->itb),
143 dtb(params->dtb),
144 tickEvent([this]{ tick(); }, "FullO3CPU tick",
145 false, Event::CPU_Tick_Pri),
146#ifndef NDEBUG
147 instcount(0),
148#endif
149 removeInstsThisCycle(false),
150 fetch(this, params),
151 decode(this, params),
152 rename(this, params),
153 iew(this, params),
154 commit(this, params),
155
156 /* It is mandatory that all SMT threads use the same renaming mode as
157 * they are sharing registers and rename */
158 vecMode(initRenameMode<TheISA::ISA>::mode(params->isa[0])),
159 regFile(params->numPhysIntRegs,
160 params->numPhysFloatRegs,
161 params->numPhysVecRegs,
162 params->numPhysCCRegs,
163 vecMode),
164
165 freeList(name() + ".freelist", ®File),
166
167 rob(this, params),
168
169 scoreboard(name() + ".scoreboard",
170 regFile.totalNumPhysRegs()),
171
172 isa(numThreads, NULL),
173
174 icachePort(&fetch, this),
175 dcachePort(&iew.ldstQueue, this),
176
177 timeBuffer(params->backComSize, params->forwardComSize),
178 fetchQueue(params->backComSize, params->forwardComSize),
179 decodeQueue(params->backComSize, params->forwardComSize),
180 renameQueue(params->backComSize, params->forwardComSize),
181 iewQueue(params->backComSize, params->forwardComSize),
182 activityRec(name(), NumStages,
183 params->backComSize + params->forwardComSize,
184 params->activity),
185
186 globalSeqNum(1),
187 system(params->system),
188 lastRunningCycle(curCycle())
189{
190 if (!params->switched_out) {
191 _status = Running;
192 } else {
193 _status = SwitchedOut;
194 }
195
196 if (params->checker) {
197 BaseCPU *temp_checker = params->checker;
198 checker = dynamic_cast<Checker<Impl> *>(temp_checker);
199 checker->setIcachePort(&icachePort);
200 checker->setSystem(params->system);
201 } else {
202 checker = NULL;
203 }
204
205 if (!FullSystem) {
206 thread.resize(numThreads);
207 tids.resize(numThreads);
208 }
209
210 // The stages also need their CPU pointer setup. However this
211 // must be done at the upper level CPU because they have pointers
212 // to the upper level CPU, and not this FullO3CPU.
213
214 // Set up Pointers to the activeThreads list for each stage
215 fetch.setActiveThreads(&activeThreads);
216 decode.setActiveThreads(&activeThreads);
217 rename.setActiveThreads(&activeThreads);
218 iew.setActiveThreads(&activeThreads);
219 commit.setActiveThreads(&activeThreads);
220
221 // Give each of the stages the time buffer they will use.
222 fetch.setTimeBuffer(&timeBuffer);
223 decode.setTimeBuffer(&timeBuffer);
224 rename.setTimeBuffer(&timeBuffer);
225 iew.setTimeBuffer(&timeBuffer);
226 commit.setTimeBuffer(&timeBuffer);
227
228 // Also setup each of the stages' queues.
229 fetch.setFetchQueue(&fetchQueue);
230 decode.setFetchQueue(&fetchQueue);
231 commit.setFetchQueue(&fetchQueue);
232 decode.setDecodeQueue(&decodeQueue);
233 rename.setDecodeQueue(&decodeQueue);
234 rename.setRenameQueue(&renameQueue);
235 iew.setRenameQueue(&renameQueue);
236 iew.setIEWQueue(&iewQueue);
237 commit.setIEWQueue(&iewQueue);
238 commit.setRenameQueue(&renameQueue);
239
240 commit.setIEWStage(&iew);
241 rename.setIEWStage(&iew);
242 rename.setCommitStage(&commit);
243
244 ThreadID active_threads;
245 if (FullSystem) {
246 active_threads = 1;
247 } else {
248 active_threads = params->workload.size();
249
250 if (active_threads > Impl::MaxThreads) {
251 panic("Workload Size too large. Increase the 'MaxThreads' "
252 "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) "
253 "or edit your workload size.");
254 }
255 }
256
257 //Make Sure That this a Valid Architeture
258 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs);
259 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
260 assert(params->numPhysVecRegs >= numThreads * TheISA::NumVecRegs);
261 assert(params->numPhysCCRegs >= numThreads * TheISA::NumCCRegs);
262
263 rename.setScoreboard(&scoreboard);
264 iew.setScoreboard(&scoreboard);
265
266 // Setup the rename map for whichever stages need it.
267 for (ThreadID tid = 0; tid < numThreads; tid++) {
268 isa[tid] = params->isa[tid];
269 assert(initRenameMode<TheISA::ISA>::equals(isa[tid], isa[0]));
270
271 // Only Alpha has an FP zero register, so for other ISAs we
272 // use an invalid FP register index to avoid special treatment
273 // of any valid FP reg.
274 RegIndex invalidFPReg = TheISA::NumFloatRegs + 1;
275 RegIndex fpZeroReg =
276 (THE_ISA == ALPHA_ISA) ? TheISA::ZeroReg : invalidFPReg;
277
278 commitRenameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg,
279 &freeList,
280 vecMode);
281
282 renameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg,
283 &freeList, vecMode);
284 }
285
286 // Initialize rename map to assign physical registers to the
287 // architectural registers for active threads only.
288 for (ThreadID tid = 0; tid < active_threads; tid++) {
289 for (RegIndex ridx = 0; ridx < TheISA::NumIntRegs; ++ridx) {
290 // Note that we can't use the rename() method because we don't
291 // want special treatment for the zero register at this point
292 PhysRegIdPtr phys_reg = freeList.getIntReg();
293 renameMap[tid].setEntry(RegId(IntRegClass, ridx), phys_reg);
294 commitRenameMap[tid].setEntry(RegId(IntRegClass, ridx), phys_reg);
295 }
296
297 for (RegIndex ridx = 0; ridx < TheISA::NumFloatRegs; ++ridx) {
298 PhysRegIdPtr phys_reg = freeList.getFloatReg();
299 renameMap[tid].setEntry(RegId(FloatRegClass, ridx), phys_reg);
300 commitRenameMap[tid].setEntry(
301 RegId(FloatRegClass, ridx), phys_reg);
302 }
303
304 /* Here we need two 'interfaces' the 'whole register' and the
305 * 'register element'. At any point only one of them will be
306 * active. */
307 if (vecMode == Enums::Full) {
308 /* Initialize the full-vector interface */
309 for (RegIndex ridx = 0; ridx < TheISA::NumVecRegs; ++ridx) {
310 RegId rid = RegId(VecRegClass, ridx);
311 PhysRegIdPtr phys_reg = freeList.getVecReg();
312 renameMap[tid].setEntry(rid, phys_reg);
313 commitRenameMap[tid].setEntry(rid, phys_reg);
314 }
315 } else {
316 /* Initialize the vector-element interface */
317 for (RegIndex ridx = 0; ridx < TheISA::NumVecRegs; ++ridx) {
318 for (ElemIndex ldx = 0; ldx < TheISA::NumVecElemPerVecReg;
319 ++ldx) {
320 RegId lrid = RegId(VecElemClass, ridx, ldx);
321 PhysRegIdPtr phys_elem = freeList.getVecElem();
322 renameMap[tid].setEntry(lrid, phys_elem);
323 commitRenameMap[tid].setEntry(lrid, phys_elem);
324 }
325 }
326 }
327
328 for (RegIndex ridx = 0; ridx < TheISA::NumCCRegs; ++ridx) {
329 PhysRegIdPtr phys_reg = freeList.getCCReg();
330 renameMap[tid].setEntry(RegId(CCRegClass, ridx), phys_reg);
331 commitRenameMap[tid].setEntry(RegId(CCRegClass, ridx), phys_reg);
332 }
333 }
334
335 rename.setRenameMap(renameMap);
336 commit.setRenameMap(commitRenameMap);
337 rename.setFreeList(&freeList);
338
339 // Setup the ROB for whichever stages need it.
340 commit.setROB(&rob);
341
342 lastActivatedCycle = 0;
343#if 0
344 // Give renameMap & rename stage access to the freeList;
345 for (ThreadID tid = 0; tid < numThreads; tid++)
346 globalSeqNum[tid] = 1;
347#endif
348
349 DPRINTF(O3CPU, "Creating O3CPU object.\n");
350
351 // Setup any thread state.
352 this->thread.resize(this->numThreads);
353
354 for (ThreadID tid = 0; tid < this->numThreads; ++tid) {
355 if (FullSystem) {
356 // SMT is not supported in FS mode yet.
357 assert(this->numThreads == 1);
358 this->thread[tid] = new Thread(this, 0, NULL);
359 } else {
360 if (tid < params->workload.size()) {
361 DPRINTF(O3CPU, "Workload[%i] process is %#x",
362 tid, this->thread[tid]);
363 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
364 (typename Impl::O3CPU *)(this),
365 tid, params->workload[tid]);
366
367 //usedTids[tid] = true;
368 //threadMap[tid] = tid;
369 } else {
370 //Allocate Empty thread so M5 can use later
371 //when scheduling threads to CPU
372 Process* dummy_proc = NULL;
373
374 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
375 (typename Impl::O3CPU *)(this),
376 tid, dummy_proc);
377 //usedTids[tid] = false;
378 }
379 }
380
381 ThreadContext *tc;
382
383 // Setup the TC that will serve as the interface to the threads/CPU.
384 O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>;
385
386 tc = o3_tc;
387
388 // If we're using a checker, then the TC should be the
389 // CheckerThreadContext.
390 if (params->checker) {
391 tc = new CheckerThreadContext<O3ThreadContext<Impl> >(
392 o3_tc, this->checker);
393 }
394
395 o3_tc->cpu = (typename Impl::O3CPU *)(this);
396 assert(o3_tc->cpu);
397 o3_tc->thread = this->thread[tid];
398
399 // Setup quiesce event.
400 this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
401
402 // Give the thread the TC.
403 this->thread[tid]->tc = tc;
404
405 // Add the TC to the CPU's list of TC's.
406 this->threadContexts.push_back(tc);
407 }
408
409 // FullO3CPU always requires an interrupt controller.
410 if (!params->switched_out && interrupts.empty()) {
411 fatal("FullO3CPU %s has no interrupt controller.\n"
412 "Ensure createInterruptController() is called.\n", name());
413 }
414
415 for (ThreadID tid = 0; tid < this->numThreads; tid++)
416 this->thread[tid]->setFuncExeInst(0);
417}
418
419template <class Impl>
420FullO3CPU<Impl>::~FullO3CPU()
421{
422}
423
424template <class Impl>
425void
426FullO3CPU<Impl>::regProbePoints()
427{
428 BaseCPU::regProbePoints();
429
430 ppInstAccessComplete = new ProbePointArg<PacketPtr>(getProbeManager(), "InstAccessComplete");
431 ppDataAccessComplete = new ProbePointArg<std::pair<DynInstPtr, PacketPtr> >(getProbeManager(), "DataAccessComplete");
432
433 fetch.regProbePoints();
434 rename.regProbePoints();
435 iew.regProbePoints();
436 commit.regProbePoints();
437}
438
439template <class Impl>
440void
441FullO3CPU<Impl>::regStats()
442{
443 BaseO3CPU::regStats();
444
445 // Register any of the O3CPU's stats here.
446 timesIdled
447 .name(name() + ".timesIdled")
448 .desc("Number of times that the entire CPU went into an idle state and"
449 " unscheduled itself")
450 .prereq(timesIdled);
451
452 idleCycles
453 .name(name() + ".idleCycles")
454 .desc("Total number of cycles that the CPU has spent unscheduled due "
455 "to idling")
456 .prereq(idleCycles);
457
458 quiesceCycles
459 .name(name() + ".quiesceCycles")
460 .desc("Total number of cycles that CPU has spent quiesced or waiting "
461 "for an interrupt")
462 .prereq(quiesceCycles);
463
464 // Number of Instructions simulated
465 // --------------------------------
466 // Should probably be in Base CPU but need templated
467 // MaxThreads so put in here instead
468 committedInsts
469 .init(numThreads)
470 .name(name() + ".committedInsts")
471 .desc("Number of Instructions Simulated")
472 .flags(Stats::total);
473
474 committedOps
475 .init(numThreads)
476 .name(name() + ".committedOps")
477 .desc("Number of Ops (including micro ops) Simulated")
478 .flags(Stats::total);
479
480 cpi
481 .name(name() + ".cpi")
482 .desc("CPI: Cycles Per Instruction")
483 .precision(6);
484 cpi = numCycles / committedInsts;
485
486 totalCpi
487 .name(name() + ".cpi_total")
488 .desc("CPI: Total CPI of All Threads")
489 .precision(6);
490 totalCpi = numCycles / sum(committedInsts);
491
492 ipc
493 .name(name() + ".ipc")
494 .desc("IPC: Instructions Per Cycle")
495 .precision(6);
496 ipc = committedInsts / numCycles;
497
498 totalIpc
499 .name(name() + ".ipc_total")
500 .desc("IPC: Total IPC of All Threads")
501 .precision(6);
502 totalIpc = sum(committedInsts) / numCycles;
503
504 this->fetch.regStats();
505 this->decode.regStats();
506 this->rename.regStats();
507 this->iew.regStats();
508 this->commit.regStats();
509 this->rob.regStats();
510
511 intRegfileReads
512 .name(name() + ".int_regfile_reads")
513 .desc("number of integer regfile reads")
514 .prereq(intRegfileReads);
515
516 intRegfileWrites
517 .name(name() + ".int_regfile_writes")
518 .desc("number of integer regfile writes")
519 .prereq(intRegfileWrites);
520
521 fpRegfileReads
522 .name(name() + ".fp_regfile_reads")
523 .desc("number of floating regfile reads")
524 .prereq(fpRegfileReads);
525
526 fpRegfileWrites
527 .name(name() + ".fp_regfile_writes")
528 .desc("number of floating regfile writes")
529 .prereq(fpRegfileWrites);
530
531 vecRegfileReads
532 .name(name() + ".vec_regfile_reads")
533 .desc("number of vector regfile reads")
534 .prereq(vecRegfileReads);
535
536 vecRegfileWrites
537 .name(name() + ".vec_regfile_writes")
538 .desc("number of vector regfile writes")
539 .prereq(vecRegfileWrites);
540
541 ccRegfileReads
542 .name(name() + ".cc_regfile_reads")
543 .desc("number of cc regfile reads")
544 .prereq(ccRegfileReads);
545
546 ccRegfileWrites
547 .name(name() + ".cc_regfile_writes")
548 .desc("number of cc regfile writes")
549 .prereq(ccRegfileWrites);
550
551 miscRegfileReads
552 .name(name() + ".misc_regfile_reads")
553 .desc("number of misc regfile reads")
554 .prereq(miscRegfileReads);
555
556 miscRegfileWrites
557 .name(name() + ".misc_regfile_writes")
558 .desc("number of misc regfile writes")
559 .prereq(miscRegfileWrites);
560}
561
562template <class Impl>
563void
564FullO3CPU<Impl>::tick()
565{
566 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
567 assert(!switchedOut());
568 assert(drainState() != DrainState::Drained);
569
570 ++numCycles;
571 updateCycleCounters(BaseCPU::CPU_STATE_ON);
572
573// activity = false;
574
575 //Tick each of the stages
576 fetch.tick();
577
578 decode.tick();
579
580 rename.tick();
581
582 iew.tick();
583
584 commit.tick();
585
586 // Now advance the time buffers
587 timeBuffer.advance();
588
589 fetchQueue.advance();
590 decodeQueue.advance();
591 renameQueue.advance();
592 iewQueue.advance();
593
594 activityRec.advance();
595
596 if (removeInstsThisCycle) {
597 cleanUpRemovedInsts();
598 }
599
600 if (!tickEvent.scheduled()) {
601 if (_status == SwitchedOut) {
602 DPRINTF(O3CPU, "Switched out!\n");
603 // increment stat
604 lastRunningCycle = curCycle();
605 } else if (!activityRec.active() || _status == Idle) {
606 DPRINTF(O3CPU, "Idle!\n");
607 lastRunningCycle = curCycle();
608 timesIdled++;
609 } else {
610 schedule(tickEvent, clockEdge(Cycles(1)));
611 DPRINTF(O3CPU, "Scheduling next tick!\n");
612 }
613 }
614
615 if (!FullSystem)
616 updateThreadPriority();
617
618 tryDrain();
619}
620
621template <class Impl>
622void
623FullO3CPU<Impl>::init()
624{
625 BaseCPU::init();
626
627 for (ThreadID tid = 0; tid < numThreads; ++tid) {
628 // Set noSquashFromTC so that the CPU doesn't squash when initially
629 // setting up registers.
630 thread[tid]->noSquashFromTC = true;
631 // Initialise the ThreadContext's memory proxies
632 thread[tid]->initMemProxies(thread[tid]->getTC());
633 }
634
635 if (FullSystem && !params()->switched_out) {
636 for (ThreadID tid = 0; tid < numThreads; tid++) {
637 ThreadContext *src_tc = threadContexts[tid];
638 TheISA::initCPU(src_tc, src_tc->contextId());
639 }
640 }
641
642 // Clear noSquashFromTC.
643 for (int tid = 0; tid < numThreads; ++tid)
644 thread[tid]->noSquashFromTC = false;
645
646 commit.setThreads(thread);
647}
648
649template <class Impl>
650void
651FullO3CPU<Impl>::startup()
652{
653 BaseCPU::startup();
654 for (int tid = 0; tid < numThreads; ++tid)
655 isa[tid]->startup(threadContexts[tid]);
656
657 fetch.startupStage();
658 decode.startupStage();
659 iew.startupStage();
660 rename.startupStage();
661 commit.startupStage();
662}
663
664template <class Impl>
665void
666FullO3CPU<Impl>::activateThread(ThreadID tid)
667{
668 list<ThreadID>::iterator isActive =
669 std::find(activeThreads.begin(), activeThreads.end(), tid);
670
671 DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid);
672 assert(!switchedOut());
673
674 if (isActive == activeThreads.end()) {
675 DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n",
676 tid);
677
678 activeThreads.push_back(tid);
679 }
680}
681
682template <class Impl>
683void
684FullO3CPU<Impl>::deactivateThread(ThreadID tid)
685{
686 //Remove From Active List, if Active
687 list<ThreadID>::iterator thread_it =
688 std::find(activeThreads.begin(), activeThreads.end(), tid);
689
690 DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid);
691 assert(!switchedOut());
692
693 if (thread_it != activeThreads.end()) {
694 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
695 tid);
696 activeThreads.erase(thread_it);
697 }
698
699 fetch.deactivateThread(tid);
700 commit.deactivateThread(tid);
701}
702
703template <class Impl>
704Counter
705FullO3CPU<Impl>::totalInsts() const
706{
707 Counter total(0);
708
709 ThreadID size = thread.size();
710 for (ThreadID i = 0; i < size; i++)
711 total += thread[i]->numInst;
712
713 return total;
714}
715
716template <class Impl>
717Counter
718FullO3CPU<Impl>::totalOps() const
719{
720 Counter total(0);
721
722 ThreadID size = thread.size();
723 for (ThreadID i = 0; i < size; i++)
724 total += thread[i]->numOp;
725
726 return total;
727}
728
729template <class Impl>
730void
731FullO3CPU<Impl>::activateContext(ThreadID tid)
732{
733 assert(!switchedOut());
734
735 // Needs to set each stage to running as well.
736 activateThread(tid);
737
738 // We don't want to wake the CPU if it is drained. In that case,
739 // we just want to flag the thread as active and schedule the tick
740 // event from drainResume() instead.
741 if (drainState() == DrainState::Drained)
742 return;
743
744 // If we are time 0 or if the last activation time is in the past,
745 // schedule the next tick and wake up the fetch unit
746 if (lastActivatedCycle == 0 || lastActivatedCycle < curTick()) {
747 scheduleTickEvent(Cycles(0));
748
749 // Be sure to signal that there's some activity so the CPU doesn't
750 // deschedule itself.
751 activityRec.activity();
752 fetch.wakeFromQuiesce();
753
754 Cycles cycles(curCycle() - lastRunningCycle);
755 // @todo: This is an oddity that is only here to match the stats
756 if (cycles != 0)
757 --cycles;
758 quiesceCycles += cycles;
759
760 lastActivatedCycle = curTick();
761
762 _status = Running;
763
764 BaseCPU::activateContext(tid);
765 }
766}
767
768template <class Impl>
769void
770FullO3CPU<Impl>::suspendContext(ThreadID tid)
771{
772 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
773 assert(!switchedOut());
774
775 deactivateThread(tid);
776
777 // If this was the last thread then unschedule the tick event.
778 if (activeThreads.size() == 0) {
779 unscheduleTickEvent();
780 lastRunningCycle = curCycle();
781 _status = Idle;
782 }
783
784 DPRINTF(Quiesce, "Suspending Context\n");
785
786 BaseCPU::suspendContext(tid);
787}
788
789template <class Impl>
790void
791FullO3CPU<Impl>::haltContext(ThreadID tid)
792{
793 //For now, this is the same as deallocate
794 DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
795 assert(!switchedOut());
796
797 deactivateThread(tid);
798 removeThread(tid);
799
800 updateCycleCounters(BaseCPU::CPU_STATE_SLEEP);
801}
802
803template <class Impl>
804void
805FullO3CPU<Impl>::insertThread(ThreadID tid)
806{
807 DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
808 // Will change now that the PC and thread state is internal to the CPU
809 // and not in the ThreadContext.
810 ThreadContext *src_tc;
811 if (FullSystem)
812 src_tc = system->threadContexts[tid];
813 else
814 src_tc = tcBase(tid);
815
816 //Bind Int Regs to Rename Map
817
818 for (RegId reg_id(IntRegClass, 0); reg_id.index() < TheISA::NumIntRegs;
819 reg_id.index()++) {
820 PhysRegIdPtr phys_reg = freeList.getIntReg();
821 renameMap[tid].setEntry(reg_id, phys_reg);
822 scoreboard.setReg(phys_reg);
823 }
824
825 //Bind Float Regs to Rename Map
826 for (RegId reg_id(FloatRegClass, 0); reg_id.index() < TheISA::NumFloatRegs;
827 reg_id.index()++) {
828 PhysRegIdPtr phys_reg = freeList.getFloatReg();
829 renameMap[tid].setEntry(reg_id, phys_reg);
830 scoreboard.setReg(phys_reg);
831 }
832
833 //Bind condition-code Regs to Rename Map
834 for (RegId reg_id(CCRegClass, 0); reg_id.index() < TheISA::NumCCRegs;
835 reg_id.index()++) {
836 PhysRegIdPtr phys_reg = freeList.getCCReg();
837 renameMap[tid].setEntry(reg_id, phys_reg);
838 scoreboard.setReg(phys_reg);
839 }
840
841 //Copy Thread Data Into RegFile
842 //this->copyFromTC(tid);
843
844 //Set PC/NPC/NNPC
845 pcState(src_tc->pcState(), tid);
846
847 src_tc->setStatus(ThreadContext::Active);
848
849 activateContext(tid);
850
851 //Reset ROB/IQ/LSQ Entries
852 commit.rob->resetEntries();
853}
854
855template <class Impl>
856void
857FullO3CPU<Impl>::removeThread(ThreadID tid)
858{
859 DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
860
861 // Copy Thread Data From RegFile
862 // If thread is suspended, it might be re-allocated
863 // this->copyToTC(tid);
864
865
866 // @todo: 2-27-2008: Fix how we free up rename mappings
867 // here to alleviate the case for double-freeing registers
868 // in SMT workloads.
869
870 // Unbind Int Regs from Rename Map
871 for (RegId reg_id(IntRegClass, 0); reg_id.index() < TheISA::NumIntRegs;
872 reg_id.index()++) {
873 PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id);
874 scoreboard.unsetReg(phys_reg);
875 freeList.addReg(phys_reg);
876 }
877
878 // Unbind Float Regs from Rename Map
879 for (RegId reg_id(FloatRegClass, 0); reg_id.index() < TheISA::NumFloatRegs;
880 reg_id.index()++) {
881 PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id);
882 scoreboard.unsetReg(phys_reg);
883 freeList.addReg(phys_reg);
884 }
885
886 // Unbind condition-code Regs from Rename Map
887 for (RegId reg_id(CCRegClass, 0); reg_id.index() < TheISA::NumCCRegs;
888 reg_id.index()++) {
889 PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id);
890 scoreboard.unsetReg(phys_reg);
891 freeList.addReg(phys_reg);
892 }
893
894 // Squash Throughout Pipeline
895 DynInstPtr inst = commit.rob->readHeadInst(tid);
896 InstSeqNum squash_seq_num = inst->seqNum;
897 fetch.squash(0, squash_seq_num, inst, tid);
898 decode.squash(tid);
899 rename.squash(squash_seq_num, tid);
900 iew.squash(tid);
901 iew.ldstQueue.squash(squash_seq_num, tid);
902 commit.rob->squash(squash_seq_num, tid);
903
904
905 assert(iew.instQueue.getCount(tid) == 0);
906 assert(iew.ldstQueue.getCount(tid) == 0);
907
908 // Reset ROB/IQ/LSQ Entries
909
910 // Commented out for now. This should be possible to do by
911 // telling all the pipeline stages to drain first, and then
912 // checking until the drain completes. Once the pipeline is
913 // drained, call resetEntries(). - 10-09-06 ktlim
914/*
915 if (activeThreads.size() >= 1) {
916 commit.rob->resetEntries();
917 iew.resetEntries();
918 }
919*/
920}
921
922template <class Impl>
923Fault
924FullO3CPU<Impl>::hwrei(ThreadID tid)
925{
926#if THE_ISA == ALPHA_ISA
927 // Need to clear the lock flag upon returning from an interrupt.
928 this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
929
930 this->thread[tid]->kernelStats->hwrei();
931
932 // FIXME: XXX check for interrupts? XXX
933#endif
934 return NoFault;
935}
936
937template <class Impl>
938bool
939FullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid)
940{
941#if THE_ISA == ALPHA_ISA
942 if (this->thread[tid]->kernelStats)
943 this->thread[tid]->kernelStats->callpal(palFunc,
944 this->threadContexts[tid]);
945
946 switch (palFunc) {
947 case PAL::halt:
948 halt();
949 if (--System::numSystemsRunning == 0)
950 exitSimLoop("all cpus halted");
951 break;
952
953 case PAL::bpt:
954 case PAL::bugchk:
955 if (this->system->breakpoint())
956 return false;
957 break;
958 }
959#endif
960 return true;
961}
962
963template <class Impl>
964Fault
965FullO3CPU<Impl>::getInterrupts()
966{
967 // Check if there are any outstanding interrupts
968 return this->interrupts[0]->getInterrupt(this->threadContexts[0]);
969}
970
971template <class Impl>
972void
973FullO3CPU<Impl>::processInterrupts(const Fault &interrupt)
974{
975 // Check for interrupts here. For now can copy the code that
976 // exists within isa_fullsys_traits.hh. Also assume that thread 0
977 // is the one that handles the interrupts.
978 // @todo: Possibly consolidate the interrupt checking code.
979 // @todo: Allow other threads to handle interrupts.
980
981 assert(interrupt != NoFault);
982 this->interrupts[0]->updateIntrInfo(this->threadContexts[0]);
983
984 DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
985 this->trap(interrupt, 0, nullptr);
986}
987
988template <class Impl>
989void
990FullO3CPU<Impl>::trap(const Fault &fault, ThreadID tid,
991 const StaticInstPtr &inst)
992{
993 // Pass the thread's TC into the invoke method.
994 fault->invoke(this->threadContexts[tid], inst);
995}
996
997template <class Impl>
998void
999FullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid, Fault *fault)
1000{
1001 DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid);
1002
1003 DPRINTF(Activity,"Activity: syscall() called.\n");
1004
1005 // Temporarily increase this by one to account for the syscall
1006 // instruction.
1007 ++(this->thread[tid]->funcExeInst);
1008
1009 // Execute the actual syscall.
1010 this->thread[tid]->syscall(callnum, fault);
1011
1012 // Decrease funcExeInst by one as the normal commit will handle
1013 // incrementing it.
1014 --(this->thread[tid]->funcExeInst);
1015}
1016
1017template <class Impl>
1018void
1019FullO3CPU<Impl>::serializeThread(CheckpointOut &cp, ThreadID tid) const
1020{
1021 thread[tid]->serialize(cp);
1022}
1023
1024template <class Impl>
1025void
1026FullO3CPU<Impl>::unserializeThread(CheckpointIn &cp, ThreadID tid)
1027{
1028 thread[tid]->unserialize(cp);
1029}
1030
1031template <class Impl>
1032DrainState
1033FullO3CPU<Impl>::drain()
1034{
1035 // Deschedule any power gating event (if any)
1036 deschedulePowerGatingEvent();
1037
1038 // If the CPU isn't doing anything, then return immediately.
1039 if (switchedOut())
1040 return DrainState::Drained;
1041
1042 DPRINTF(Drain, "Draining...\n");
1043
1044 // We only need to signal a drain to the commit stage as this
1045 // initiates squashing controls the draining. Once the commit
1046 // stage commits an instruction where it is safe to stop, it'll
1047 // squash the rest of the instructions in the pipeline and force
1048 // the fetch stage to stall. The pipeline will be drained once all
1049 // in-flight instructions have retired.
1050 commit.drain();
1051
1052 // Wake the CPU and record activity so everything can drain out if
1053 // the CPU was not able to immediately drain.
1054 if (!isDrained()) {
1055 // If a thread is suspended, wake it up so it can be drained
1056 for (auto t : threadContexts) {
1057 if (t->status() == ThreadContext::Suspended){
1058 DPRINTF(Drain, "Currently suspended so activate %i \n",
1059 t->threadId());
1060 t->activate();
1061 // As the thread is now active, change the power state as well
1062 activateContext(t->threadId());
1063 }
1064 }
1065
1066 wakeCPU();
1067 activityRec.activity();
1068
1069 DPRINTF(Drain, "CPU not drained\n");
1070
1071 return DrainState::Draining;
1072 } else {
1073 DPRINTF(Drain, "CPU is already drained\n");
1074 if (tickEvent.scheduled())
1075 deschedule(tickEvent);
1076
1077 // Flush out any old data from the time buffers. In
1078 // particular, there might be some data in flight from the
1079 // fetch stage that isn't visible in any of the CPU buffers we
1080 // test in isDrained().
1081 for (int i = 0; i < timeBuffer.getSize(); ++i) {
1082 timeBuffer.advance();
1083 fetchQueue.advance();
1084 decodeQueue.advance();
1085 renameQueue.advance();
1086 iewQueue.advance();
1087 }
1088
1089 drainSanityCheck();
1090 return DrainState::Drained;
1091 }
1092}
1093
1094template <class Impl>
1095bool
1096FullO3CPU<Impl>::tryDrain()
1097{
1098 if (drainState() != DrainState::Draining || !isDrained())
1099 return false;
1100
1101 if (tickEvent.scheduled())
1102 deschedule(tickEvent);
1103
1104 DPRINTF(Drain, "CPU done draining, processing drain event\n");
1105 signalDrainDone();
1106
1107 return true;
1108}
1109
1110template <class Impl>
1111void
1112FullO3CPU<Impl>::drainSanityCheck() const
1113{
1114 assert(isDrained());
1115 fetch.drainSanityCheck();
1116 decode.drainSanityCheck();
1117 rename.drainSanityCheck();
1118 iew.drainSanityCheck();
1119 commit.drainSanityCheck();
1120}
1121
1122template <class Impl>
1123bool
1124FullO3CPU<Impl>::isDrained() const
1125{
1126 bool drained(true);
1127
1128 if (!instList.empty() || !removeList.empty()) {
1129 DPRINTF(Drain, "Main CPU structures not drained.\n");
1130 drained = false;
1131 }
1132
1133 if (!fetch.isDrained()) {
1134 DPRINTF(Drain, "Fetch not drained.\n");
1135 drained = false;
1136 }
1137
1138 if (!decode.isDrained()) {
1139 DPRINTF(Drain, "Decode not drained.\n");
1140 drained = false;
1141 }
1142
1143 if (!rename.isDrained()) {
1144 DPRINTF(Drain, "Rename not drained.\n");
1145 drained = false;
1146 }
1147
1148 if (!iew.isDrained()) {
1149 DPRINTF(Drain, "IEW not drained.\n");
1150 drained = false;
1151 }
1152
1153 if (!commit.isDrained()) {
1154 DPRINTF(Drain, "Commit not drained.\n");
1155 drained = false;
1156 }
1157
1158 return drained;
1159}
1160
1161template <class Impl>
1162void
1163FullO3CPU<Impl>::commitDrained(ThreadID tid)
1164{
1165 fetch.drainStall(tid);
1166}
1167
1168template <class Impl>
1169void
1170FullO3CPU<Impl>::drainResume()
1171{
1172 if (switchedOut())
1173 return;
1174
1175 DPRINTF(Drain, "Resuming...\n");
1176 verifyMemoryMode();
1177
1178 fetch.drainResume();
1179 commit.drainResume();
1180
1181 _status = Idle;
1182 for (ThreadID i = 0; i < thread.size(); i++) {
1183 if (thread[i]->status() == ThreadContext::Active) {
1184 DPRINTF(Drain, "Activating thread: %i\n", i);
1185 activateThread(i);
1186 _status = Running;
1187 }
1188 }
1189
1190 assert(!tickEvent.scheduled());
1191 if (_status == Running)
1192 schedule(tickEvent, nextCycle());
1193
1194 // Reschedule any power gating event (if any)
1195 schedulePowerGatingEvent();
1196}
1197
1198template <class Impl>
1199void
1200FullO3CPU<Impl>::switchOut()
1201{
1202 DPRINTF(O3CPU, "Switching out\n");
1203 BaseCPU::switchOut();
1204
1205 activityRec.reset();
1206
1207 _status = SwitchedOut;
1208
1209 if (checker)
1210 checker->switchOut();
1211}
1212
1213template <class Impl>
1214void
1215FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
1216{
1217 BaseCPU::takeOverFrom(oldCPU);
1218
1219 fetch.takeOverFrom();
1220 decode.takeOverFrom();
1221 rename.takeOverFrom();
1222 iew.takeOverFrom();
1223 commit.takeOverFrom();
1224
1225 assert(!tickEvent.scheduled());
1226
1227 FullO3CPU<Impl> *oldO3CPU = dynamic_cast<FullO3CPU<Impl>*>(oldCPU);
1228 if (oldO3CPU)
1229 globalSeqNum = oldO3CPU->globalSeqNum;
1230
1231 lastRunningCycle = curCycle();
1232 _status = Idle;
1233}
1234
1235template <class Impl>
1236void
1237FullO3CPU<Impl>::verifyMemoryMode() const
1238{
1239 if (!system->isTimingMode()) {
1240 fatal("The O3 CPU requires the memory system to be in "
1241 "'timing' mode.\n");
1242 }
1243}
1244
1245template <class Impl>
1246RegVal
1247FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
1248{
1249 return this->isa[tid]->readMiscRegNoEffect(misc_reg);
1250}
1251
1252template <class Impl>
1253RegVal
1254FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
1255{
1256 miscRegfileReads++;
1257 return this->isa[tid]->readMiscReg(misc_reg, tcBase(tid));
1258}
1259
1260template <class Impl>
1261void
1262FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid)
1263{
1264 this->isa[tid]->setMiscRegNoEffect(misc_reg, val);
1265}
1266
1267template <class Impl>
1268void
1269FullO3CPU<Impl>::setMiscReg(int misc_reg, RegVal val, ThreadID tid)
1270{
1271 miscRegfileWrites++;
1272 this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid));
1273}
1274
1275template <class Impl>
1276RegVal
1277FullO3CPU<Impl>::readIntReg(PhysRegIdPtr phys_reg)
1278{
1279 intRegfileReads++;
1280 return regFile.readIntReg(phys_reg);
1281}
1282
1283template <class Impl>
1284RegVal
1285FullO3CPU<Impl>::readFloatRegBits(PhysRegIdPtr phys_reg)
1286{
1287 fpRegfileReads++;
1288 return regFile.readFloatRegBits(phys_reg);
1289}
1290
1291template <class Impl>
1292auto
1293FullO3CPU<Impl>::readVecReg(PhysRegIdPtr phys_reg) const
1294 -> const VecRegContainer&
1295{
1296 vecRegfileReads++;
1297 return regFile.readVecReg(phys_reg);
1298}
1299
1300template <class Impl>
1301auto
1302FullO3CPU<Impl>::getWritableVecReg(PhysRegIdPtr phys_reg)
1303 -> VecRegContainer&
1304{
1305 vecRegfileWrites++;
1306 return regFile.getWritableVecReg(phys_reg);
1307}
1308
1309template <class Impl>
1310auto
1311FullO3CPU<Impl>::readVecElem(PhysRegIdPtr phys_reg) const -> const VecElem&
1312{
1313 vecRegfileReads++;
1314 return regFile.readVecElem(phys_reg);
1315}
1316
1317template <class Impl>
1318CCReg
1319FullO3CPU<Impl>::readCCReg(PhysRegIdPtr phys_reg)
1320{
1321 ccRegfileReads++;
1322 return regFile.readCCReg(phys_reg);
1323}
1324
1325template <class Impl>
1326void
1327FullO3CPU<Impl>::setIntReg(PhysRegIdPtr phys_reg, RegVal val)
1328{
1329 intRegfileWrites++;
1330 regFile.setIntReg(phys_reg, val);
1331}
1332
1333template <class Impl>
1334void
1335FullO3CPU<Impl>::setFloatRegBits(PhysRegIdPtr phys_reg, RegVal val)
1336{
1337 fpRegfileWrites++;
1338 regFile.setFloatRegBits(phys_reg, val);
1339}
1340
1341template <class Impl>
1342void
1343FullO3CPU<Impl>::setVecReg(PhysRegIdPtr phys_reg, const VecRegContainer& val)
1344{
1345 vecRegfileWrites++;
1346 regFile.setVecReg(phys_reg, val);
1347}
1348
1349template <class Impl>
1350void
1351FullO3CPU<Impl>::setVecElem(PhysRegIdPtr phys_reg, const VecElem& val)
1352{
1353 vecRegfileWrites++;
1354 regFile.setVecElem(phys_reg, val);
1355}
1356
1357template <class Impl>
1358void
1359FullO3CPU<Impl>::setCCReg(PhysRegIdPtr phys_reg, CCReg val)
1360{
1361 ccRegfileWrites++;
1362 regFile.setCCReg(phys_reg, val);
1363}
1364
1365template <class Impl>
1366RegVal
1367FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1368{
1369 intRegfileReads++;
1370 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1371 RegId(IntRegClass, reg_idx));
1372
1373 return regFile.readIntReg(phys_reg);
1374}
1375
1376template <class Impl>
1377RegVal
1378FullO3CPU<Impl>::readArchFloatRegBits(int reg_idx, ThreadID tid)
1379{
1380 fpRegfileReads++;
1381 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1382 RegId(FloatRegClass, reg_idx));
1383
1384 return regFile.readFloatRegBits(phys_reg);
1385}
1386
1387template <class Impl>
1388auto
1389FullO3CPU<Impl>::readArchVecReg(int reg_idx, ThreadID tid) const
1390 -> const VecRegContainer&
1391{
1392 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1393 RegId(VecRegClass, reg_idx));
1394 return readVecReg(phys_reg);
1395}
1396
1397template <class Impl>
1398auto
1399FullO3CPU<Impl>::getWritableArchVecReg(int reg_idx, ThreadID tid)
1400 -> VecRegContainer&
1401{
1402 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1403 RegId(VecRegClass, reg_idx));
1404 return getWritableVecReg(phys_reg);
1405}
1406
1407template <class Impl>
1408auto
1409FullO3CPU<Impl>::readArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
1410 ThreadID tid) const -> const VecElem&
1411{
1412 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
| 1/*
2 * Copyright (c) 2011-2012, 2014, 2016, 2017 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * Copyright (c) 2011 Regents of the University of California
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Kevin Lim
43 * Korey Sewell
44 * Rick Strong
45 */
46
47#include "cpu/o3/cpu.hh"
48
49#include "arch/generic/traits.hh"
50#include "arch/kernel_stats.hh"
51#include "config/the_isa.hh"
52#include "cpu/activity.hh"
53#include "cpu/checker/cpu.hh"
54#include "cpu/checker/thread_context.hh"
55#include "cpu/o3/isa_specific.hh"
56#include "cpu/o3/thread_context.hh"
57#include "cpu/quiesce_event.hh"
58#include "cpu/simple_thread.hh"
59#include "cpu/thread_context.hh"
60#include "debug/Activity.hh"
61#include "debug/Drain.hh"
62#include "debug/O3CPU.hh"
63#include "debug/Quiesce.hh"
64#include "enums/MemoryMode.hh"
65#include "sim/core.hh"
66#include "sim/full_system.hh"
67#include "sim/process.hh"
68#include "sim/stat_control.hh"
69#include "sim/system.hh"
70
71#if THE_ISA == ALPHA_ISA
72#include "arch/alpha/osfpal.hh"
73#include "debug/Activity.hh"
74
75#endif
76
77struct BaseCPUParams;
78
79using namespace TheISA;
80using namespace std;
81
82BaseO3CPU::BaseO3CPU(BaseCPUParams *params)
83 : BaseCPU(params)
84{
85}
86
87void
88BaseO3CPU::regStats()
89{
90 BaseCPU::regStats();
91}
92
93template<class Impl>
94bool
95FullO3CPU<Impl>::IcachePort::recvTimingResp(PacketPtr pkt)
96{
97 DPRINTF(O3CPU, "Fetch unit received timing\n");
98 // We shouldn't ever get a cacheable block in Modified state
99 assert(pkt->req->isUncacheable() ||
100 !(pkt->cacheResponding() && !pkt->hasSharers()));
101 fetch->processCacheCompletion(pkt);
102
103 return true;
104}
105
106template<class Impl>
107void
108FullO3CPU<Impl>::IcachePort::recvReqRetry()
109{
110 fetch->recvReqRetry();
111}
112
113template <class Impl>
114bool
115FullO3CPU<Impl>::DcachePort::recvTimingResp(PacketPtr pkt)
116{
117 return lsq->recvTimingResp(pkt);
118}
119
120template <class Impl>
121void
122FullO3CPU<Impl>::DcachePort::recvTimingSnoopReq(PacketPtr pkt)
123{
124 for (ThreadID tid = 0; tid < cpu->numThreads; tid++) {
125 if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) {
126 cpu->wakeup(tid);
127 }
128 }
129 lsq->recvTimingSnoopReq(pkt);
130}
131
132template <class Impl>
133void
134FullO3CPU<Impl>::DcachePort::recvReqRetry()
135{
136 lsq->recvReqRetry();
137}
138
139template <class Impl>
140FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
141 : BaseO3CPU(params),
142 itb(params->itb),
143 dtb(params->dtb),
144 tickEvent([this]{ tick(); }, "FullO3CPU tick",
145 false, Event::CPU_Tick_Pri),
146#ifndef NDEBUG
147 instcount(0),
148#endif
149 removeInstsThisCycle(false),
150 fetch(this, params),
151 decode(this, params),
152 rename(this, params),
153 iew(this, params),
154 commit(this, params),
155
156 /* It is mandatory that all SMT threads use the same renaming mode as
157 * they are sharing registers and rename */
158 vecMode(initRenameMode<TheISA::ISA>::mode(params->isa[0])),
159 regFile(params->numPhysIntRegs,
160 params->numPhysFloatRegs,
161 params->numPhysVecRegs,
162 params->numPhysCCRegs,
163 vecMode),
164
165 freeList(name() + ".freelist", ®File),
166
167 rob(this, params),
168
169 scoreboard(name() + ".scoreboard",
170 regFile.totalNumPhysRegs()),
171
172 isa(numThreads, NULL),
173
174 icachePort(&fetch, this),
175 dcachePort(&iew.ldstQueue, this),
176
177 timeBuffer(params->backComSize, params->forwardComSize),
178 fetchQueue(params->backComSize, params->forwardComSize),
179 decodeQueue(params->backComSize, params->forwardComSize),
180 renameQueue(params->backComSize, params->forwardComSize),
181 iewQueue(params->backComSize, params->forwardComSize),
182 activityRec(name(), NumStages,
183 params->backComSize + params->forwardComSize,
184 params->activity),
185
186 globalSeqNum(1),
187 system(params->system),
188 lastRunningCycle(curCycle())
189{
190 if (!params->switched_out) {
191 _status = Running;
192 } else {
193 _status = SwitchedOut;
194 }
195
196 if (params->checker) {
197 BaseCPU *temp_checker = params->checker;
198 checker = dynamic_cast<Checker<Impl> *>(temp_checker);
199 checker->setIcachePort(&icachePort);
200 checker->setSystem(params->system);
201 } else {
202 checker = NULL;
203 }
204
205 if (!FullSystem) {
206 thread.resize(numThreads);
207 tids.resize(numThreads);
208 }
209
210 // The stages also need their CPU pointer setup. However this
211 // must be done at the upper level CPU because they have pointers
212 // to the upper level CPU, and not this FullO3CPU.
213
214 // Set up Pointers to the activeThreads list for each stage
215 fetch.setActiveThreads(&activeThreads);
216 decode.setActiveThreads(&activeThreads);
217 rename.setActiveThreads(&activeThreads);
218 iew.setActiveThreads(&activeThreads);
219 commit.setActiveThreads(&activeThreads);
220
221 // Give each of the stages the time buffer they will use.
222 fetch.setTimeBuffer(&timeBuffer);
223 decode.setTimeBuffer(&timeBuffer);
224 rename.setTimeBuffer(&timeBuffer);
225 iew.setTimeBuffer(&timeBuffer);
226 commit.setTimeBuffer(&timeBuffer);
227
228 // Also setup each of the stages' queues.
229 fetch.setFetchQueue(&fetchQueue);
230 decode.setFetchQueue(&fetchQueue);
231 commit.setFetchQueue(&fetchQueue);
232 decode.setDecodeQueue(&decodeQueue);
233 rename.setDecodeQueue(&decodeQueue);
234 rename.setRenameQueue(&renameQueue);
235 iew.setRenameQueue(&renameQueue);
236 iew.setIEWQueue(&iewQueue);
237 commit.setIEWQueue(&iewQueue);
238 commit.setRenameQueue(&renameQueue);
239
240 commit.setIEWStage(&iew);
241 rename.setIEWStage(&iew);
242 rename.setCommitStage(&commit);
243
244 ThreadID active_threads;
245 if (FullSystem) {
246 active_threads = 1;
247 } else {
248 active_threads = params->workload.size();
249
250 if (active_threads > Impl::MaxThreads) {
251 panic("Workload Size too large. Increase the 'MaxThreads' "
252 "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) "
253 "or edit your workload size.");
254 }
255 }
256
257 //Make Sure That this a Valid Architeture
258 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs);
259 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
260 assert(params->numPhysVecRegs >= numThreads * TheISA::NumVecRegs);
261 assert(params->numPhysCCRegs >= numThreads * TheISA::NumCCRegs);
262
263 rename.setScoreboard(&scoreboard);
264 iew.setScoreboard(&scoreboard);
265
266 // Setup the rename map for whichever stages need it.
267 for (ThreadID tid = 0; tid < numThreads; tid++) {
268 isa[tid] = params->isa[tid];
269 assert(initRenameMode<TheISA::ISA>::equals(isa[tid], isa[0]));
270
271 // Only Alpha has an FP zero register, so for other ISAs we
272 // use an invalid FP register index to avoid special treatment
273 // of any valid FP reg.
274 RegIndex invalidFPReg = TheISA::NumFloatRegs + 1;
275 RegIndex fpZeroReg =
276 (THE_ISA == ALPHA_ISA) ? TheISA::ZeroReg : invalidFPReg;
277
278 commitRenameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg,
279 &freeList,
280 vecMode);
281
282 renameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg,
283 &freeList, vecMode);
284 }
285
286 // Initialize rename map to assign physical registers to the
287 // architectural registers for active threads only.
288 for (ThreadID tid = 0; tid < active_threads; tid++) {
289 for (RegIndex ridx = 0; ridx < TheISA::NumIntRegs; ++ridx) {
290 // Note that we can't use the rename() method because we don't
291 // want special treatment for the zero register at this point
292 PhysRegIdPtr phys_reg = freeList.getIntReg();
293 renameMap[tid].setEntry(RegId(IntRegClass, ridx), phys_reg);
294 commitRenameMap[tid].setEntry(RegId(IntRegClass, ridx), phys_reg);
295 }
296
297 for (RegIndex ridx = 0; ridx < TheISA::NumFloatRegs; ++ridx) {
298 PhysRegIdPtr phys_reg = freeList.getFloatReg();
299 renameMap[tid].setEntry(RegId(FloatRegClass, ridx), phys_reg);
300 commitRenameMap[tid].setEntry(
301 RegId(FloatRegClass, ridx), phys_reg);
302 }
303
304 /* Here we need two 'interfaces' the 'whole register' and the
305 * 'register element'. At any point only one of them will be
306 * active. */
307 if (vecMode == Enums::Full) {
308 /* Initialize the full-vector interface */
309 for (RegIndex ridx = 0; ridx < TheISA::NumVecRegs; ++ridx) {
310 RegId rid = RegId(VecRegClass, ridx);
311 PhysRegIdPtr phys_reg = freeList.getVecReg();
312 renameMap[tid].setEntry(rid, phys_reg);
313 commitRenameMap[tid].setEntry(rid, phys_reg);
314 }
315 } else {
316 /* Initialize the vector-element interface */
317 for (RegIndex ridx = 0; ridx < TheISA::NumVecRegs; ++ridx) {
318 for (ElemIndex ldx = 0; ldx < TheISA::NumVecElemPerVecReg;
319 ++ldx) {
320 RegId lrid = RegId(VecElemClass, ridx, ldx);
321 PhysRegIdPtr phys_elem = freeList.getVecElem();
322 renameMap[tid].setEntry(lrid, phys_elem);
323 commitRenameMap[tid].setEntry(lrid, phys_elem);
324 }
325 }
326 }
327
328 for (RegIndex ridx = 0; ridx < TheISA::NumCCRegs; ++ridx) {
329 PhysRegIdPtr phys_reg = freeList.getCCReg();
330 renameMap[tid].setEntry(RegId(CCRegClass, ridx), phys_reg);
331 commitRenameMap[tid].setEntry(RegId(CCRegClass, ridx), phys_reg);
332 }
333 }
334
335 rename.setRenameMap(renameMap);
336 commit.setRenameMap(commitRenameMap);
337 rename.setFreeList(&freeList);
338
339 // Setup the ROB for whichever stages need it.
340 commit.setROB(&rob);
341
342 lastActivatedCycle = 0;
343#if 0
344 // Give renameMap & rename stage access to the freeList;
345 for (ThreadID tid = 0; tid < numThreads; tid++)
346 globalSeqNum[tid] = 1;
347#endif
348
349 DPRINTF(O3CPU, "Creating O3CPU object.\n");
350
351 // Setup any thread state.
352 this->thread.resize(this->numThreads);
353
354 for (ThreadID tid = 0; tid < this->numThreads; ++tid) {
355 if (FullSystem) {
356 // SMT is not supported in FS mode yet.
357 assert(this->numThreads == 1);
358 this->thread[tid] = new Thread(this, 0, NULL);
359 } else {
360 if (tid < params->workload.size()) {
361 DPRINTF(O3CPU, "Workload[%i] process is %#x",
362 tid, this->thread[tid]);
363 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
364 (typename Impl::O3CPU *)(this),
365 tid, params->workload[tid]);
366
367 //usedTids[tid] = true;
368 //threadMap[tid] = tid;
369 } else {
370 //Allocate Empty thread so M5 can use later
371 //when scheduling threads to CPU
372 Process* dummy_proc = NULL;
373
374 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
375 (typename Impl::O3CPU *)(this),
376 tid, dummy_proc);
377 //usedTids[tid] = false;
378 }
379 }
380
381 ThreadContext *tc;
382
383 // Setup the TC that will serve as the interface to the threads/CPU.
384 O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>;
385
386 tc = o3_tc;
387
388 // If we're using a checker, then the TC should be the
389 // CheckerThreadContext.
390 if (params->checker) {
391 tc = new CheckerThreadContext<O3ThreadContext<Impl> >(
392 o3_tc, this->checker);
393 }
394
395 o3_tc->cpu = (typename Impl::O3CPU *)(this);
396 assert(o3_tc->cpu);
397 o3_tc->thread = this->thread[tid];
398
399 // Setup quiesce event.
400 this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
401
402 // Give the thread the TC.
403 this->thread[tid]->tc = tc;
404
405 // Add the TC to the CPU's list of TC's.
406 this->threadContexts.push_back(tc);
407 }
408
409 // FullO3CPU always requires an interrupt controller.
410 if (!params->switched_out && interrupts.empty()) {
411 fatal("FullO3CPU %s has no interrupt controller.\n"
412 "Ensure createInterruptController() is called.\n", name());
413 }
414
415 for (ThreadID tid = 0; tid < this->numThreads; tid++)
416 this->thread[tid]->setFuncExeInst(0);
417}
418
419template <class Impl>
420FullO3CPU<Impl>::~FullO3CPU()
421{
422}
423
424template <class Impl>
425void
426FullO3CPU<Impl>::regProbePoints()
427{
428 BaseCPU::regProbePoints();
429
430 ppInstAccessComplete = new ProbePointArg<PacketPtr>(getProbeManager(), "InstAccessComplete");
431 ppDataAccessComplete = new ProbePointArg<std::pair<DynInstPtr, PacketPtr> >(getProbeManager(), "DataAccessComplete");
432
433 fetch.regProbePoints();
434 rename.regProbePoints();
435 iew.regProbePoints();
436 commit.regProbePoints();
437}
438
439template <class Impl>
440void
441FullO3CPU<Impl>::regStats()
442{
443 BaseO3CPU::regStats();
444
445 // Register any of the O3CPU's stats here.
446 timesIdled
447 .name(name() + ".timesIdled")
448 .desc("Number of times that the entire CPU went into an idle state and"
449 " unscheduled itself")
450 .prereq(timesIdled);
451
452 idleCycles
453 .name(name() + ".idleCycles")
454 .desc("Total number of cycles that the CPU has spent unscheduled due "
455 "to idling")
456 .prereq(idleCycles);
457
458 quiesceCycles
459 .name(name() + ".quiesceCycles")
460 .desc("Total number of cycles that CPU has spent quiesced or waiting "
461 "for an interrupt")
462 .prereq(quiesceCycles);
463
464 // Number of Instructions simulated
465 // --------------------------------
466 // Should probably be in Base CPU but need templated
467 // MaxThreads so put in here instead
468 committedInsts
469 .init(numThreads)
470 .name(name() + ".committedInsts")
471 .desc("Number of Instructions Simulated")
472 .flags(Stats::total);
473
474 committedOps
475 .init(numThreads)
476 .name(name() + ".committedOps")
477 .desc("Number of Ops (including micro ops) Simulated")
478 .flags(Stats::total);
479
480 cpi
481 .name(name() + ".cpi")
482 .desc("CPI: Cycles Per Instruction")
483 .precision(6);
484 cpi = numCycles / committedInsts;
485
486 totalCpi
487 .name(name() + ".cpi_total")
488 .desc("CPI: Total CPI of All Threads")
489 .precision(6);
490 totalCpi = numCycles / sum(committedInsts);
491
492 ipc
493 .name(name() + ".ipc")
494 .desc("IPC: Instructions Per Cycle")
495 .precision(6);
496 ipc = committedInsts / numCycles;
497
498 totalIpc
499 .name(name() + ".ipc_total")
500 .desc("IPC: Total IPC of All Threads")
501 .precision(6);
502 totalIpc = sum(committedInsts) / numCycles;
503
504 this->fetch.regStats();
505 this->decode.regStats();
506 this->rename.regStats();
507 this->iew.regStats();
508 this->commit.regStats();
509 this->rob.regStats();
510
511 intRegfileReads
512 .name(name() + ".int_regfile_reads")
513 .desc("number of integer regfile reads")
514 .prereq(intRegfileReads);
515
516 intRegfileWrites
517 .name(name() + ".int_regfile_writes")
518 .desc("number of integer regfile writes")
519 .prereq(intRegfileWrites);
520
521 fpRegfileReads
522 .name(name() + ".fp_regfile_reads")
523 .desc("number of floating regfile reads")
524 .prereq(fpRegfileReads);
525
526 fpRegfileWrites
527 .name(name() + ".fp_regfile_writes")
528 .desc("number of floating regfile writes")
529 .prereq(fpRegfileWrites);
530
531 vecRegfileReads
532 .name(name() + ".vec_regfile_reads")
533 .desc("number of vector regfile reads")
534 .prereq(vecRegfileReads);
535
536 vecRegfileWrites
537 .name(name() + ".vec_regfile_writes")
538 .desc("number of vector regfile writes")
539 .prereq(vecRegfileWrites);
540
541 ccRegfileReads
542 .name(name() + ".cc_regfile_reads")
543 .desc("number of cc regfile reads")
544 .prereq(ccRegfileReads);
545
546 ccRegfileWrites
547 .name(name() + ".cc_regfile_writes")
548 .desc("number of cc regfile writes")
549 .prereq(ccRegfileWrites);
550
551 miscRegfileReads
552 .name(name() + ".misc_regfile_reads")
553 .desc("number of misc regfile reads")
554 .prereq(miscRegfileReads);
555
556 miscRegfileWrites
557 .name(name() + ".misc_regfile_writes")
558 .desc("number of misc regfile writes")
559 .prereq(miscRegfileWrites);
560}
561
562template <class Impl>
563void
564FullO3CPU<Impl>::tick()
565{
566 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
567 assert(!switchedOut());
568 assert(drainState() != DrainState::Drained);
569
570 ++numCycles;
571 updateCycleCounters(BaseCPU::CPU_STATE_ON);
572
573// activity = false;
574
575 //Tick each of the stages
576 fetch.tick();
577
578 decode.tick();
579
580 rename.tick();
581
582 iew.tick();
583
584 commit.tick();
585
586 // Now advance the time buffers
587 timeBuffer.advance();
588
589 fetchQueue.advance();
590 decodeQueue.advance();
591 renameQueue.advance();
592 iewQueue.advance();
593
594 activityRec.advance();
595
596 if (removeInstsThisCycle) {
597 cleanUpRemovedInsts();
598 }
599
600 if (!tickEvent.scheduled()) {
601 if (_status == SwitchedOut) {
602 DPRINTF(O3CPU, "Switched out!\n");
603 // increment stat
604 lastRunningCycle = curCycle();
605 } else if (!activityRec.active() || _status == Idle) {
606 DPRINTF(O3CPU, "Idle!\n");
607 lastRunningCycle = curCycle();
608 timesIdled++;
609 } else {
610 schedule(tickEvent, clockEdge(Cycles(1)));
611 DPRINTF(O3CPU, "Scheduling next tick!\n");
612 }
613 }
614
615 if (!FullSystem)
616 updateThreadPriority();
617
618 tryDrain();
619}
620
621template <class Impl>
622void
623FullO3CPU<Impl>::init()
624{
625 BaseCPU::init();
626
627 for (ThreadID tid = 0; tid < numThreads; ++tid) {
628 // Set noSquashFromTC so that the CPU doesn't squash when initially
629 // setting up registers.
630 thread[tid]->noSquashFromTC = true;
631 // Initialise the ThreadContext's memory proxies
632 thread[tid]->initMemProxies(thread[tid]->getTC());
633 }
634
635 if (FullSystem && !params()->switched_out) {
636 for (ThreadID tid = 0; tid < numThreads; tid++) {
637 ThreadContext *src_tc = threadContexts[tid];
638 TheISA::initCPU(src_tc, src_tc->contextId());
639 }
640 }
641
642 // Clear noSquashFromTC.
643 for (int tid = 0; tid < numThreads; ++tid)
644 thread[tid]->noSquashFromTC = false;
645
646 commit.setThreads(thread);
647}
648
649template <class Impl>
650void
651FullO3CPU<Impl>::startup()
652{
653 BaseCPU::startup();
654 for (int tid = 0; tid < numThreads; ++tid)
655 isa[tid]->startup(threadContexts[tid]);
656
657 fetch.startupStage();
658 decode.startupStage();
659 iew.startupStage();
660 rename.startupStage();
661 commit.startupStage();
662}
663
664template <class Impl>
665void
666FullO3CPU<Impl>::activateThread(ThreadID tid)
667{
668 list<ThreadID>::iterator isActive =
669 std::find(activeThreads.begin(), activeThreads.end(), tid);
670
671 DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid);
672 assert(!switchedOut());
673
674 if (isActive == activeThreads.end()) {
675 DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n",
676 tid);
677
678 activeThreads.push_back(tid);
679 }
680}
681
682template <class Impl>
683void
684FullO3CPU<Impl>::deactivateThread(ThreadID tid)
685{
686 //Remove From Active List, if Active
687 list<ThreadID>::iterator thread_it =
688 std::find(activeThreads.begin(), activeThreads.end(), tid);
689
690 DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid);
691 assert(!switchedOut());
692
693 if (thread_it != activeThreads.end()) {
694 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
695 tid);
696 activeThreads.erase(thread_it);
697 }
698
699 fetch.deactivateThread(tid);
700 commit.deactivateThread(tid);
701}
702
703template <class Impl>
704Counter
705FullO3CPU<Impl>::totalInsts() const
706{
707 Counter total(0);
708
709 ThreadID size = thread.size();
710 for (ThreadID i = 0; i < size; i++)
711 total += thread[i]->numInst;
712
713 return total;
714}
715
716template <class Impl>
717Counter
718FullO3CPU<Impl>::totalOps() const
719{
720 Counter total(0);
721
722 ThreadID size = thread.size();
723 for (ThreadID i = 0; i < size; i++)
724 total += thread[i]->numOp;
725
726 return total;
727}
728
729template <class Impl>
730void
731FullO3CPU<Impl>::activateContext(ThreadID tid)
732{
733 assert(!switchedOut());
734
735 // Needs to set each stage to running as well.
736 activateThread(tid);
737
738 // We don't want to wake the CPU if it is drained. In that case,
739 // we just want to flag the thread as active and schedule the tick
740 // event from drainResume() instead.
741 if (drainState() == DrainState::Drained)
742 return;
743
744 // If we are time 0 or if the last activation time is in the past,
745 // schedule the next tick and wake up the fetch unit
746 if (lastActivatedCycle == 0 || lastActivatedCycle < curTick()) {
747 scheduleTickEvent(Cycles(0));
748
749 // Be sure to signal that there's some activity so the CPU doesn't
750 // deschedule itself.
751 activityRec.activity();
752 fetch.wakeFromQuiesce();
753
754 Cycles cycles(curCycle() - lastRunningCycle);
755 // @todo: This is an oddity that is only here to match the stats
756 if (cycles != 0)
757 --cycles;
758 quiesceCycles += cycles;
759
760 lastActivatedCycle = curTick();
761
762 _status = Running;
763
764 BaseCPU::activateContext(tid);
765 }
766}
767
768template <class Impl>
769void
770FullO3CPU<Impl>::suspendContext(ThreadID tid)
771{
772 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
773 assert(!switchedOut());
774
775 deactivateThread(tid);
776
777 // If this was the last thread then unschedule the tick event.
778 if (activeThreads.size() == 0) {
779 unscheduleTickEvent();
780 lastRunningCycle = curCycle();
781 _status = Idle;
782 }
783
784 DPRINTF(Quiesce, "Suspending Context\n");
785
786 BaseCPU::suspendContext(tid);
787}
788
789template <class Impl>
790void
791FullO3CPU<Impl>::haltContext(ThreadID tid)
792{
793 //For now, this is the same as deallocate
794 DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
795 assert(!switchedOut());
796
797 deactivateThread(tid);
798 removeThread(tid);
799
800 updateCycleCounters(BaseCPU::CPU_STATE_SLEEP);
801}
802
803template <class Impl>
804void
805FullO3CPU<Impl>::insertThread(ThreadID tid)
806{
807 DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
808 // Will change now that the PC and thread state is internal to the CPU
809 // and not in the ThreadContext.
810 ThreadContext *src_tc;
811 if (FullSystem)
812 src_tc = system->threadContexts[tid];
813 else
814 src_tc = tcBase(tid);
815
816 //Bind Int Regs to Rename Map
817
818 for (RegId reg_id(IntRegClass, 0); reg_id.index() < TheISA::NumIntRegs;
819 reg_id.index()++) {
820 PhysRegIdPtr phys_reg = freeList.getIntReg();
821 renameMap[tid].setEntry(reg_id, phys_reg);
822 scoreboard.setReg(phys_reg);
823 }
824
825 //Bind Float Regs to Rename Map
826 for (RegId reg_id(FloatRegClass, 0); reg_id.index() < TheISA::NumFloatRegs;
827 reg_id.index()++) {
828 PhysRegIdPtr phys_reg = freeList.getFloatReg();
829 renameMap[tid].setEntry(reg_id, phys_reg);
830 scoreboard.setReg(phys_reg);
831 }
832
833 //Bind condition-code Regs to Rename Map
834 for (RegId reg_id(CCRegClass, 0); reg_id.index() < TheISA::NumCCRegs;
835 reg_id.index()++) {
836 PhysRegIdPtr phys_reg = freeList.getCCReg();
837 renameMap[tid].setEntry(reg_id, phys_reg);
838 scoreboard.setReg(phys_reg);
839 }
840
841 //Copy Thread Data Into RegFile
842 //this->copyFromTC(tid);
843
844 //Set PC/NPC/NNPC
845 pcState(src_tc->pcState(), tid);
846
847 src_tc->setStatus(ThreadContext::Active);
848
849 activateContext(tid);
850
851 //Reset ROB/IQ/LSQ Entries
852 commit.rob->resetEntries();
853}
854
855template <class Impl>
856void
857FullO3CPU<Impl>::removeThread(ThreadID tid)
858{
859 DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
860
861 // Copy Thread Data From RegFile
862 // If thread is suspended, it might be re-allocated
863 // this->copyToTC(tid);
864
865
866 // @todo: 2-27-2008: Fix how we free up rename mappings
867 // here to alleviate the case for double-freeing registers
868 // in SMT workloads.
869
870 // Unbind Int Regs from Rename Map
871 for (RegId reg_id(IntRegClass, 0); reg_id.index() < TheISA::NumIntRegs;
872 reg_id.index()++) {
873 PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id);
874 scoreboard.unsetReg(phys_reg);
875 freeList.addReg(phys_reg);
876 }
877
878 // Unbind Float Regs from Rename Map
879 for (RegId reg_id(FloatRegClass, 0); reg_id.index() < TheISA::NumFloatRegs;
880 reg_id.index()++) {
881 PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id);
882 scoreboard.unsetReg(phys_reg);
883 freeList.addReg(phys_reg);
884 }
885
886 // Unbind condition-code Regs from Rename Map
887 for (RegId reg_id(CCRegClass, 0); reg_id.index() < TheISA::NumCCRegs;
888 reg_id.index()++) {
889 PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id);
890 scoreboard.unsetReg(phys_reg);
891 freeList.addReg(phys_reg);
892 }
893
894 // Squash Throughout Pipeline
895 DynInstPtr inst = commit.rob->readHeadInst(tid);
896 InstSeqNum squash_seq_num = inst->seqNum;
897 fetch.squash(0, squash_seq_num, inst, tid);
898 decode.squash(tid);
899 rename.squash(squash_seq_num, tid);
900 iew.squash(tid);
901 iew.ldstQueue.squash(squash_seq_num, tid);
902 commit.rob->squash(squash_seq_num, tid);
903
904
905 assert(iew.instQueue.getCount(tid) == 0);
906 assert(iew.ldstQueue.getCount(tid) == 0);
907
908 // Reset ROB/IQ/LSQ Entries
909
910 // Commented out for now. This should be possible to do by
911 // telling all the pipeline stages to drain first, and then
912 // checking until the drain completes. Once the pipeline is
913 // drained, call resetEntries(). - 10-09-06 ktlim
914/*
915 if (activeThreads.size() >= 1) {
916 commit.rob->resetEntries();
917 iew.resetEntries();
918 }
919*/
920}
921
922template <class Impl>
923Fault
924FullO3CPU<Impl>::hwrei(ThreadID tid)
925{
926#if THE_ISA == ALPHA_ISA
927 // Need to clear the lock flag upon returning from an interrupt.
928 this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
929
930 this->thread[tid]->kernelStats->hwrei();
931
932 // FIXME: XXX check for interrupts? XXX
933#endif
934 return NoFault;
935}
936
937template <class Impl>
938bool
939FullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid)
940{
941#if THE_ISA == ALPHA_ISA
942 if (this->thread[tid]->kernelStats)
943 this->thread[tid]->kernelStats->callpal(palFunc,
944 this->threadContexts[tid]);
945
946 switch (palFunc) {
947 case PAL::halt:
948 halt();
949 if (--System::numSystemsRunning == 0)
950 exitSimLoop("all cpus halted");
951 break;
952
953 case PAL::bpt:
954 case PAL::bugchk:
955 if (this->system->breakpoint())
956 return false;
957 break;
958 }
959#endif
960 return true;
961}
962
963template <class Impl>
964Fault
965FullO3CPU<Impl>::getInterrupts()
966{
967 // Check if there are any outstanding interrupts
968 return this->interrupts[0]->getInterrupt(this->threadContexts[0]);
969}
970
971template <class Impl>
972void
973FullO3CPU<Impl>::processInterrupts(const Fault &interrupt)
974{
975 // Check for interrupts here. For now can copy the code that
976 // exists within isa_fullsys_traits.hh. Also assume that thread 0
977 // is the one that handles the interrupts.
978 // @todo: Possibly consolidate the interrupt checking code.
979 // @todo: Allow other threads to handle interrupts.
980
981 assert(interrupt != NoFault);
982 this->interrupts[0]->updateIntrInfo(this->threadContexts[0]);
983
984 DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
985 this->trap(interrupt, 0, nullptr);
986}
987
988template <class Impl>
989void
990FullO3CPU<Impl>::trap(const Fault &fault, ThreadID tid,
991 const StaticInstPtr &inst)
992{
993 // Pass the thread's TC into the invoke method.
994 fault->invoke(this->threadContexts[tid], inst);
995}
996
997template <class Impl>
998void
999FullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid, Fault *fault)
1000{
1001 DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid);
1002
1003 DPRINTF(Activity,"Activity: syscall() called.\n");
1004
1005 // Temporarily increase this by one to account for the syscall
1006 // instruction.
1007 ++(this->thread[tid]->funcExeInst);
1008
1009 // Execute the actual syscall.
1010 this->thread[tid]->syscall(callnum, fault);
1011
1012 // Decrease funcExeInst by one as the normal commit will handle
1013 // incrementing it.
1014 --(this->thread[tid]->funcExeInst);
1015}
1016
1017template <class Impl>
1018void
1019FullO3CPU<Impl>::serializeThread(CheckpointOut &cp, ThreadID tid) const
1020{
1021 thread[tid]->serialize(cp);
1022}
1023
1024template <class Impl>
1025void
1026FullO3CPU<Impl>::unserializeThread(CheckpointIn &cp, ThreadID tid)
1027{
1028 thread[tid]->unserialize(cp);
1029}
1030
1031template <class Impl>
1032DrainState
1033FullO3CPU<Impl>::drain()
1034{
1035 // Deschedule any power gating event (if any)
1036 deschedulePowerGatingEvent();
1037
1038 // If the CPU isn't doing anything, then return immediately.
1039 if (switchedOut())
1040 return DrainState::Drained;
1041
1042 DPRINTF(Drain, "Draining...\n");
1043
1044 // We only need to signal a drain to the commit stage as this
1045 // initiates squashing controls the draining. Once the commit
1046 // stage commits an instruction where it is safe to stop, it'll
1047 // squash the rest of the instructions in the pipeline and force
1048 // the fetch stage to stall. The pipeline will be drained once all
1049 // in-flight instructions have retired.
1050 commit.drain();
1051
1052 // Wake the CPU and record activity so everything can drain out if
1053 // the CPU was not able to immediately drain.
1054 if (!isDrained()) {
1055 // If a thread is suspended, wake it up so it can be drained
1056 for (auto t : threadContexts) {
1057 if (t->status() == ThreadContext::Suspended){
1058 DPRINTF(Drain, "Currently suspended so activate %i \n",
1059 t->threadId());
1060 t->activate();
1061 // As the thread is now active, change the power state as well
1062 activateContext(t->threadId());
1063 }
1064 }
1065
1066 wakeCPU();
1067 activityRec.activity();
1068
1069 DPRINTF(Drain, "CPU not drained\n");
1070
1071 return DrainState::Draining;
1072 } else {
1073 DPRINTF(Drain, "CPU is already drained\n");
1074 if (tickEvent.scheduled())
1075 deschedule(tickEvent);
1076
1077 // Flush out any old data from the time buffers. In
1078 // particular, there might be some data in flight from the
1079 // fetch stage that isn't visible in any of the CPU buffers we
1080 // test in isDrained().
1081 for (int i = 0; i < timeBuffer.getSize(); ++i) {
1082 timeBuffer.advance();
1083 fetchQueue.advance();
1084 decodeQueue.advance();
1085 renameQueue.advance();
1086 iewQueue.advance();
1087 }
1088
1089 drainSanityCheck();
1090 return DrainState::Drained;
1091 }
1092}
1093
1094template <class Impl>
1095bool
1096FullO3CPU<Impl>::tryDrain()
1097{
1098 if (drainState() != DrainState::Draining || !isDrained())
1099 return false;
1100
1101 if (tickEvent.scheduled())
1102 deschedule(tickEvent);
1103
1104 DPRINTF(Drain, "CPU done draining, processing drain event\n");
1105 signalDrainDone();
1106
1107 return true;
1108}
1109
1110template <class Impl>
1111void
1112FullO3CPU<Impl>::drainSanityCheck() const
1113{
1114 assert(isDrained());
1115 fetch.drainSanityCheck();
1116 decode.drainSanityCheck();
1117 rename.drainSanityCheck();
1118 iew.drainSanityCheck();
1119 commit.drainSanityCheck();
1120}
1121
1122template <class Impl>
1123bool
1124FullO3CPU<Impl>::isDrained() const
1125{
1126 bool drained(true);
1127
1128 if (!instList.empty() || !removeList.empty()) {
1129 DPRINTF(Drain, "Main CPU structures not drained.\n");
1130 drained = false;
1131 }
1132
1133 if (!fetch.isDrained()) {
1134 DPRINTF(Drain, "Fetch not drained.\n");
1135 drained = false;
1136 }
1137
1138 if (!decode.isDrained()) {
1139 DPRINTF(Drain, "Decode not drained.\n");
1140 drained = false;
1141 }
1142
1143 if (!rename.isDrained()) {
1144 DPRINTF(Drain, "Rename not drained.\n");
1145 drained = false;
1146 }
1147
1148 if (!iew.isDrained()) {
1149 DPRINTF(Drain, "IEW not drained.\n");
1150 drained = false;
1151 }
1152
1153 if (!commit.isDrained()) {
1154 DPRINTF(Drain, "Commit not drained.\n");
1155 drained = false;
1156 }
1157
1158 return drained;
1159}
1160
1161template <class Impl>
1162void
1163FullO3CPU<Impl>::commitDrained(ThreadID tid)
1164{
1165 fetch.drainStall(tid);
1166}
1167
1168template <class Impl>
1169void
1170FullO3CPU<Impl>::drainResume()
1171{
1172 if (switchedOut())
1173 return;
1174
1175 DPRINTF(Drain, "Resuming...\n");
1176 verifyMemoryMode();
1177
1178 fetch.drainResume();
1179 commit.drainResume();
1180
1181 _status = Idle;
1182 for (ThreadID i = 0; i < thread.size(); i++) {
1183 if (thread[i]->status() == ThreadContext::Active) {
1184 DPRINTF(Drain, "Activating thread: %i\n", i);
1185 activateThread(i);
1186 _status = Running;
1187 }
1188 }
1189
1190 assert(!tickEvent.scheduled());
1191 if (_status == Running)
1192 schedule(tickEvent, nextCycle());
1193
1194 // Reschedule any power gating event (if any)
1195 schedulePowerGatingEvent();
1196}
1197
1198template <class Impl>
1199void
1200FullO3CPU<Impl>::switchOut()
1201{
1202 DPRINTF(O3CPU, "Switching out\n");
1203 BaseCPU::switchOut();
1204
1205 activityRec.reset();
1206
1207 _status = SwitchedOut;
1208
1209 if (checker)
1210 checker->switchOut();
1211}
1212
1213template <class Impl>
1214void
1215FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
1216{
1217 BaseCPU::takeOverFrom(oldCPU);
1218
1219 fetch.takeOverFrom();
1220 decode.takeOverFrom();
1221 rename.takeOverFrom();
1222 iew.takeOverFrom();
1223 commit.takeOverFrom();
1224
1225 assert(!tickEvent.scheduled());
1226
1227 FullO3CPU<Impl> *oldO3CPU = dynamic_cast<FullO3CPU<Impl>*>(oldCPU);
1228 if (oldO3CPU)
1229 globalSeqNum = oldO3CPU->globalSeqNum;
1230
1231 lastRunningCycle = curCycle();
1232 _status = Idle;
1233}
1234
1235template <class Impl>
1236void
1237FullO3CPU<Impl>::verifyMemoryMode() const
1238{
1239 if (!system->isTimingMode()) {
1240 fatal("The O3 CPU requires the memory system to be in "
1241 "'timing' mode.\n");
1242 }
1243}
1244
1245template <class Impl>
1246RegVal
1247FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
1248{
1249 return this->isa[tid]->readMiscRegNoEffect(misc_reg);
1250}
1251
1252template <class Impl>
1253RegVal
1254FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
1255{
1256 miscRegfileReads++;
1257 return this->isa[tid]->readMiscReg(misc_reg, tcBase(tid));
1258}
1259
1260template <class Impl>
1261void
1262FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid)
1263{
1264 this->isa[tid]->setMiscRegNoEffect(misc_reg, val);
1265}
1266
1267template <class Impl>
1268void
1269FullO3CPU<Impl>::setMiscReg(int misc_reg, RegVal val, ThreadID tid)
1270{
1271 miscRegfileWrites++;
1272 this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid));
1273}
1274
1275template <class Impl>
1276RegVal
1277FullO3CPU<Impl>::readIntReg(PhysRegIdPtr phys_reg)
1278{
1279 intRegfileReads++;
1280 return regFile.readIntReg(phys_reg);
1281}
1282
1283template <class Impl>
1284RegVal
1285FullO3CPU<Impl>::readFloatRegBits(PhysRegIdPtr phys_reg)
1286{
1287 fpRegfileReads++;
1288 return regFile.readFloatRegBits(phys_reg);
1289}
1290
1291template <class Impl>
1292auto
1293FullO3CPU<Impl>::readVecReg(PhysRegIdPtr phys_reg) const
1294 -> const VecRegContainer&
1295{
1296 vecRegfileReads++;
1297 return regFile.readVecReg(phys_reg);
1298}
1299
1300template <class Impl>
1301auto
1302FullO3CPU<Impl>::getWritableVecReg(PhysRegIdPtr phys_reg)
1303 -> VecRegContainer&
1304{
1305 vecRegfileWrites++;
1306 return regFile.getWritableVecReg(phys_reg);
1307}
1308
1309template <class Impl>
1310auto
1311FullO3CPU<Impl>::readVecElem(PhysRegIdPtr phys_reg) const -> const VecElem&
1312{
1313 vecRegfileReads++;
1314 return regFile.readVecElem(phys_reg);
1315}
1316
1317template <class Impl>
1318CCReg
1319FullO3CPU<Impl>::readCCReg(PhysRegIdPtr phys_reg)
1320{
1321 ccRegfileReads++;
1322 return regFile.readCCReg(phys_reg);
1323}
1324
1325template <class Impl>
1326void
1327FullO3CPU<Impl>::setIntReg(PhysRegIdPtr phys_reg, RegVal val)
1328{
1329 intRegfileWrites++;
1330 regFile.setIntReg(phys_reg, val);
1331}
1332
1333template <class Impl>
1334void
1335FullO3CPU<Impl>::setFloatRegBits(PhysRegIdPtr phys_reg, RegVal val)
1336{
1337 fpRegfileWrites++;
1338 regFile.setFloatRegBits(phys_reg, val);
1339}
1340
1341template <class Impl>
1342void
1343FullO3CPU<Impl>::setVecReg(PhysRegIdPtr phys_reg, const VecRegContainer& val)
1344{
1345 vecRegfileWrites++;
1346 regFile.setVecReg(phys_reg, val);
1347}
1348
1349template <class Impl>
1350void
1351FullO3CPU<Impl>::setVecElem(PhysRegIdPtr phys_reg, const VecElem& val)
1352{
1353 vecRegfileWrites++;
1354 regFile.setVecElem(phys_reg, val);
1355}
1356
1357template <class Impl>
1358void
1359FullO3CPU<Impl>::setCCReg(PhysRegIdPtr phys_reg, CCReg val)
1360{
1361 ccRegfileWrites++;
1362 regFile.setCCReg(phys_reg, val);
1363}
1364
1365template <class Impl>
1366RegVal
1367FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1368{
1369 intRegfileReads++;
1370 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1371 RegId(IntRegClass, reg_idx));
1372
1373 return regFile.readIntReg(phys_reg);
1374}
1375
1376template <class Impl>
1377RegVal
1378FullO3CPU<Impl>::readArchFloatRegBits(int reg_idx, ThreadID tid)
1379{
1380 fpRegfileReads++;
1381 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1382 RegId(FloatRegClass, reg_idx));
1383
1384 return regFile.readFloatRegBits(phys_reg);
1385}
1386
1387template <class Impl>
1388auto
1389FullO3CPU<Impl>::readArchVecReg(int reg_idx, ThreadID tid) const
1390 -> const VecRegContainer&
1391{
1392 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1393 RegId(VecRegClass, reg_idx));
1394 return readVecReg(phys_reg);
1395}
1396
1397template <class Impl>
1398auto
1399FullO3CPU<Impl>::getWritableArchVecReg(int reg_idx, ThreadID tid)
1400 -> VecRegContainer&
1401{
1402 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1403 RegId(VecRegClass, reg_idx));
1404 return getWritableVecReg(phys_reg);
1405}
1406
1407template <class Impl>
1408auto
1409FullO3CPU<Impl>::readArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
1410 ThreadID tid) const -> const VecElem&
1411{
1412 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
|
1414 return readVecElem(phys_reg);
1415}
1416
1417template <class Impl>
1418CCReg
1419FullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid)
1420{
1421 ccRegfileReads++;
1422 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1423 RegId(CCRegClass, reg_idx));
1424
1425 return regFile.readCCReg(phys_reg);
1426}
1427
1428template <class Impl>
1429void
1430FullO3CPU<Impl>::setArchIntReg(int reg_idx, RegVal val, ThreadID tid)
1431{
1432 intRegfileWrites++;
1433 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1434 RegId(IntRegClass, reg_idx));
1435
1436 regFile.setIntReg(phys_reg, val);
1437}
1438
1439template <class Impl>
1440void
1441FullO3CPU<Impl>::setArchFloatRegBits(int reg_idx, RegVal val, ThreadID tid)
1442{
1443 fpRegfileWrites++;
1444 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1445 RegId(FloatRegClass, reg_idx));
1446
1447 regFile.setFloatRegBits(phys_reg, val);
1448}
1449
1450template <class Impl>
1451void
1452FullO3CPU<Impl>::setArchVecReg(int reg_idx, const VecRegContainer& val,
1453 ThreadID tid)
1454{
1455 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1456 RegId(VecRegClass, reg_idx));
1457 setVecReg(phys_reg, val);
1458}
1459
1460template <class Impl>
1461void
1462FullO3CPU<Impl>::setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
1463 const VecElem& val, ThreadID tid)
1464{
1465 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1466 RegId(VecElemClass, reg_idx, ldx));
1467 setVecElem(phys_reg, val);
1468}
1469
1470template <class Impl>
1471void
1472FullO3CPU<Impl>::setArchCCReg(int reg_idx, CCReg val, ThreadID tid)
1473{
1474 ccRegfileWrites++;
1475 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1476 RegId(CCRegClass, reg_idx));
1477
1478 regFile.setCCReg(phys_reg, val);
1479}
1480
1481template <class Impl>
1482TheISA::PCState
1483FullO3CPU<Impl>::pcState(ThreadID tid)
1484{
1485 return commit.pcState(tid);
1486}
1487
1488template <class Impl>
1489void
1490FullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid)
1491{
1492 commit.pcState(val, tid);
1493}
1494
1495template <class Impl>
1496Addr
1497FullO3CPU<Impl>::instAddr(ThreadID tid)
1498{
1499 return commit.instAddr(tid);
1500}
1501
1502template <class Impl>
1503Addr
1504FullO3CPU<Impl>::nextInstAddr(ThreadID tid)
1505{
1506 return commit.nextInstAddr(tid);
1507}
1508
1509template <class Impl>
1510MicroPC
1511FullO3CPU<Impl>::microPC(ThreadID tid)
1512{
1513 return commit.microPC(tid);
1514}
1515
1516template <class Impl>
1517void
1518FullO3CPU<Impl>::squashFromTC(ThreadID tid)
1519{
1520 this->thread[tid]->noSquashFromTC = true;
1521 this->commit.generateTCEvent(tid);
1522}
1523
1524template <class Impl>
1525typename FullO3CPU<Impl>::ListIt
1526FullO3CPU<Impl>::addInst(const DynInstPtr &inst)
1527{
1528 instList.push_back(inst);
1529
1530 return --(instList.end());
1531}
1532
1533template <class Impl>
1534void
1535FullO3CPU<Impl>::instDone(ThreadID tid, const DynInstPtr &inst)
1536{
1537 // Keep an instruction count.
1538 if (!inst->isMicroop() || inst->isLastMicroop()) {
1539 thread[tid]->numInst++;
1540 thread[tid]->numInsts++;
1541 committedInsts[tid]++;
1542 system->totalNumInsts++;
1543
1544 // Check for instruction-count-based events.
1545 comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1546 system->instEventQueue.serviceEvents(system->totalNumInsts);
1547 }
1548 thread[tid]->numOp++;
1549 thread[tid]->numOps++;
1550 committedOps[tid]++;
1551
1552 probeInstCommit(inst->staticInst);
1553}
1554
1555template <class Impl>
1556void
1557FullO3CPU<Impl>::removeFrontInst(const DynInstPtr &inst)
1558{
1559 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s "
1560 "[sn:%lli]\n",
1561 inst->threadNumber, inst->pcState(), inst->seqNum);
1562
1563 removeInstsThisCycle = true;
1564
1565 // Remove the front instruction.
1566 removeList.push(inst->getInstListIt());
1567}
1568
1569template <class Impl>
1570void
1571FullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid)
1572{
1573 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1574 " list.\n", tid);
1575
1576 ListIt end_it;
1577
1578 bool rob_empty = false;
1579
1580 if (instList.empty()) {
1581 return;
1582 } else if (rob.isEmpty(tid)) {
1583 DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1584 end_it = instList.begin();
1585 rob_empty = true;
1586 } else {
1587 end_it = (rob.readTailInst(tid))->getInstListIt();
1588 DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1589 }
1590
1591 removeInstsThisCycle = true;
1592
1593 ListIt inst_it = instList.end();
1594
1595 inst_it--;
1596
1597 // Walk through the instruction list, removing any instructions
1598 // that were inserted after the given instruction iterator, end_it.
1599 while (inst_it != end_it) {
1600 assert(!instList.empty());
1601
1602 squashInstIt(inst_it, tid);
1603
1604 inst_it--;
1605 }
1606
1607 // If the ROB was empty, then we actually need to remove the first
1608 // instruction as well.
1609 if (rob_empty) {
1610 squashInstIt(inst_it, tid);
1611 }
1612}
1613
1614template <class Impl>
1615void
1616FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1617{
1618 assert(!instList.empty());
1619
1620 removeInstsThisCycle = true;
1621
1622 ListIt inst_iter = instList.end();
1623
1624 inst_iter--;
1625
1626 DPRINTF(O3CPU, "Deleting instructions from instruction "
1627 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1628 tid, seq_num, (*inst_iter)->seqNum);
1629
1630 while ((*inst_iter)->seqNum > seq_num) {
1631
1632 bool break_loop = (inst_iter == instList.begin());
1633
1634 squashInstIt(inst_iter, tid);
1635
1636 inst_iter--;
1637
1638 if (break_loop)
1639 break;
1640 }
1641}
1642
1643template <class Impl>
1644inline void
1645FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid)
1646{
1647 if ((*instIt)->threadNumber == tid) {
1648 DPRINTF(O3CPU, "Squashing instruction, "
1649 "[tid:%i] [sn:%lli] PC %s\n",
1650 (*instIt)->threadNumber,
1651 (*instIt)->seqNum,
1652 (*instIt)->pcState());
1653
1654 // Mark it as squashed.
1655 (*instIt)->setSquashed();
1656
1657 // @todo: Formulate a consistent method for deleting
1658 // instructions from the instruction list
1659 // Remove the instruction from the list.
1660 removeList.push(instIt);
1661 }
1662}
1663
1664template <class Impl>
1665void
1666FullO3CPU<Impl>::cleanUpRemovedInsts()
1667{
1668 while (!removeList.empty()) {
1669 DPRINTF(O3CPU, "Removing instruction, "
1670 "[tid:%i] [sn:%lli] PC %s\n",
1671 (*removeList.front())->threadNumber,
1672 (*removeList.front())->seqNum,
1673 (*removeList.front())->pcState());
1674
1675 instList.erase(removeList.front());
1676
1677 removeList.pop();
1678 }
1679
1680 removeInstsThisCycle = false;
1681}
1682/*
1683template <class Impl>
1684void
1685FullO3CPU<Impl>::removeAllInsts()
1686{
1687 instList.clear();
1688}
1689*/
1690template <class Impl>
1691void
1692FullO3CPU<Impl>::dumpInsts()
1693{
1694 int num = 0;
1695
1696 ListIt inst_list_it = instList.begin();
1697
1698 cprintf("Dumping Instruction List\n");
1699
1700 while (inst_list_it != instList.end()) {
1701 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1702 "Squashed:%i\n\n",
1703 num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber,
1704 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1705 (*inst_list_it)->isSquashed());
1706 inst_list_it++;
1707 ++num;
1708 }
1709}
1710/*
1711template <class Impl>
1712void
1713FullO3CPU<Impl>::wakeDependents(const DynInstPtr &inst)
1714{
1715 iew.wakeDependents(inst);
1716}
1717*/
1718template <class Impl>
1719void
1720FullO3CPU<Impl>::wakeCPU()
1721{
1722 if (activityRec.active() || tickEvent.scheduled()) {
1723 DPRINTF(Activity, "CPU already running.\n");
1724 return;
1725 }
1726
1727 DPRINTF(Activity, "Waking up CPU\n");
1728
1729 Cycles cycles(curCycle() - lastRunningCycle);
1730 // @todo: This is an oddity that is only here to match the stats
1731 if (cycles > 1) {
1732 --cycles;
1733 idleCycles += cycles;
1734 numCycles += cycles;
1735 }
1736
1737 schedule(tickEvent, clockEdge());
1738}
1739
1740template <class Impl>
1741void
1742FullO3CPU<Impl>::wakeup(ThreadID tid)
1743{
1744 if (this->thread[tid]->status() != ThreadContext::Suspended)
1745 return;
1746
1747 this->wakeCPU();
1748
1749 DPRINTF(Quiesce, "Suspended Processor woken\n");
1750 this->threadContexts[tid]->activate();
1751}
1752
1753template <class Impl>
1754ThreadID
1755FullO3CPU<Impl>::getFreeTid()
1756{
1757 for (ThreadID tid = 0; tid < numThreads; tid++) {
1758 if (!tids[tid]) {
1759 tids[tid] = true;
1760 return tid;
1761 }
1762 }
1763
1764 return InvalidThreadID;
1765}
1766
1767template <class Impl>
1768void
1769FullO3CPU<Impl>::updateThreadPriority()
1770{
1771 if (activeThreads.size() > 1) {
1772 //DEFAULT TO ROUND ROBIN SCHEME
1773 //e.g. Move highest priority to end of thread list
1774 list<ThreadID>::iterator list_begin = activeThreads.begin();
1775
1776 unsigned high_thread = *list_begin;
1777
1778 activeThreads.erase(list_begin);
1779
1780 activeThreads.push_back(high_thread);
1781 }
1782}
1783
1784// Forward declaration of FullO3CPU.
1785template class FullO3CPU<O3CPUImpl>;
| 1414 return readVecElem(phys_reg);
1415}
1416
1417template <class Impl>
1418CCReg
1419FullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid)
1420{
1421 ccRegfileReads++;
1422 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1423 RegId(CCRegClass, reg_idx));
1424
1425 return regFile.readCCReg(phys_reg);
1426}
1427
1428template <class Impl>
1429void
1430FullO3CPU<Impl>::setArchIntReg(int reg_idx, RegVal val, ThreadID tid)
1431{
1432 intRegfileWrites++;
1433 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1434 RegId(IntRegClass, reg_idx));
1435
1436 regFile.setIntReg(phys_reg, val);
1437}
1438
1439template <class Impl>
1440void
1441FullO3CPU<Impl>::setArchFloatRegBits(int reg_idx, RegVal val, ThreadID tid)
1442{
1443 fpRegfileWrites++;
1444 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1445 RegId(FloatRegClass, reg_idx));
1446
1447 regFile.setFloatRegBits(phys_reg, val);
1448}
1449
1450template <class Impl>
1451void
1452FullO3CPU<Impl>::setArchVecReg(int reg_idx, const VecRegContainer& val,
1453 ThreadID tid)
1454{
1455 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1456 RegId(VecRegClass, reg_idx));
1457 setVecReg(phys_reg, val);
1458}
1459
1460template <class Impl>
1461void
1462FullO3CPU<Impl>::setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
1463 const VecElem& val, ThreadID tid)
1464{
1465 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1466 RegId(VecElemClass, reg_idx, ldx));
1467 setVecElem(phys_reg, val);
1468}
1469
1470template <class Impl>
1471void
1472FullO3CPU<Impl>::setArchCCReg(int reg_idx, CCReg val, ThreadID tid)
1473{
1474 ccRegfileWrites++;
1475 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1476 RegId(CCRegClass, reg_idx));
1477
1478 regFile.setCCReg(phys_reg, val);
1479}
1480
1481template <class Impl>
1482TheISA::PCState
1483FullO3CPU<Impl>::pcState(ThreadID tid)
1484{
1485 return commit.pcState(tid);
1486}
1487
1488template <class Impl>
1489void
1490FullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid)
1491{
1492 commit.pcState(val, tid);
1493}
1494
1495template <class Impl>
1496Addr
1497FullO3CPU<Impl>::instAddr(ThreadID tid)
1498{
1499 return commit.instAddr(tid);
1500}
1501
1502template <class Impl>
1503Addr
1504FullO3CPU<Impl>::nextInstAddr(ThreadID tid)
1505{
1506 return commit.nextInstAddr(tid);
1507}
1508
1509template <class Impl>
1510MicroPC
1511FullO3CPU<Impl>::microPC(ThreadID tid)
1512{
1513 return commit.microPC(tid);
1514}
1515
1516template <class Impl>
1517void
1518FullO3CPU<Impl>::squashFromTC(ThreadID tid)
1519{
1520 this->thread[tid]->noSquashFromTC = true;
1521 this->commit.generateTCEvent(tid);
1522}
1523
1524template <class Impl>
1525typename FullO3CPU<Impl>::ListIt
1526FullO3CPU<Impl>::addInst(const DynInstPtr &inst)
1527{
1528 instList.push_back(inst);
1529
1530 return --(instList.end());
1531}
1532
1533template <class Impl>
1534void
1535FullO3CPU<Impl>::instDone(ThreadID tid, const DynInstPtr &inst)
1536{
1537 // Keep an instruction count.
1538 if (!inst->isMicroop() || inst->isLastMicroop()) {
1539 thread[tid]->numInst++;
1540 thread[tid]->numInsts++;
1541 committedInsts[tid]++;
1542 system->totalNumInsts++;
1543
1544 // Check for instruction-count-based events.
1545 comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1546 system->instEventQueue.serviceEvents(system->totalNumInsts);
1547 }
1548 thread[tid]->numOp++;
1549 thread[tid]->numOps++;
1550 committedOps[tid]++;
1551
1552 probeInstCommit(inst->staticInst);
1553}
1554
1555template <class Impl>
1556void
1557FullO3CPU<Impl>::removeFrontInst(const DynInstPtr &inst)
1558{
1559 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s "
1560 "[sn:%lli]\n",
1561 inst->threadNumber, inst->pcState(), inst->seqNum);
1562
1563 removeInstsThisCycle = true;
1564
1565 // Remove the front instruction.
1566 removeList.push(inst->getInstListIt());
1567}
1568
1569template <class Impl>
1570void
1571FullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid)
1572{
1573 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1574 " list.\n", tid);
1575
1576 ListIt end_it;
1577
1578 bool rob_empty = false;
1579
1580 if (instList.empty()) {
1581 return;
1582 } else if (rob.isEmpty(tid)) {
1583 DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1584 end_it = instList.begin();
1585 rob_empty = true;
1586 } else {
1587 end_it = (rob.readTailInst(tid))->getInstListIt();
1588 DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1589 }
1590
1591 removeInstsThisCycle = true;
1592
1593 ListIt inst_it = instList.end();
1594
1595 inst_it--;
1596
1597 // Walk through the instruction list, removing any instructions
1598 // that were inserted after the given instruction iterator, end_it.
1599 while (inst_it != end_it) {
1600 assert(!instList.empty());
1601
1602 squashInstIt(inst_it, tid);
1603
1604 inst_it--;
1605 }
1606
1607 // If the ROB was empty, then we actually need to remove the first
1608 // instruction as well.
1609 if (rob_empty) {
1610 squashInstIt(inst_it, tid);
1611 }
1612}
1613
1614template <class Impl>
1615void
1616FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1617{
1618 assert(!instList.empty());
1619
1620 removeInstsThisCycle = true;
1621
1622 ListIt inst_iter = instList.end();
1623
1624 inst_iter--;
1625
1626 DPRINTF(O3CPU, "Deleting instructions from instruction "
1627 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1628 tid, seq_num, (*inst_iter)->seqNum);
1629
1630 while ((*inst_iter)->seqNum > seq_num) {
1631
1632 bool break_loop = (inst_iter == instList.begin());
1633
1634 squashInstIt(inst_iter, tid);
1635
1636 inst_iter--;
1637
1638 if (break_loop)
1639 break;
1640 }
1641}
1642
1643template <class Impl>
1644inline void
1645FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid)
1646{
1647 if ((*instIt)->threadNumber == tid) {
1648 DPRINTF(O3CPU, "Squashing instruction, "
1649 "[tid:%i] [sn:%lli] PC %s\n",
1650 (*instIt)->threadNumber,
1651 (*instIt)->seqNum,
1652 (*instIt)->pcState());
1653
1654 // Mark it as squashed.
1655 (*instIt)->setSquashed();
1656
1657 // @todo: Formulate a consistent method for deleting
1658 // instructions from the instruction list
1659 // Remove the instruction from the list.
1660 removeList.push(instIt);
1661 }
1662}
1663
1664template <class Impl>
1665void
1666FullO3CPU<Impl>::cleanUpRemovedInsts()
1667{
1668 while (!removeList.empty()) {
1669 DPRINTF(O3CPU, "Removing instruction, "
1670 "[tid:%i] [sn:%lli] PC %s\n",
1671 (*removeList.front())->threadNumber,
1672 (*removeList.front())->seqNum,
1673 (*removeList.front())->pcState());
1674
1675 instList.erase(removeList.front());
1676
1677 removeList.pop();
1678 }
1679
1680 removeInstsThisCycle = false;
1681}
1682/*
1683template <class Impl>
1684void
1685FullO3CPU<Impl>::removeAllInsts()
1686{
1687 instList.clear();
1688}
1689*/
1690template <class Impl>
1691void
1692FullO3CPU<Impl>::dumpInsts()
1693{
1694 int num = 0;
1695
1696 ListIt inst_list_it = instList.begin();
1697
1698 cprintf("Dumping Instruction List\n");
1699
1700 while (inst_list_it != instList.end()) {
1701 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1702 "Squashed:%i\n\n",
1703 num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber,
1704 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1705 (*inst_list_it)->isSquashed());
1706 inst_list_it++;
1707 ++num;
1708 }
1709}
1710/*
1711template <class Impl>
1712void
1713FullO3CPU<Impl>::wakeDependents(const DynInstPtr &inst)
1714{
1715 iew.wakeDependents(inst);
1716}
1717*/
1718template <class Impl>
1719void
1720FullO3CPU<Impl>::wakeCPU()
1721{
1722 if (activityRec.active() || tickEvent.scheduled()) {
1723 DPRINTF(Activity, "CPU already running.\n");
1724 return;
1725 }
1726
1727 DPRINTF(Activity, "Waking up CPU\n");
1728
1729 Cycles cycles(curCycle() - lastRunningCycle);
1730 // @todo: This is an oddity that is only here to match the stats
1731 if (cycles > 1) {
1732 --cycles;
1733 idleCycles += cycles;
1734 numCycles += cycles;
1735 }
1736
1737 schedule(tickEvent, clockEdge());
1738}
1739
1740template <class Impl>
1741void
1742FullO3CPU<Impl>::wakeup(ThreadID tid)
1743{
1744 if (this->thread[tid]->status() != ThreadContext::Suspended)
1745 return;
1746
1747 this->wakeCPU();
1748
1749 DPRINTF(Quiesce, "Suspended Processor woken\n");
1750 this->threadContexts[tid]->activate();
1751}
1752
1753template <class Impl>
1754ThreadID
1755FullO3CPU<Impl>::getFreeTid()
1756{
1757 for (ThreadID tid = 0; tid < numThreads; tid++) {
1758 if (!tids[tid]) {
1759 tids[tid] = true;
1760 return tid;
1761 }
1762 }
1763
1764 return InvalidThreadID;
1765}
1766
1767template <class Impl>
1768void
1769FullO3CPU<Impl>::updateThreadPriority()
1770{
1771 if (activeThreads.size() > 1) {
1772 //DEFAULT TO ROUND ROBIN SCHEME
1773 //e.g. Move highest priority to end of thread list
1774 list<ThreadID>::iterator list_begin = activeThreads.begin();
1775
1776 unsigned high_thread = *list_begin;
1777
1778 activeThreads.erase(list_begin);
1779
1780 activeThreads.push_back(high_thread);
1781 }
1782}
1783
1784// Forward declaration of FullO3CPU.
1785template class FullO3CPU<O3CPUImpl>;
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