1/*
2 * Copyright (c) 2011-2012, 2014, 2016, 2017 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * Copyright (c) 2011 Regents of the University of California
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Kevin Lim
43 * Korey Sewell
44 * Rick Strong
45 */
46
47#include "cpu/o3/cpu.hh"
48
49#include "arch/generic/traits.hh"
50#include "arch/kernel_stats.hh"
51#include "config/the_isa.hh"
52#include "cpu/activity.hh"
53#include "cpu/checker/cpu.hh"
54#include "cpu/checker/thread_context.hh"
55#include "cpu/o3/isa_specific.hh"
56#include "cpu/o3/thread_context.hh"
57#include "cpu/quiesce_event.hh"
58#include "cpu/simple_thread.hh"
59#include "cpu/thread_context.hh"
60#include "debug/Activity.hh"
61#include "debug/Drain.hh"
62#include "debug/O3CPU.hh"
63#include "debug/Quiesce.hh"
64#include "enums/MemoryMode.hh"
65#include "sim/core.hh"
66#include "sim/full_system.hh"
67#include "sim/process.hh"
68#include "sim/stat_control.hh"
69#include "sim/system.hh"
70
71#if THE_ISA == ALPHA_ISA
72#include "arch/alpha/osfpal.hh"
73#include "debug/Activity.hh"
74
75#endif
76
77struct BaseCPUParams;
78
79using namespace TheISA;
80using namespace std;
81
82BaseO3CPU::BaseO3CPU(BaseCPUParams *params)
83 : BaseCPU(params)
84{
85}
86
87void
88BaseO3CPU::regStats()
89{
90 BaseCPU::regStats();
91}
92
93template<class Impl>
94bool
95FullO3CPU<Impl>::IcachePort::recvTimingResp(PacketPtr pkt)
96{
97 DPRINTF(O3CPU, "Fetch unit received timing\n");
98 // We shouldn't ever get a cacheable block in Modified state
99 assert(pkt->req->isUncacheable() ||
100 !(pkt->cacheResponding() && !pkt->hasSharers()));
101 fetch->processCacheCompletion(pkt);
102
103 return true;
104}
105
106template<class Impl>
107void
108FullO3CPU<Impl>::IcachePort::recvReqRetry()
109{
110 fetch->recvReqRetry();
111}
112
113template <class Impl>
114bool
115FullO3CPU<Impl>::DcachePort::recvTimingResp(PacketPtr pkt)
116{
117 return lsq->recvTimingResp(pkt);
118}
119
120template <class Impl>
121void
122FullO3CPU<Impl>::DcachePort::recvTimingSnoopReq(PacketPtr pkt)
123{
124 for (ThreadID tid = 0; tid < cpu->numThreads; tid++) {
125 if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) {
126 cpu->wakeup(tid);
127 }
128 }
129 lsq->recvTimingSnoopReq(pkt);
130}
131
132template <class Impl>
133void
134FullO3CPU<Impl>::DcachePort::recvReqRetry()
135{
136 lsq->recvReqRetry();
137}
138
139template <class Impl>
140FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
141 : BaseO3CPU(params),
142 itb(params->itb),
143 dtb(params->dtb),
144 tickEvent([this]{ tick(); }, "FullO3CPU tick",
145 false, Event::CPU_Tick_Pri),
146#ifndef NDEBUG
147 instcount(0),
148#endif
149 removeInstsThisCycle(false),
150 fetch(this, params),
151 decode(this, params),
152 rename(this, params),
153 iew(this, params),
154 commit(this, params),
155
156 /* It is mandatory that all SMT threads use the same renaming mode as
157 * they are sharing registers and rename */
158 vecMode(initRenameMode<TheISA::ISA>::mode(params->isa[0])),
159 regFile(params->numPhysIntRegs,
160 params->numPhysFloatRegs,
161 params->numPhysVecRegs,
162 params->numPhysCCRegs,
163 vecMode),
164
165 freeList(name() + ".freelist", ®File),
166
167 rob(this, params),
168
169 scoreboard(name() + ".scoreboard",
170 regFile.totalNumPhysRegs()),
171
172 isa(numThreads, NULL),
173
174 icachePort(&fetch, this),
175 dcachePort(&iew.ldstQueue, this),
176
177 timeBuffer(params->backComSize, params->forwardComSize),
178 fetchQueue(params->backComSize, params->forwardComSize),
179 decodeQueue(params->backComSize, params->forwardComSize),
180 renameQueue(params->backComSize, params->forwardComSize),
181 iewQueue(params->backComSize, params->forwardComSize),
182 activityRec(name(), NumStages,
183 params->backComSize + params->forwardComSize,
184 params->activity),
185
186 globalSeqNum(1),
187 system(params->system),
188 lastRunningCycle(curCycle())
189{
190 if (!params->switched_out) {
191 _status = Running;
192 } else {
193 _status = SwitchedOut;
194 }
195
196 if (params->checker) {
197 BaseCPU *temp_checker = params->checker;
198 checker = dynamic_cast<Checker<Impl> *>(temp_checker);
199 checker->setIcachePort(&icachePort);
200 checker->setSystem(params->system);
201 } else {
202 checker = NULL;
203 }
204
205 if (!FullSystem) {
206 thread.resize(numThreads);
207 tids.resize(numThreads);
208 }
209
210 // The stages also need their CPU pointer setup. However this
211 // must be done at the upper level CPU because they have pointers
212 // to the upper level CPU, and not this FullO3CPU.
213
214 // Set up Pointers to the activeThreads list for each stage
215 fetch.setActiveThreads(&activeThreads);
216 decode.setActiveThreads(&activeThreads);
217 rename.setActiveThreads(&activeThreads);
218 iew.setActiveThreads(&activeThreads);
219 commit.setActiveThreads(&activeThreads);
220
221 // Give each of the stages the time buffer they will use.
222 fetch.setTimeBuffer(&timeBuffer);
223 decode.setTimeBuffer(&timeBuffer);
224 rename.setTimeBuffer(&timeBuffer);
225 iew.setTimeBuffer(&timeBuffer);
226 commit.setTimeBuffer(&timeBuffer);
227
228 // Also setup each of the stages' queues.
229 fetch.setFetchQueue(&fetchQueue);
230 decode.setFetchQueue(&fetchQueue);
231 commit.setFetchQueue(&fetchQueue);
232 decode.setDecodeQueue(&decodeQueue);
233 rename.setDecodeQueue(&decodeQueue);
234 rename.setRenameQueue(&renameQueue);
235 iew.setRenameQueue(&renameQueue);
236 iew.setIEWQueue(&iewQueue);
237 commit.setIEWQueue(&iewQueue);
238 commit.setRenameQueue(&renameQueue);
239
240 commit.setIEWStage(&iew);
241 rename.setIEWStage(&iew);
242 rename.setCommitStage(&commit);
243
244 ThreadID active_threads;
245 if (FullSystem) {
246 active_threads = 1;
247 } else {
248 active_threads = params->workload.size();
249
250 if (active_threads > Impl::MaxThreads) {
251 panic("Workload Size too large. Increase the 'MaxThreads' "
252 "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) "
253 "or edit your workload size.");
254 }
255 }
256
257 //Make Sure That this a Valid Architeture
258 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs);
259 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
260 assert(params->numPhysVecRegs >= numThreads * TheISA::NumVecRegs);
261 assert(params->numPhysCCRegs >= numThreads * TheISA::NumCCRegs);
262
263 rename.setScoreboard(&scoreboard);
264 iew.setScoreboard(&scoreboard);
265
266 // Setup the rename map for whichever stages need it.
267 for (ThreadID tid = 0; tid < numThreads; tid++) {
268 isa[tid] = params->isa[tid];
269 assert(initRenameMode<TheISA::ISA>::equals(isa[tid], isa[0]));
270
271 // Only Alpha has an FP zero register, so for other ISAs we
272 // use an invalid FP register index to avoid special treatment
273 // of any valid FP reg.
274 RegIndex invalidFPReg = TheISA::NumFloatRegs + 1;
275 RegIndex fpZeroReg =
276 (THE_ISA == ALPHA_ISA) ? TheISA::ZeroReg : invalidFPReg;
277
278 commitRenameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg,
279 &freeList,
280 vecMode);
281
282 renameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg,
283 &freeList, vecMode);
284 }
285
286 // Initialize rename map to assign physical registers to the
287 // architectural registers for active threads only.
288 for (ThreadID tid = 0; tid < active_threads; tid++) {
289 for (RegIndex ridx = 0; ridx < TheISA::NumIntRegs; ++ridx) {
290 // Note that we can't use the rename() method because we don't
291 // want special treatment for the zero register at this point
292 PhysRegIdPtr phys_reg = freeList.getIntReg();
293 renameMap[tid].setEntry(RegId(IntRegClass, ridx), phys_reg);
294 commitRenameMap[tid].setEntry(RegId(IntRegClass, ridx), phys_reg);
295 }
296
297 for (RegIndex ridx = 0; ridx < TheISA::NumFloatRegs; ++ridx) {
298 PhysRegIdPtr phys_reg = freeList.getFloatReg();
299 renameMap[tid].setEntry(RegId(FloatRegClass, ridx), phys_reg);
300 commitRenameMap[tid].setEntry(
301 RegId(FloatRegClass, ridx), phys_reg);
302 }
303
304 /* Here we need two 'interfaces' the 'whole register' and the
305 * 'register element'. At any point only one of them will be
306 * active. */
307 if (vecMode == Enums::Full) {
308 /* Initialize the full-vector interface */
309 for (RegIndex ridx = 0; ridx < TheISA::NumVecRegs; ++ridx) {
310 RegId rid = RegId(VecRegClass, ridx);
311 PhysRegIdPtr phys_reg = freeList.getVecReg();
312 renameMap[tid].setEntry(rid, phys_reg);
313 commitRenameMap[tid].setEntry(rid, phys_reg);
314 }
315 } else {
316 /* Initialize the vector-element interface */
317 for (RegIndex ridx = 0; ridx < TheISA::NumVecRegs; ++ridx) {
318 for (ElemIndex ldx = 0; ldx < TheISA::NumVecElemPerVecReg;
319 ++ldx) {
320 RegId lrid = RegId(VecElemClass, ridx, ldx);
321 PhysRegIdPtr phys_elem = freeList.getVecElem();
322 renameMap[tid].setEntry(lrid, phys_elem);
323 commitRenameMap[tid].setEntry(lrid, phys_elem);
324 }
325 }
326 }
327
328 for (RegIndex ridx = 0; ridx < TheISA::NumCCRegs; ++ridx) {
329 PhysRegIdPtr phys_reg = freeList.getCCReg();
330 renameMap[tid].setEntry(RegId(CCRegClass, ridx), phys_reg);
331 commitRenameMap[tid].setEntry(RegId(CCRegClass, ridx), phys_reg);
332 }
333 }
334
335 rename.setRenameMap(renameMap);
336 commit.setRenameMap(commitRenameMap);
337 rename.setFreeList(&freeList);
338
339 // Setup the ROB for whichever stages need it.
340 commit.setROB(&rob);
341
342 lastActivatedCycle = 0;
343#if 0
344 // Give renameMap & rename stage access to the freeList;
345 for (ThreadID tid = 0; tid < numThreads; tid++)
346 globalSeqNum[tid] = 1;
347#endif
348
349 DPRINTF(O3CPU, "Creating O3CPU object.\n");
350
351 // Setup any thread state.
352 this->thread.resize(this->numThreads);
353
354 for (ThreadID tid = 0; tid < this->numThreads; ++tid) {
355 if (FullSystem) {
356 // SMT is not supported in FS mode yet.
357 assert(this->numThreads == 1);
358 this->thread[tid] = new Thread(this, 0, NULL);
359 } else {
360 if (tid < params->workload.size()) {
361 DPRINTF(O3CPU, "Workload[%i] process is %#x",
362 tid, this->thread[tid]);
363 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
364 (typename Impl::O3CPU *)(this),
365 tid, params->workload[tid]);
366
367 //usedTids[tid] = true;
368 //threadMap[tid] = tid;
369 } else {
370 //Allocate Empty thread so M5 can use later
371 //when scheduling threads to CPU
372 Process* dummy_proc = NULL;
373
374 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
375 (typename Impl::O3CPU *)(this),
376 tid, dummy_proc);
377 //usedTids[tid] = false;
378 }
379 }
380
381 ThreadContext *tc;
382
383 // Setup the TC that will serve as the interface to the threads/CPU.
384 O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>;
385
386 tc = o3_tc;
387
388 // If we're using a checker, then the TC should be the
389 // CheckerThreadContext.
390 if (params->checker) {
391 tc = new CheckerThreadContext<O3ThreadContext<Impl> >(
392 o3_tc, this->checker);
393 }
394
395 o3_tc->cpu = (typename Impl::O3CPU *)(this);
396 assert(o3_tc->cpu);
397 o3_tc->thread = this->thread[tid];
398
399 // Setup quiesce event.
400 this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
401
402 // Give the thread the TC.
403 this->thread[tid]->tc = tc;
404
405 // Add the TC to the CPU's list of TC's.
406 this->threadContexts.push_back(tc);
407 }
408
409 // FullO3CPU always requires an interrupt controller.
410 if (!params->switched_out && interrupts.empty()) {
411 fatal("FullO3CPU %s has no interrupt controller.\n"
412 "Ensure createInterruptController() is called.\n", name());
413 }
414
415 for (ThreadID tid = 0; tid < this->numThreads; tid++)
416 this->thread[tid]->setFuncExeInst(0);
417}
418
419template <class Impl>
420FullO3CPU<Impl>::~FullO3CPU()
421{
422}
423
424template <class Impl>
425void
426FullO3CPU<Impl>::regProbePoints()
427{
428 BaseCPU::regProbePoints();
429
430 ppInstAccessComplete = new ProbePointArg<PacketPtr>(getProbeManager(), "InstAccessComplete");
431 ppDataAccessComplete = new ProbePointArg<std::pair<DynInstPtr, PacketPtr> >(getProbeManager(), "DataAccessComplete");
432
433 fetch.regProbePoints();
434 rename.regProbePoints();
435 iew.regProbePoints();
436 commit.regProbePoints();
437}
438
439template <class Impl>
440void
441FullO3CPU<Impl>::regStats()
442{
443 BaseO3CPU::regStats();
444
445 // Register any of the O3CPU's stats here.
446 timesIdled
447 .name(name() + ".timesIdled")
448 .desc("Number of times that the entire CPU went into an idle state and"
449 " unscheduled itself")
450 .prereq(timesIdled);
451
452 idleCycles
453 .name(name() + ".idleCycles")
454 .desc("Total number of cycles that the CPU has spent unscheduled due "
455 "to idling")
456 .prereq(idleCycles);
457
458 quiesceCycles
459 .name(name() + ".quiesceCycles")
460 .desc("Total number of cycles that CPU has spent quiesced or waiting "
461 "for an interrupt")
462 .prereq(quiesceCycles);
463
464 // Number of Instructions simulated
465 // --------------------------------
466 // Should probably be in Base CPU but need templated
467 // MaxThreads so put in here instead
468 committedInsts
469 .init(numThreads)
470 .name(name() + ".committedInsts")
471 .desc("Number of Instructions Simulated")
472 .flags(Stats::total);
473
474 committedOps
475 .init(numThreads)
476 .name(name() + ".committedOps")
477 .desc("Number of Ops (including micro ops) Simulated")
478 .flags(Stats::total);
479
480 cpi
481 .name(name() + ".cpi")
482 .desc("CPI: Cycles Per Instruction")
483 .precision(6);
484 cpi = numCycles / committedInsts;
485
486 totalCpi
487 .name(name() + ".cpi_total")
488 .desc("CPI: Total CPI of All Threads")
489 .precision(6);
490 totalCpi = numCycles / sum(committedInsts);
491
492 ipc
493 .name(name() + ".ipc")
494 .desc("IPC: Instructions Per Cycle")
495 .precision(6);
496 ipc = committedInsts / numCycles;
497
498 totalIpc
499 .name(name() + ".ipc_total")
500 .desc("IPC: Total IPC of All Threads")
501 .precision(6);
502 totalIpc = sum(committedInsts) / numCycles;
503
504 this->fetch.regStats();
505 this->decode.regStats();
506 this->rename.regStats();
507 this->iew.regStats();
508 this->commit.regStats();
509 this->rob.regStats();
510
511 intRegfileReads
512 .name(name() + ".int_regfile_reads")
513 .desc("number of integer regfile reads")
514 .prereq(intRegfileReads);
515
516 intRegfileWrites
517 .name(name() + ".int_regfile_writes")
518 .desc("number of integer regfile writes")
519 .prereq(intRegfileWrites);
520
521 fpRegfileReads
522 .name(name() + ".fp_regfile_reads")
523 .desc("number of floating regfile reads")
524 .prereq(fpRegfileReads);
525
526 fpRegfileWrites
527 .name(name() + ".fp_regfile_writes")
528 .desc("number of floating regfile writes")
529 .prereq(fpRegfileWrites);
530
531 vecRegfileReads
532 .name(name() + ".vec_regfile_reads")
533 .desc("number of vector regfile reads")
534 .prereq(vecRegfileReads);
535
536 vecRegfileWrites
537 .name(name() + ".vec_regfile_writes")
538 .desc("number of vector regfile writes")
539 .prereq(vecRegfileWrites);
540
541 ccRegfileReads
542 .name(name() + ".cc_regfile_reads")
543 .desc("number of cc regfile reads")
544 .prereq(ccRegfileReads);
545
546 ccRegfileWrites
547 .name(name() + ".cc_regfile_writes")
548 .desc("number of cc regfile writes")
549 .prereq(ccRegfileWrites);
550
551 miscRegfileReads
552 .name(name() + ".misc_regfile_reads")
553 .desc("number of misc regfile reads")
554 .prereq(miscRegfileReads);
555
556 miscRegfileWrites
557 .name(name() + ".misc_regfile_writes")
558 .desc("number of misc regfile writes")
559 .prereq(miscRegfileWrites);
560}
561
562template <class Impl>
563void
564FullO3CPU<Impl>::tick()
565{
566 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
567 assert(!switchedOut());
568 assert(drainState() != DrainState::Drained);
569
570 ++numCycles;
| 1/*
2 * Copyright (c) 2011-2012, 2014, 2016, 2017 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * Copyright (c) 2011 Regents of the University of California
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Kevin Lim
43 * Korey Sewell
44 * Rick Strong
45 */
46
47#include "cpu/o3/cpu.hh"
48
49#include "arch/generic/traits.hh"
50#include "arch/kernel_stats.hh"
51#include "config/the_isa.hh"
52#include "cpu/activity.hh"
53#include "cpu/checker/cpu.hh"
54#include "cpu/checker/thread_context.hh"
55#include "cpu/o3/isa_specific.hh"
56#include "cpu/o3/thread_context.hh"
57#include "cpu/quiesce_event.hh"
58#include "cpu/simple_thread.hh"
59#include "cpu/thread_context.hh"
60#include "debug/Activity.hh"
61#include "debug/Drain.hh"
62#include "debug/O3CPU.hh"
63#include "debug/Quiesce.hh"
64#include "enums/MemoryMode.hh"
65#include "sim/core.hh"
66#include "sim/full_system.hh"
67#include "sim/process.hh"
68#include "sim/stat_control.hh"
69#include "sim/system.hh"
70
71#if THE_ISA == ALPHA_ISA
72#include "arch/alpha/osfpal.hh"
73#include "debug/Activity.hh"
74
75#endif
76
77struct BaseCPUParams;
78
79using namespace TheISA;
80using namespace std;
81
82BaseO3CPU::BaseO3CPU(BaseCPUParams *params)
83 : BaseCPU(params)
84{
85}
86
87void
88BaseO3CPU::regStats()
89{
90 BaseCPU::regStats();
91}
92
93template<class Impl>
94bool
95FullO3CPU<Impl>::IcachePort::recvTimingResp(PacketPtr pkt)
96{
97 DPRINTF(O3CPU, "Fetch unit received timing\n");
98 // We shouldn't ever get a cacheable block in Modified state
99 assert(pkt->req->isUncacheable() ||
100 !(pkt->cacheResponding() && !pkt->hasSharers()));
101 fetch->processCacheCompletion(pkt);
102
103 return true;
104}
105
106template<class Impl>
107void
108FullO3CPU<Impl>::IcachePort::recvReqRetry()
109{
110 fetch->recvReqRetry();
111}
112
113template <class Impl>
114bool
115FullO3CPU<Impl>::DcachePort::recvTimingResp(PacketPtr pkt)
116{
117 return lsq->recvTimingResp(pkt);
118}
119
120template <class Impl>
121void
122FullO3CPU<Impl>::DcachePort::recvTimingSnoopReq(PacketPtr pkt)
123{
124 for (ThreadID tid = 0; tid < cpu->numThreads; tid++) {
125 if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) {
126 cpu->wakeup(tid);
127 }
128 }
129 lsq->recvTimingSnoopReq(pkt);
130}
131
132template <class Impl>
133void
134FullO3CPU<Impl>::DcachePort::recvReqRetry()
135{
136 lsq->recvReqRetry();
137}
138
139template <class Impl>
140FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
141 : BaseO3CPU(params),
142 itb(params->itb),
143 dtb(params->dtb),
144 tickEvent([this]{ tick(); }, "FullO3CPU tick",
145 false, Event::CPU_Tick_Pri),
146#ifndef NDEBUG
147 instcount(0),
148#endif
149 removeInstsThisCycle(false),
150 fetch(this, params),
151 decode(this, params),
152 rename(this, params),
153 iew(this, params),
154 commit(this, params),
155
156 /* It is mandatory that all SMT threads use the same renaming mode as
157 * they are sharing registers and rename */
158 vecMode(initRenameMode<TheISA::ISA>::mode(params->isa[0])),
159 regFile(params->numPhysIntRegs,
160 params->numPhysFloatRegs,
161 params->numPhysVecRegs,
162 params->numPhysCCRegs,
163 vecMode),
164
165 freeList(name() + ".freelist", ®File),
166
167 rob(this, params),
168
169 scoreboard(name() + ".scoreboard",
170 regFile.totalNumPhysRegs()),
171
172 isa(numThreads, NULL),
173
174 icachePort(&fetch, this),
175 dcachePort(&iew.ldstQueue, this),
176
177 timeBuffer(params->backComSize, params->forwardComSize),
178 fetchQueue(params->backComSize, params->forwardComSize),
179 decodeQueue(params->backComSize, params->forwardComSize),
180 renameQueue(params->backComSize, params->forwardComSize),
181 iewQueue(params->backComSize, params->forwardComSize),
182 activityRec(name(), NumStages,
183 params->backComSize + params->forwardComSize,
184 params->activity),
185
186 globalSeqNum(1),
187 system(params->system),
188 lastRunningCycle(curCycle())
189{
190 if (!params->switched_out) {
191 _status = Running;
192 } else {
193 _status = SwitchedOut;
194 }
195
196 if (params->checker) {
197 BaseCPU *temp_checker = params->checker;
198 checker = dynamic_cast<Checker<Impl> *>(temp_checker);
199 checker->setIcachePort(&icachePort);
200 checker->setSystem(params->system);
201 } else {
202 checker = NULL;
203 }
204
205 if (!FullSystem) {
206 thread.resize(numThreads);
207 tids.resize(numThreads);
208 }
209
210 // The stages also need their CPU pointer setup. However this
211 // must be done at the upper level CPU because they have pointers
212 // to the upper level CPU, and not this FullO3CPU.
213
214 // Set up Pointers to the activeThreads list for each stage
215 fetch.setActiveThreads(&activeThreads);
216 decode.setActiveThreads(&activeThreads);
217 rename.setActiveThreads(&activeThreads);
218 iew.setActiveThreads(&activeThreads);
219 commit.setActiveThreads(&activeThreads);
220
221 // Give each of the stages the time buffer they will use.
222 fetch.setTimeBuffer(&timeBuffer);
223 decode.setTimeBuffer(&timeBuffer);
224 rename.setTimeBuffer(&timeBuffer);
225 iew.setTimeBuffer(&timeBuffer);
226 commit.setTimeBuffer(&timeBuffer);
227
228 // Also setup each of the stages' queues.
229 fetch.setFetchQueue(&fetchQueue);
230 decode.setFetchQueue(&fetchQueue);
231 commit.setFetchQueue(&fetchQueue);
232 decode.setDecodeQueue(&decodeQueue);
233 rename.setDecodeQueue(&decodeQueue);
234 rename.setRenameQueue(&renameQueue);
235 iew.setRenameQueue(&renameQueue);
236 iew.setIEWQueue(&iewQueue);
237 commit.setIEWQueue(&iewQueue);
238 commit.setRenameQueue(&renameQueue);
239
240 commit.setIEWStage(&iew);
241 rename.setIEWStage(&iew);
242 rename.setCommitStage(&commit);
243
244 ThreadID active_threads;
245 if (FullSystem) {
246 active_threads = 1;
247 } else {
248 active_threads = params->workload.size();
249
250 if (active_threads > Impl::MaxThreads) {
251 panic("Workload Size too large. Increase the 'MaxThreads' "
252 "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) "
253 "or edit your workload size.");
254 }
255 }
256
257 //Make Sure That this a Valid Architeture
258 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs);
259 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
260 assert(params->numPhysVecRegs >= numThreads * TheISA::NumVecRegs);
261 assert(params->numPhysCCRegs >= numThreads * TheISA::NumCCRegs);
262
263 rename.setScoreboard(&scoreboard);
264 iew.setScoreboard(&scoreboard);
265
266 // Setup the rename map for whichever stages need it.
267 for (ThreadID tid = 0; tid < numThreads; tid++) {
268 isa[tid] = params->isa[tid];
269 assert(initRenameMode<TheISA::ISA>::equals(isa[tid], isa[0]));
270
271 // Only Alpha has an FP zero register, so for other ISAs we
272 // use an invalid FP register index to avoid special treatment
273 // of any valid FP reg.
274 RegIndex invalidFPReg = TheISA::NumFloatRegs + 1;
275 RegIndex fpZeroReg =
276 (THE_ISA == ALPHA_ISA) ? TheISA::ZeroReg : invalidFPReg;
277
278 commitRenameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg,
279 &freeList,
280 vecMode);
281
282 renameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg,
283 &freeList, vecMode);
284 }
285
286 // Initialize rename map to assign physical registers to the
287 // architectural registers for active threads only.
288 for (ThreadID tid = 0; tid < active_threads; tid++) {
289 for (RegIndex ridx = 0; ridx < TheISA::NumIntRegs; ++ridx) {
290 // Note that we can't use the rename() method because we don't
291 // want special treatment for the zero register at this point
292 PhysRegIdPtr phys_reg = freeList.getIntReg();
293 renameMap[tid].setEntry(RegId(IntRegClass, ridx), phys_reg);
294 commitRenameMap[tid].setEntry(RegId(IntRegClass, ridx), phys_reg);
295 }
296
297 for (RegIndex ridx = 0; ridx < TheISA::NumFloatRegs; ++ridx) {
298 PhysRegIdPtr phys_reg = freeList.getFloatReg();
299 renameMap[tid].setEntry(RegId(FloatRegClass, ridx), phys_reg);
300 commitRenameMap[tid].setEntry(
301 RegId(FloatRegClass, ridx), phys_reg);
302 }
303
304 /* Here we need two 'interfaces' the 'whole register' and the
305 * 'register element'. At any point only one of them will be
306 * active. */
307 if (vecMode == Enums::Full) {
308 /* Initialize the full-vector interface */
309 for (RegIndex ridx = 0; ridx < TheISA::NumVecRegs; ++ridx) {
310 RegId rid = RegId(VecRegClass, ridx);
311 PhysRegIdPtr phys_reg = freeList.getVecReg();
312 renameMap[tid].setEntry(rid, phys_reg);
313 commitRenameMap[tid].setEntry(rid, phys_reg);
314 }
315 } else {
316 /* Initialize the vector-element interface */
317 for (RegIndex ridx = 0; ridx < TheISA::NumVecRegs; ++ridx) {
318 for (ElemIndex ldx = 0; ldx < TheISA::NumVecElemPerVecReg;
319 ++ldx) {
320 RegId lrid = RegId(VecElemClass, ridx, ldx);
321 PhysRegIdPtr phys_elem = freeList.getVecElem();
322 renameMap[tid].setEntry(lrid, phys_elem);
323 commitRenameMap[tid].setEntry(lrid, phys_elem);
324 }
325 }
326 }
327
328 for (RegIndex ridx = 0; ridx < TheISA::NumCCRegs; ++ridx) {
329 PhysRegIdPtr phys_reg = freeList.getCCReg();
330 renameMap[tid].setEntry(RegId(CCRegClass, ridx), phys_reg);
331 commitRenameMap[tid].setEntry(RegId(CCRegClass, ridx), phys_reg);
332 }
333 }
334
335 rename.setRenameMap(renameMap);
336 commit.setRenameMap(commitRenameMap);
337 rename.setFreeList(&freeList);
338
339 // Setup the ROB for whichever stages need it.
340 commit.setROB(&rob);
341
342 lastActivatedCycle = 0;
343#if 0
344 // Give renameMap & rename stage access to the freeList;
345 for (ThreadID tid = 0; tid < numThreads; tid++)
346 globalSeqNum[tid] = 1;
347#endif
348
349 DPRINTF(O3CPU, "Creating O3CPU object.\n");
350
351 // Setup any thread state.
352 this->thread.resize(this->numThreads);
353
354 for (ThreadID tid = 0; tid < this->numThreads; ++tid) {
355 if (FullSystem) {
356 // SMT is not supported in FS mode yet.
357 assert(this->numThreads == 1);
358 this->thread[tid] = new Thread(this, 0, NULL);
359 } else {
360 if (tid < params->workload.size()) {
361 DPRINTF(O3CPU, "Workload[%i] process is %#x",
362 tid, this->thread[tid]);
363 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
364 (typename Impl::O3CPU *)(this),
365 tid, params->workload[tid]);
366
367 //usedTids[tid] = true;
368 //threadMap[tid] = tid;
369 } else {
370 //Allocate Empty thread so M5 can use later
371 //when scheduling threads to CPU
372 Process* dummy_proc = NULL;
373
374 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
375 (typename Impl::O3CPU *)(this),
376 tid, dummy_proc);
377 //usedTids[tid] = false;
378 }
379 }
380
381 ThreadContext *tc;
382
383 // Setup the TC that will serve as the interface to the threads/CPU.
384 O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>;
385
386 tc = o3_tc;
387
388 // If we're using a checker, then the TC should be the
389 // CheckerThreadContext.
390 if (params->checker) {
391 tc = new CheckerThreadContext<O3ThreadContext<Impl> >(
392 o3_tc, this->checker);
393 }
394
395 o3_tc->cpu = (typename Impl::O3CPU *)(this);
396 assert(o3_tc->cpu);
397 o3_tc->thread = this->thread[tid];
398
399 // Setup quiesce event.
400 this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
401
402 // Give the thread the TC.
403 this->thread[tid]->tc = tc;
404
405 // Add the TC to the CPU's list of TC's.
406 this->threadContexts.push_back(tc);
407 }
408
409 // FullO3CPU always requires an interrupt controller.
410 if (!params->switched_out && interrupts.empty()) {
411 fatal("FullO3CPU %s has no interrupt controller.\n"
412 "Ensure createInterruptController() is called.\n", name());
413 }
414
415 for (ThreadID tid = 0; tid < this->numThreads; tid++)
416 this->thread[tid]->setFuncExeInst(0);
417}
418
419template <class Impl>
420FullO3CPU<Impl>::~FullO3CPU()
421{
422}
423
424template <class Impl>
425void
426FullO3CPU<Impl>::regProbePoints()
427{
428 BaseCPU::regProbePoints();
429
430 ppInstAccessComplete = new ProbePointArg<PacketPtr>(getProbeManager(), "InstAccessComplete");
431 ppDataAccessComplete = new ProbePointArg<std::pair<DynInstPtr, PacketPtr> >(getProbeManager(), "DataAccessComplete");
432
433 fetch.regProbePoints();
434 rename.regProbePoints();
435 iew.regProbePoints();
436 commit.regProbePoints();
437}
438
439template <class Impl>
440void
441FullO3CPU<Impl>::regStats()
442{
443 BaseO3CPU::regStats();
444
445 // Register any of the O3CPU's stats here.
446 timesIdled
447 .name(name() + ".timesIdled")
448 .desc("Number of times that the entire CPU went into an idle state and"
449 " unscheduled itself")
450 .prereq(timesIdled);
451
452 idleCycles
453 .name(name() + ".idleCycles")
454 .desc("Total number of cycles that the CPU has spent unscheduled due "
455 "to idling")
456 .prereq(idleCycles);
457
458 quiesceCycles
459 .name(name() + ".quiesceCycles")
460 .desc("Total number of cycles that CPU has spent quiesced or waiting "
461 "for an interrupt")
462 .prereq(quiesceCycles);
463
464 // Number of Instructions simulated
465 // --------------------------------
466 // Should probably be in Base CPU but need templated
467 // MaxThreads so put in here instead
468 committedInsts
469 .init(numThreads)
470 .name(name() + ".committedInsts")
471 .desc("Number of Instructions Simulated")
472 .flags(Stats::total);
473
474 committedOps
475 .init(numThreads)
476 .name(name() + ".committedOps")
477 .desc("Number of Ops (including micro ops) Simulated")
478 .flags(Stats::total);
479
480 cpi
481 .name(name() + ".cpi")
482 .desc("CPI: Cycles Per Instruction")
483 .precision(6);
484 cpi = numCycles / committedInsts;
485
486 totalCpi
487 .name(name() + ".cpi_total")
488 .desc("CPI: Total CPI of All Threads")
489 .precision(6);
490 totalCpi = numCycles / sum(committedInsts);
491
492 ipc
493 .name(name() + ".ipc")
494 .desc("IPC: Instructions Per Cycle")
495 .precision(6);
496 ipc = committedInsts / numCycles;
497
498 totalIpc
499 .name(name() + ".ipc_total")
500 .desc("IPC: Total IPC of All Threads")
501 .precision(6);
502 totalIpc = sum(committedInsts) / numCycles;
503
504 this->fetch.regStats();
505 this->decode.regStats();
506 this->rename.regStats();
507 this->iew.regStats();
508 this->commit.regStats();
509 this->rob.regStats();
510
511 intRegfileReads
512 .name(name() + ".int_regfile_reads")
513 .desc("number of integer regfile reads")
514 .prereq(intRegfileReads);
515
516 intRegfileWrites
517 .name(name() + ".int_regfile_writes")
518 .desc("number of integer regfile writes")
519 .prereq(intRegfileWrites);
520
521 fpRegfileReads
522 .name(name() + ".fp_regfile_reads")
523 .desc("number of floating regfile reads")
524 .prereq(fpRegfileReads);
525
526 fpRegfileWrites
527 .name(name() + ".fp_regfile_writes")
528 .desc("number of floating regfile writes")
529 .prereq(fpRegfileWrites);
530
531 vecRegfileReads
532 .name(name() + ".vec_regfile_reads")
533 .desc("number of vector regfile reads")
534 .prereq(vecRegfileReads);
535
536 vecRegfileWrites
537 .name(name() + ".vec_regfile_writes")
538 .desc("number of vector regfile writes")
539 .prereq(vecRegfileWrites);
540
541 ccRegfileReads
542 .name(name() + ".cc_regfile_reads")
543 .desc("number of cc regfile reads")
544 .prereq(ccRegfileReads);
545
546 ccRegfileWrites
547 .name(name() + ".cc_regfile_writes")
548 .desc("number of cc regfile writes")
549 .prereq(ccRegfileWrites);
550
551 miscRegfileReads
552 .name(name() + ".misc_regfile_reads")
553 .desc("number of misc regfile reads")
554 .prereq(miscRegfileReads);
555
556 miscRegfileWrites
557 .name(name() + ".misc_regfile_writes")
558 .desc("number of misc regfile writes")
559 .prereq(miscRegfileWrites);
560}
561
562template <class Impl>
563void
564FullO3CPU<Impl>::tick()
565{
566 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
567 assert(!switchedOut());
568 assert(drainState() != DrainState::Drained);
569
570 ++numCycles;
|
799}
800
801template <class Impl>
802void
803FullO3CPU<Impl>::insertThread(ThreadID tid)
804{
805 DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
806 // Will change now that the PC and thread state is internal to the CPU
807 // and not in the ThreadContext.
808 ThreadContext *src_tc;
809 if (FullSystem)
810 src_tc = system->threadContexts[tid];
811 else
812 src_tc = tcBase(tid);
813
814 //Bind Int Regs to Rename Map
815
816 for (RegId reg_id(IntRegClass, 0); reg_id.index() < TheISA::NumIntRegs;
817 reg_id.index()++) {
818 PhysRegIdPtr phys_reg = freeList.getIntReg();
819 renameMap[tid].setEntry(reg_id, phys_reg);
820 scoreboard.setReg(phys_reg);
821 }
822
823 //Bind Float Regs to Rename Map
824 for (RegId reg_id(FloatRegClass, 0); reg_id.index() < TheISA::NumFloatRegs;
825 reg_id.index()++) {
826 PhysRegIdPtr phys_reg = freeList.getFloatReg();
827 renameMap[tid].setEntry(reg_id, phys_reg);
828 scoreboard.setReg(phys_reg);
829 }
830
831 //Bind condition-code Regs to Rename Map
832 for (RegId reg_id(CCRegClass, 0); reg_id.index() < TheISA::NumCCRegs;
833 reg_id.index()++) {
834 PhysRegIdPtr phys_reg = freeList.getCCReg();
835 renameMap[tid].setEntry(reg_id, phys_reg);
836 scoreboard.setReg(phys_reg);
837 }
838
839 //Copy Thread Data Into RegFile
840 //this->copyFromTC(tid);
841
842 //Set PC/NPC/NNPC
843 pcState(src_tc->pcState(), tid);
844
845 src_tc->setStatus(ThreadContext::Active);
846
847 activateContext(tid);
848
849 //Reset ROB/IQ/LSQ Entries
850 commit.rob->resetEntries();
851 iew.resetEntries();
852}
853
854template <class Impl>
855void
856FullO3CPU<Impl>::removeThread(ThreadID tid)
857{
858 DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
859
860 // Copy Thread Data From RegFile
861 // If thread is suspended, it might be re-allocated
862 // this->copyToTC(tid);
863
864
865 // @todo: 2-27-2008: Fix how we free up rename mappings
866 // here to alleviate the case for double-freeing registers
867 // in SMT workloads.
868
869 // Unbind Int Regs from Rename Map
870 for (RegId reg_id(IntRegClass, 0); reg_id.index() < TheISA::NumIntRegs;
871 reg_id.index()++) {
872 PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id);
873 scoreboard.unsetReg(phys_reg);
874 freeList.addReg(phys_reg);
875 }
876
877 // Unbind Float Regs from Rename Map
878 for (RegId reg_id(FloatRegClass, 0); reg_id.index() < TheISA::NumFloatRegs;
879 reg_id.index()++) {
880 PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id);
881 scoreboard.unsetReg(phys_reg);
882 freeList.addReg(phys_reg);
883 }
884
885 // Unbind condition-code Regs from Rename Map
886 for (RegId reg_id(CCRegClass, 0); reg_id.index() < TheISA::NumCCRegs;
887 reg_id.index()++) {
888 PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id);
889 scoreboard.unsetReg(phys_reg);
890 freeList.addReg(phys_reg);
891 }
892
893 // Squash Throughout Pipeline
894 DynInstPtr inst = commit.rob->readHeadInst(tid);
895 InstSeqNum squash_seq_num = inst->seqNum;
896 fetch.squash(0, squash_seq_num, inst, tid);
897 decode.squash(tid);
898 rename.squash(squash_seq_num, tid);
899 iew.squash(tid);
900 iew.ldstQueue.squash(squash_seq_num, tid);
901 commit.rob->squash(squash_seq_num, tid);
902
903
904 assert(iew.instQueue.getCount(tid) == 0);
905 assert(iew.ldstQueue.getCount(tid) == 0);
906
907 // Reset ROB/IQ/LSQ Entries
908
909 // Commented out for now. This should be possible to do by
910 // telling all the pipeline stages to drain first, and then
911 // checking until the drain completes. Once the pipeline is
912 // drained, call resetEntries(). - 10-09-06 ktlim
913/*
914 if (activeThreads.size() >= 1) {
915 commit.rob->resetEntries();
916 iew.resetEntries();
917 }
918*/
919}
920
921template <class Impl>
922Fault
923FullO3CPU<Impl>::hwrei(ThreadID tid)
924{
925#if THE_ISA == ALPHA_ISA
926 // Need to clear the lock flag upon returning from an interrupt.
927 this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
928
929 this->thread[tid]->kernelStats->hwrei();
930
931 // FIXME: XXX check for interrupts? XXX
932#endif
933 return NoFault;
934}
935
936template <class Impl>
937bool
938FullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid)
939{
940#if THE_ISA == ALPHA_ISA
941 if (this->thread[tid]->kernelStats)
942 this->thread[tid]->kernelStats->callpal(palFunc,
943 this->threadContexts[tid]);
944
945 switch (palFunc) {
946 case PAL::halt:
947 halt();
948 if (--System::numSystemsRunning == 0)
949 exitSimLoop("all cpus halted");
950 break;
951
952 case PAL::bpt:
953 case PAL::bugchk:
954 if (this->system->breakpoint())
955 return false;
956 break;
957 }
958#endif
959 return true;
960}
961
962template <class Impl>
963Fault
964FullO3CPU<Impl>::getInterrupts()
965{
966 // Check if there are any outstanding interrupts
967 return this->interrupts[0]->getInterrupt(this->threadContexts[0]);
968}
969
970template <class Impl>
971void
972FullO3CPU<Impl>::processInterrupts(const Fault &interrupt)
973{
974 // Check for interrupts here. For now can copy the code that
975 // exists within isa_fullsys_traits.hh. Also assume that thread 0
976 // is the one that handles the interrupts.
977 // @todo: Possibly consolidate the interrupt checking code.
978 // @todo: Allow other threads to handle interrupts.
979
980 assert(interrupt != NoFault);
981 this->interrupts[0]->updateIntrInfo(this->threadContexts[0]);
982
983 DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
984 this->trap(interrupt, 0, nullptr);
985}
986
987template <class Impl>
988void
989FullO3CPU<Impl>::trap(const Fault &fault, ThreadID tid,
990 const StaticInstPtr &inst)
991{
992 // Pass the thread's TC into the invoke method.
993 fault->invoke(this->threadContexts[tid], inst);
994}
995
996template <class Impl>
997void
998FullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid, Fault *fault)
999{
1000 DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid);
1001
1002 DPRINTF(Activity,"Activity: syscall() called.\n");
1003
1004 // Temporarily increase this by one to account for the syscall
1005 // instruction.
1006 ++(this->thread[tid]->funcExeInst);
1007
1008 // Execute the actual syscall.
1009 this->thread[tid]->syscall(callnum, fault);
1010
1011 // Decrease funcExeInst by one as the normal commit will handle
1012 // incrementing it.
1013 --(this->thread[tid]->funcExeInst);
1014}
1015
1016template <class Impl>
1017void
1018FullO3CPU<Impl>::serializeThread(CheckpointOut &cp, ThreadID tid) const
1019{
1020 thread[tid]->serialize(cp);
1021}
1022
1023template <class Impl>
1024void
1025FullO3CPU<Impl>::unserializeThread(CheckpointIn &cp, ThreadID tid)
1026{
1027 thread[tid]->unserialize(cp);
1028}
1029
1030template <class Impl>
1031DrainState
1032FullO3CPU<Impl>::drain()
1033{
1034 // Deschedule any power gating event (if any)
1035 deschedulePowerGatingEvent();
1036
1037 // If the CPU isn't doing anything, then return immediately.
1038 if (switchedOut())
1039 return DrainState::Drained;
1040
1041 DPRINTF(Drain, "Draining...\n");
1042
1043 // We only need to signal a drain to the commit stage as this
1044 // initiates squashing controls the draining. Once the commit
1045 // stage commits an instruction where it is safe to stop, it'll
1046 // squash the rest of the instructions in the pipeline and force
1047 // the fetch stage to stall. The pipeline will be drained once all
1048 // in-flight instructions have retired.
1049 commit.drain();
1050
1051 // Wake the CPU and record activity so everything can drain out if
1052 // the CPU was not able to immediately drain.
1053 if (!isDrained()) {
1054 // If a thread is suspended, wake it up so it can be drained
1055 for (auto t : threadContexts) {
1056 if (t->status() == ThreadContext::Suspended){
1057 DPRINTF(Drain, "Currently suspended so activate %i \n",
1058 t->threadId());
1059 t->activate();
1060 // As the thread is now active, change the power state as well
1061 activateContext(t->threadId());
1062 }
1063 }
1064
1065 wakeCPU();
1066 activityRec.activity();
1067
1068 DPRINTF(Drain, "CPU not drained\n");
1069
1070 return DrainState::Draining;
1071 } else {
1072 DPRINTF(Drain, "CPU is already drained\n");
1073 if (tickEvent.scheduled())
1074 deschedule(tickEvent);
1075
1076 // Flush out any old data from the time buffers. In
1077 // particular, there might be some data in flight from the
1078 // fetch stage that isn't visible in any of the CPU buffers we
1079 // test in isDrained().
1080 for (int i = 0; i < timeBuffer.getSize(); ++i) {
1081 timeBuffer.advance();
1082 fetchQueue.advance();
1083 decodeQueue.advance();
1084 renameQueue.advance();
1085 iewQueue.advance();
1086 }
1087
1088 drainSanityCheck();
1089 return DrainState::Drained;
1090 }
1091}
1092
1093template <class Impl>
1094bool
1095FullO3CPU<Impl>::tryDrain()
1096{
1097 if (drainState() != DrainState::Draining || !isDrained())
1098 return false;
1099
1100 if (tickEvent.scheduled())
1101 deschedule(tickEvent);
1102
1103 DPRINTF(Drain, "CPU done draining, processing drain event\n");
1104 signalDrainDone();
1105
1106 return true;
1107}
1108
1109template <class Impl>
1110void
1111FullO3CPU<Impl>::drainSanityCheck() const
1112{
1113 assert(isDrained());
1114 fetch.drainSanityCheck();
1115 decode.drainSanityCheck();
1116 rename.drainSanityCheck();
1117 iew.drainSanityCheck();
1118 commit.drainSanityCheck();
1119}
1120
1121template <class Impl>
1122bool
1123FullO3CPU<Impl>::isDrained() const
1124{
1125 bool drained(true);
1126
1127 if (!instList.empty() || !removeList.empty()) {
1128 DPRINTF(Drain, "Main CPU structures not drained.\n");
1129 drained = false;
1130 }
1131
1132 if (!fetch.isDrained()) {
1133 DPRINTF(Drain, "Fetch not drained.\n");
1134 drained = false;
1135 }
1136
1137 if (!decode.isDrained()) {
1138 DPRINTF(Drain, "Decode not drained.\n");
1139 drained = false;
1140 }
1141
1142 if (!rename.isDrained()) {
1143 DPRINTF(Drain, "Rename not drained.\n");
1144 drained = false;
1145 }
1146
1147 if (!iew.isDrained()) {
1148 DPRINTF(Drain, "IEW not drained.\n");
1149 drained = false;
1150 }
1151
1152 if (!commit.isDrained()) {
1153 DPRINTF(Drain, "Commit not drained.\n");
1154 drained = false;
1155 }
1156
1157 return drained;
1158}
1159
1160template <class Impl>
1161void
1162FullO3CPU<Impl>::commitDrained(ThreadID tid)
1163{
1164 fetch.drainStall(tid);
1165}
1166
1167template <class Impl>
1168void
1169FullO3CPU<Impl>::drainResume()
1170{
1171 if (switchedOut())
1172 return;
1173
1174 DPRINTF(Drain, "Resuming...\n");
1175 verifyMemoryMode();
1176
1177 fetch.drainResume();
1178 commit.drainResume();
1179
1180 _status = Idle;
1181 for (ThreadID i = 0; i < thread.size(); i++) {
1182 if (thread[i]->status() == ThreadContext::Active) {
1183 DPRINTF(Drain, "Activating thread: %i\n", i);
1184 activateThread(i);
1185 _status = Running;
1186 }
1187 }
1188
1189 assert(!tickEvent.scheduled());
1190 if (_status == Running)
1191 schedule(tickEvent, nextCycle());
1192
1193 // Reschedule any power gating event (if any)
1194 schedulePowerGatingEvent();
1195}
1196
1197template <class Impl>
1198void
1199FullO3CPU<Impl>::switchOut()
1200{
1201 DPRINTF(O3CPU, "Switching out\n");
1202 BaseCPU::switchOut();
1203
1204 activityRec.reset();
1205
1206 _status = SwitchedOut;
1207
1208 if (checker)
1209 checker->switchOut();
1210}
1211
1212template <class Impl>
1213void
1214FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
1215{
1216 BaseCPU::takeOverFrom(oldCPU);
1217
1218 fetch.takeOverFrom();
1219 decode.takeOverFrom();
1220 rename.takeOverFrom();
1221 iew.takeOverFrom();
1222 commit.takeOverFrom();
1223
1224 assert(!tickEvent.scheduled());
1225
1226 FullO3CPU<Impl> *oldO3CPU = dynamic_cast<FullO3CPU<Impl>*>(oldCPU);
1227 if (oldO3CPU)
1228 globalSeqNum = oldO3CPU->globalSeqNum;
1229
1230 lastRunningCycle = curCycle();
1231 _status = Idle;
1232}
1233
1234template <class Impl>
1235void
1236FullO3CPU<Impl>::verifyMemoryMode() const
1237{
1238 if (!system->isTimingMode()) {
1239 fatal("The O3 CPU requires the memory system to be in "
1240 "'timing' mode.\n");
1241 }
1242}
1243
1244template <class Impl>
1245TheISA::MiscReg
1246FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
1247{
1248 return this->isa[tid]->readMiscRegNoEffect(misc_reg);
1249}
1250
1251template <class Impl>
1252TheISA::MiscReg
1253FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
1254{
1255 miscRegfileReads++;
1256 return this->isa[tid]->readMiscReg(misc_reg, tcBase(tid));
1257}
1258
1259template <class Impl>
1260void
1261FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
1262 const TheISA::MiscReg &val, ThreadID tid)
1263{
1264 this->isa[tid]->setMiscRegNoEffect(misc_reg, val);
1265}
1266
1267template <class Impl>
1268void
1269FullO3CPU<Impl>::setMiscReg(int misc_reg,
1270 const TheISA::MiscReg &val, ThreadID tid)
1271{
1272 miscRegfileWrites++;
1273 this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid));
1274}
1275
1276template <class Impl>
1277uint64_t
1278FullO3CPU<Impl>::readIntReg(PhysRegIdPtr phys_reg)
1279{
1280 intRegfileReads++;
1281 return regFile.readIntReg(phys_reg);
1282}
1283
1284template <class Impl>
1285FloatReg
1286FullO3CPU<Impl>::readFloatReg(PhysRegIdPtr phys_reg)
1287{
1288 fpRegfileReads++;
1289 return regFile.readFloatReg(phys_reg);
1290}
1291
1292template <class Impl>
1293FloatRegBits
1294FullO3CPU<Impl>::readFloatRegBits(PhysRegIdPtr phys_reg)
1295{
1296 fpRegfileReads++;
1297 return regFile.readFloatRegBits(phys_reg);
1298}
1299
1300template <class Impl>
1301auto
1302FullO3CPU<Impl>::readVecReg(PhysRegIdPtr phys_reg) const
1303 -> const VecRegContainer&
1304{
1305 vecRegfileReads++;
1306 return regFile.readVecReg(phys_reg);
1307}
1308
1309template <class Impl>
1310auto
1311FullO3CPU<Impl>::getWritableVecReg(PhysRegIdPtr phys_reg)
1312 -> VecRegContainer&
1313{
1314 vecRegfileWrites++;
1315 return regFile.getWritableVecReg(phys_reg);
1316}
1317
1318template <class Impl>
1319auto
1320FullO3CPU<Impl>::readVecElem(PhysRegIdPtr phys_reg) const -> const VecElem&
1321{
1322 vecRegfileReads++;
1323 return regFile.readVecElem(phys_reg);
1324}
1325
1326template <class Impl>
1327CCReg
1328FullO3CPU<Impl>::readCCReg(PhysRegIdPtr phys_reg)
1329{
1330 ccRegfileReads++;
1331 return regFile.readCCReg(phys_reg);
1332}
1333
1334template <class Impl>
1335void
1336FullO3CPU<Impl>::setIntReg(PhysRegIdPtr phys_reg, uint64_t val)
1337{
1338 intRegfileWrites++;
1339 regFile.setIntReg(phys_reg, val);
1340}
1341
1342template <class Impl>
1343void
1344FullO3CPU<Impl>::setFloatReg(PhysRegIdPtr phys_reg, FloatReg val)
1345{
1346 fpRegfileWrites++;
1347 regFile.setFloatReg(phys_reg, val);
1348}
1349
1350template <class Impl>
1351void
1352FullO3CPU<Impl>::setFloatRegBits(PhysRegIdPtr phys_reg, FloatRegBits val)
1353{
1354 fpRegfileWrites++;
1355 regFile.setFloatRegBits(phys_reg, val);
1356}
1357
1358template <class Impl>
1359void
1360FullO3CPU<Impl>::setVecReg(PhysRegIdPtr phys_reg, const VecRegContainer& val)
1361{
1362 vecRegfileWrites++;
1363 regFile.setVecReg(phys_reg, val);
1364}
1365
1366template <class Impl>
1367void
1368FullO3CPU<Impl>::setVecElem(PhysRegIdPtr phys_reg, const VecElem& val)
1369{
1370 vecRegfileWrites++;
1371 regFile.setVecElem(phys_reg, val);
1372}
1373
1374template <class Impl>
1375void
1376FullO3CPU<Impl>::setCCReg(PhysRegIdPtr phys_reg, CCReg val)
1377{
1378 ccRegfileWrites++;
1379 regFile.setCCReg(phys_reg, val);
1380}
1381
1382template <class Impl>
1383uint64_t
1384FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1385{
1386 intRegfileReads++;
1387 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1388 RegId(IntRegClass, reg_idx));
1389
1390 return regFile.readIntReg(phys_reg);
1391}
1392
1393template <class Impl>
1394float
1395FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
1396{
1397 fpRegfileReads++;
1398 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1399 RegId(FloatRegClass, reg_idx));
1400
1401 return regFile.readFloatReg(phys_reg);
1402}
1403
1404template <class Impl>
1405uint64_t
1406FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid)
1407{
1408 fpRegfileReads++;
1409 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1410 RegId(FloatRegClass, reg_idx));
1411
1412 return regFile.readFloatRegBits(phys_reg);
1413}
1414
1415template <class Impl>
1416auto
1417FullO3CPU<Impl>::readArchVecReg(int reg_idx, ThreadID tid) const
1418 -> const VecRegContainer&
1419{
1420 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1421 RegId(VecRegClass, reg_idx));
1422 return readVecReg(phys_reg);
1423}
1424
1425template <class Impl>
1426auto
1427FullO3CPU<Impl>::getWritableArchVecReg(int reg_idx, ThreadID tid)
1428 -> VecRegContainer&
1429{
1430 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1431 RegId(VecRegClass, reg_idx));
1432 return getWritableVecReg(phys_reg);
1433}
1434
1435template <class Impl>
1436auto
1437FullO3CPU<Impl>::readArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
1438 ThreadID tid) const -> const VecElem&
1439{
1440 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1441 RegId(VecRegClass, reg_idx, ldx));
1442 return readVecElem(phys_reg);
1443}
1444
1445template <class Impl>
1446CCReg
1447FullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid)
1448{
1449 ccRegfileReads++;
1450 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1451 RegId(CCRegClass, reg_idx));
1452
1453 return regFile.readCCReg(phys_reg);
1454}
1455
1456template <class Impl>
1457void
1458FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
1459{
1460 intRegfileWrites++;
1461 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1462 RegId(IntRegClass, reg_idx));
1463
1464 regFile.setIntReg(phys_reg, val);
1465}
1466
1467template <class Impl>
1468void
1469FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid)
1470{
1471 fpRegfileWrites++;
1472 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1473 RegId(FloatRegClass, reg_idx));
1474
1475 regFile.setFloatReg(phys_reg, val);
1476}
1477
1478template <class Impl>
1479void
1480FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid)
1481{
1482 fpRegfileWrites++;
1483 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1484 RegId(FloatRegClass, reg_idx));
1485
1486 regFile.setFloatRegBits(phys_reg, val);
1487}
1488
1489template <class Impl>
1490void
1491FullO3CPU<Impl>::setArchVecReg(int reg_idx, const VecRegContainer& val,
1492 ThreadID tid)
1493{
1494 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1495 RegId(VecRegClass, reg_idx));
1496 setVecReg(phys_reg, val);
1497}
1498
1499template <class Impl>
1500void
1501FullO3CPU<Impl>::setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
1502 const VecElem& val, ThreadID tid)
1503{
1504 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1505 RegId(VecRegClass, reg_idx, ldx));
1506 setVecElem(phys_reg, val);
1507}
1508
1509template <class Impl>
1510void
1511FullO3CPU<Impl>::setArchCCReg(int reg_idx, CCReg val, ThreadID tid)
1512{
1513 ccRegfileWrites++;
1514 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1515 RegId(CCRegClass, reg_idx));
1516
1517 regFile.setCCReg(phys_reg, val);
1518}
1519
1520template <class Impl>
1521TheISA::PCState
1522FullO3CPU<Impl>::pcState(ThreadID tid)
1523{
1524 return commit.pcState(tid);
1525}
1526
1527template <class Impl>
1528void
1529FullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid)
1530{
1531 commit.pcState(val, tid);
1532}
1533
1534template <class Impl>
1535Addr
1536FullO3CPU<Impl>::instAddr(ThreadID tid)
1537{
1538 return commit.instAddr(tid);
1539}
1540
1541template <class Impl>
1542Addr
1543FullO3CPU<Impl>::nextInstAddr(ThreadID tid)
1544{
1545 return commit.nextInstAddr(tid);
1546}
1547
1548template <class Impl>
1549MicroPC
1550FullO3CPU<Impl>::microPC(ThreadID tid)
1551{
1552 return commit.microPC(tid);
1553}
1554
1555template <class Impl>
1556void
1557FullO3CPU<Impl>::squashFromTC(ThreadID tid)
1558{
1559 this->thread[tid]->noSquashFromTC = true;
1560 this->commit.generateTCEvent(tid);
1561}
1562
1563template <class Impl>
1564typename FullO3CPU<Impl>::ListIt
1565FullO3CPU<Impl>::addInst(DynInstPtr &inst)
1566{
1567 instList.push_back(inst);
1568
1569 return --(instList.end());
1570}
1571
1572template <class Impl>
1573void
1574FullO3CPU<Impl>::instDone(ThreadID tid, DynInstPtr &inst)
1575{
1576 // Keep an instruction count.
1577 if (!inst->isMicroop() || inst->isLastMicroop()) {
1578 thread[tid]->numInst++;
1579 thread[tid]->numInsts++;
1580 committedInsts[tid]++;
1581 system->totalNumInsts++;
1582
1583 // Check for instruction-count-based events.
1584 comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1585 system->instEventQueue.serviceEvents(system->totalNumInsts);
1586 }
1587 thread[tid]->numOp++;
1588 thread[tid]->numOps++;
1589 committedOps[tid]++;
1590
1591 probeInstCommit(inst->staticInst);
1592}
1593
1594template <class Impl>
1595void
1596FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
1597{
1598 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s "
1599 "[sn:%lli]\n",
1600 inst->threadNumber, inst->pcState(), inst->seqNum);
1601
1602 removeInstsThisCycle = true;
1603
1604 // Remove the front instruction.
1605 removeList.push(inst->getInstListIt());
1606}
1607
1608template <class Impl>
1609void
1610FullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid)
1611{
1612 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1613 " list.\n", tid);
1614
1615 ListIt end_it;
1616
1617 bool rob_empty = false;
1618
1619 if (instList.empty()) {
1620 return;
1621 } else if (rob.isEmpty(tid)) {
1622 DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1623 end_it = instList.begin();
1624 rob_empty = true;
1625 } else {
1626 end_it = (rob.readTailInst(tid))->getInstListIt();
1627 DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1628 }
1629
1630 removeInstsThisCycle = true;
1631
1632 ListIt inst_it = instList.end();
1633
1634 inst_it--;
1635
1636 // Walk through the instruction list, removing any instructions
1637 // that were inserted after the given instruction iterator, end_it.
1638 while (inst_it != end_it) {
1639 assert(!instList.empty());
1640
1641 squashInstIt(inst_it, tid);
1642
1643 inst_it--;
1644 }
1645
1646 // If the ROB was empty, then we actually need to remove the first
1647 // instruction as well.
1648 if (rob_empty) {
1649 squashInstIt(inst_it, tid);
1650 }
1651}
1652
1653template <class Impl>
1654void
1655FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1656{
1657 assert(!instList.empty());
1658
1659 removeInstsThisCycle = true;
1660
1661 ListIt inst_iter = instList.end();
1662
1663 inst_iter--;
1664
1665 DPRINTF(O3CPU, "Deleting instructions from instruction "
1666 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1667 tid, seq_num, (*inst_iter)->seqNum);
1668
1669 while ((*inst_iter)->seqNum > seq_num) {
1670
1671 bool break_loop = (inst_iter == instList.begin());
1672
1673 squashInstIt(inst_iter, tid);
1674
1675 inst_iter--;
1676
1677 if (break_loop)
1678 break;
1679 }
1680}
1681
1682template <class Impl>
1683inline void
1684FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid)
1685{
1686 if ((*instIt)->threadNumber == tid) {
1687 DPRINTF(O3CPU, "Squashing instruction, "
1688 "[tid:%i] [sn:%lli] PC %s\n",
1689 (*instIt)->threadNumber,
1690 (*instIt)->seqNum,
1691 (*instIt)->pcState());
1692
1693 // Mark it as squashed.
1694 (*instIt)->setSquashed();
1695
1696 // @todo: Formulate a consistent method for deleting
1697 // instructions from the instruction list
1698 // Remove the instruction from the list.
1699 removeList.push(instIt);
1700 }
1701}
1702
1703template <class Impl>
1704void
1705FullO3CPU<Impl>::cleanUpRemovedInsts()
1706{
1707 while (!removeList.empty()) {
1708 DPRINTF(O3CPU, "Removing instruction, "
1709 "[tid:%i] [sn:%lli] PC %s\n",
1710 (*removeList.front())->threadNumber,
1711 (*removeList.front())->seqNum,
1712 (*removeList.front())->pcState());
1713
1714 instList.erase(removeList.front());
1715
1716 removeList.pop();
1717 }
1718
1719 removeInstsThisCycle = false;
1720}
1721/*
1722template <class Impl>
1723void
1724FullO3CPU<Impl>::removeAllInsts()
1725{
1726 instList.clear();
1727}
1728*/
1729template <class Impl>
1730void
1731FullO3CPU<Impl>::dumpInsts()
1732{
1733 int num = 0;
1734
1735 ListIt inst_list_it = instList.begin();
1736
1737 cprintf("Dumping Instruction List\n");
1738
1739 while (inst_list_it != instList.end()) {
1740 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1741 "Squashed:%i\n\n",
1742 num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber,
1743 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1744 (*inst_list_it)->isSquashed());
1745 inst_list_it++;
1746 ++num;
1747 }
1748}
1749/*
1750template <class Impl>
1751void
1752FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
1753{
1754 iew.wakeDependents(inst);
1755}
1756*/
1757template <class Impl>
1758void
1759FullO3CPU<Impl>::wakeCPU()
1760{
1761 if (activityRec.active() || tickEvent.scheduled()) {
1762 DPRINTF(Activity, "CPU already running.\n");
1763 return;
1764 }
1765
1766 DPRINTF(Activity, "Waking up CPU\n");
1767
1768 Cycles cycles(curCycle() - lastRunningCycle);
1769 // @todo: This is an oddity that is only here to match the stats
1770 if (cycles > 1) {
1771 --cycles;
1772 idleCycles += cycles;
1773 numCycles += cycles;
| 801}
802
803template <class Impl>
804void
805FullO3CPU<Impl>::insertThread(ThreadID tid)
806{
807 DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
808 // Will change now that the PC and thread state is internal to the CPU
809 // and not in the ThreadContext.
810 ThreadContext *src_tc;
811 if (FullSystem)
812 src_tc = system->threadContexts[tid];
813 else
814 src_tc = tcBase(tid);
815
816 //Bind Int Regs to Rename Map
817
818 for (RegId reg_id(IntRegClass, 0); reg_id.index() < TheISA::NumIntRegs;
819 reg_id.index()++) {
820 PhysRegIdPtr phys_reg = freeList.getIntReg();
821 renameMap[tid].setEntry(reg_id, phys_reg);
822 scoreboard.setReg(phys_reg);
823 }
824
825 //Bind Float Regs to Rename Map
826 for (RegId reg_id(FloatRegClass, 0); reg_id.index() < TheISA::NumFloatRegs;
827 reg_id.index()++) {
828 PhysRegIdPtr phys_reg = freeList.getFloatReg();
829 renameMap[tid].setEntry(reg_id, phys_reg);
830 scoreboard.setReg(phys_reg);
831 }
832
833 //Bind condition-code Regs to Rename Map
834 for (RegId reg_id(CCRegClass, 0); reg_id.index() < TheISA::NumCCRegs;
835 reg_id.index()++) {
836 PhysRegIdPtr phys_reg = freeList.getCCReg();
837 renameMap[tid].setEntry(reg_id, phys_reg);
838 scoreboard.setReg(phys_reg);
839 }
840
841 //Copy Thread Data Into RegFile
842 //this->copyFromTC(tid);
843
844 //Set PC/NPC/NNPC
845 pcState(src_tc->pcState(), tid);
846
847 src_tc->setStatus(ThreadContext::Active);
848
849 activateContext(tid);
850
851 //Reset ROB/IQ/LSQ Entries
852 commit.rob->resetEntries();
853 iew.resetEntries();
854}
855
856template <class Impl>
857void
858FullO3CPU<Impl>::removeThread(ThreadID tid)
859{
860 DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
861
862 // Copy Thread Data From RegFile
863 // If thread is suspended, it might be re-allocated
864 // this->copyToTC(tid);
865
866
867 // @todo: 2-27-2008: Fix how we free up rename mappings
868 // here to alleviate the case for double-freeing registers
869 // in SMT workloads.
870
871 // Unbind Int Regs from Rename Map
872 for (RegId reg_id(IntRegClass, 0); reg_id.index() < TheISA::NumIntRegs;
873 reg_id.index()++) {
874 PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id);
875 scoreboard.unsetReg(phys_reg);
876 freeList.addReg(phys_reg);
877 }
878
879 // Unbind Float Regs from Rename Map
880 for (RegId reg_id(FloatRegClass, 0); reg_id.index() < TheISA::NumFloatRegs;
881 reg_id.index()++) {
882 PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id);
883 scoreboard.unsetReg(phys_reg);
884 freeList.addReg(phys_reg);
885 }
886
887 // Unbind condition-code Regs from Rename Map
888 for (RegId reg_id(CCRegClass, 0); reg_id.index() < TheISA::NumCCRegs;
889 reg_id.index()++) {
890 PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id);
891 scoreboard.unsetReg(phys_reg);
892 freeList.addReg(phys_reg);
893 }
894
895 // Squash Throughout Pipeline
896 DynInstPtr inst = commit.rob->readHeadInst(tid);
897 InstSeqNum squash_seq_num = inst->seqNum;
898 fetch.squash(0, squash_seq_num, inst, tid);
899 decode.squash(tid);
900 rename.squash(squash_seq_num, tid);
901 iew.squash(tid);
902 iew.ldstQueue.squash(squash_seq_num, tid);
903 commit.rob->squash(squash_seq_num, tid);
904
905
906 assert(iew.instQueue.getCount(tid) == 0);
907 assert(iew.ldstQueue.getCount(tid) == 0);
908
909 // Reset ROB/IQ/LSQ Entries
910
911 // Commented out for now. This should be possible to do by
912 // telling all the pipeline stages to drain first, and then
913 // checking until the drain completes. Once the pipeline is
914 // drained, call resetEntries(). - 10-09-06 ktlim
915/*
916 if (activeThreads.size() >= 1) {
917 commit.rob->resetEntries();
918 iew.resetEntries();
919 }
920*/
921}
922
923template <class Impl>
924Fault
925FullO3CPU<Impl>::hwrei(ThreadID tid)
926{
927#if THE_ISA == ALPHA_ISA
928 // Need to clear the lock flag upon returning from an interrupt.
929 this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
930
931 this->thread[tid]->kernelStats->hwrei();
932
933 // FIXME: XXX check for interrupts? XXX
934#endif
935 return NoFault;
936}
937
938template <class Impl>
939bool
940FullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid)
941{
942#if THE_ISA == ALPHA_ISA
943 if (this->thread[tid]->kernelStats)
944 this->thread[tid]->kernelStats->callpal(palFunc,
945 this->threadContexts[tid]);
946
947 switch (palFunc) {
948 case PAL::halt:
949 halt();
950 if (--System::numSystemsRunning == 0)
951 exitSimLoop("all cpus halted");
952 break;
953
954 case PAL::bpt:
955 case PAL::bugchk:
956 if (this->system->breakpoint())
957 return false;
958 break;
959 }
960#endif
961 return true;
962}
963
964template <class Impl>
965Fault
966FullO3CPU<Impl>::getInterrupts()
967{
968 // Check if there are any outstanding interrupts
969 return this->interrupts[0]->getInterrupt(this->threadContexts[0]);
970}
971
972template <class Impl>
973void
974FullO3CPU<Impl>::processInterrupts(const Fault &interrupt)
975{
976 // Check for interrupts here. For now can copy the code that
977 // exists within isa_fullsys_traits.hh. Also assume that thread 0
978 // is the one that handles the interrupts.
979 // @todo: Possibly consolidate the interrupt checking code.
980 // @todo: Allow other threads to handle interrupts.
981
982 assert(interrupt != NoFault);
983 this->interrupts[0]->updateIntrInfo(this->threadContexts[0]);
984
985 DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
986 this->trap(interrupt, 0, nullptr);
987}
988
989template <class Impl>
990void
991FullO3CPU<Impl>::trap(const Fault &fault, ThreadID tid,
992 const StaticInstPtr &inst)
993{
994 // Pass the thread's TC into the invoke method.
995 fault->invoke(this->threadContexts[tid], inst);
996}
997
998template <class Impl>
999void
1000FullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid, Fault *fault)
1001{
1002 DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid);
1003
1004 DPRINTF(Activity,"Activity: syscall() called.\n");
1005
1006 // Temporarily increase this by one to account for the syscall
1007 // instruction.
1008 ++(this->thread[tid]->funcExeInst);
1009
1010 // Execute the actual syscall.
1011 this->thread[tid]->syscall(callnum, fault);
1012
1013 // Decrease funcExeInst by one as the normal commit will handle
1014 // incrementing it.
1015 --(this->thread[tid]->funcExeInst);
1016}
1017
1018template <class Impl>
1019void
1020FullO3CPU<Impl>::serializeThread(CheckpointOut &cp, ThreadID tid) const
1021{
1022 thread[tid]->serialize(cp);
1023}
1024
1025template <class Impl>
1026void
1027FullO3CPU<Impl>::unserializeThread(CheckpointIn &cp, ThreadID tid)
1028{
1029 thread[tid]->unserialize(cp);
1030}
1031
1032template <class Impl>
1033DrainState
1034FullO3CPU<Impl>::drain()
1035{
1036 // Deschedule any power gating event (if any)
1037 deschedulePowerGatingEvent();
1038
1039 // If the CPU isn't doing anything, then return immediately.
1040 if (switchedOut())
1041 return DrainState::Drained;
1042
1043 DPRINTF(Drain, "Draining...\n");
1044
1045 // We only need to signal a drain to the commit stage as this
1046 // initiates squashing controls the draining. Once the commit
1047 // stage commits an instruction where it is safe to stop, it'll
1048 // squash the rest of the instructions in the pipeline and force
1049 // the fetch stage to stall. The pipeline will be drained once all
1050 // in-flight instructions have retired.
1051 commit.drain();
1052
1053 // Wake the CPU and record activity so everything can drain out if
1054 // the CPU was not able to immediately drain.
1055 if (!isDrained()) {
1056 // If a thread is suspended, wake it up so it can be drained
1057 for (auto t : threadContexts) {
1058 if (t->status() == ThreadContext::Suspended){
1059 DPRINTF(Drain, "Currently suspended so activate %i \n",
1060 t->threadId());
1061 t->activate();
1062 // As the thread is now active, change the power state as well
1063 activateContext(t->threadId());
1064 }
1065 }
1066
1067 wakeCPU();
1068 activityRec.activity();
1069
1070 DPRINTF(Drain, "CPU not drained\n");
1071
1072 return DrainState::Draining;
1073 } else {
1074 DPRINTF(Drain, "CPU is already drained\n");
1075 if (tickEvent.scheduled())
1076 deschedule(tickEvent);
1077
1078 // Flush out any old data from the time buffers. In
1079 // particular, there might be some data in flight from the
1080 // fetch stage that isn't visible in any of the CPU buffers we
1081 // test in isDrained().
1082 for (int i = 0; i < timeBuffer.getSize(); ++i) {
1083 timeBuffer.advance();
1084 fetchQueue.advance();
1085 decodeQueue.advance();
1086 renameQueue.advance();
1087 iewQueue.advance();
1088 }
1089
1090 drainSanityCheck();
1091 return DrainState::Drained;
1092 }
1093}
1094
1095template <class Impl>
1096bool
1097FullO3CPU<Impl>::tryDrain()
1098{
1099 if (drainState() != DrainState::Draining || !isDrained())
1100 return false;
1101
1102 if (tickEvent.scheduled())
1103 deschedule(tickEvent);
1104
1105 DPRINTF(Drain, "CPU done draining, processing drain event\n");
1106 signalDrainDone();
1107
1108 return true;
1109}
1110
1111template <class Impl>
1112void
1113FullO3CPU<Impl>::drainSanityCheck() const
1114{
1115 assert(isDrained());
1116 fetch.drainSanityCheck();
1117 decode.drainSanityCheck();
1118 rename.drainSanityCheck();
1119 iew.drainSanityCheck();
1120 commit.drainSanityCheck();
1121}
1122
1123template <class Impl>
1124bool
1125FullO3CPU<Impl>::isDrained() const
1126{
1127 bool drained(true);
1128
1129 if (!instList.empty() || !removeList.empty()) {
1130 DPRINTF(Drain, "Main CPU structures not drained.\n");
1131 drained = false;
1132 }
1133
1134 if (!fetch.isDrained()) {
1135 DPRINTF(Drain, "Fetch not drained.\n");
1136 drained = false;
1137 }
1138
1139 if (!decode.isDrained()) {
1140 DPRINTF(Drain, "Decode not drained.\n");
1141 drained = false;
1142 }
1143
1144 if (!rename.isDrained()) {
1145 DPRINTF(Drain, "Rename not drained.\n");
1146 drained = false;
1147 }
1148
1149 if (!iew.isDrained()) {
1150 DPRINTF(Drain, "IEW not drained.\n");
1151 drained = false;
1152 }
1153
1154 if (!commit.isDrained()) {
1155 DPRINTF(Drain, "Commit not drained.\n");
1156 drained = false;
1157 }
1158
1159 return drained;
1160}
1161
1162template <class Impl>
1163void
1164FullO3CPU<Impl>::commitDrained(ThreadID tid)
1165{
1166 fetch.drainStall(tid);
1167}
1168
1169template <class Impl>
1170void
1171FullO3CPU<Impl>::drainResume()
1172{
1173 if (switchedOut())
1174 return;
1175
1176 DPRINTF(Drain, "Resuming...\n");
1177 verifyMemoryMode();
1178
1179 fetch.drainResume();
1180 commit.drainResume();
1181
1182 _status = Idle;
1183 for (ThreadID i = 0; i < thread.size(); i++) {
1184 if (thread[i]->status() == ThreadContext::Active) {
1185 DPRINTF(Drain, "Activating thread: %i\n", i);
1186 activateThread(i);
1187 _status = Running;
1188 }
1189 }
1190
1191 assert(!tickEvent.scheduled());
1192 if (_status == Running)
1193 schedule(tickEvent, nextCycle());
1194
1195 // Reschedule any power gating event (if any)
1196 schedulePowerGatingEvent();
1197}
1198
1199template <class Impl>
1200void
1201FullO3CPU<Impl>::switchOut()
1202{
1203 DPRINTF(O3CPU, "Switching out\n");
1204 BaseCPU::switchOut();
1205
1206 activityRec.reset();
1207
1208 _status = SwitchedOut;
1209
1210 if (checker)
1211 checker->switchOut();
1212}
1213
1214template <class Impl>
1215void
1216FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
1217{
1218 BaseCPU::takeOverFrom(oldCPU);
1219
1220 fetch.takeOverFrom();
1221 decode.takeOverFrom();
1222 rename.takeOverFrom();
1223 iew.takeOverFrom();
1224 commit.takeOverFrom();
1225
1226 assert(!tickEvent.scheduled());
1227
1228 FullO3CPU<Impl> *oldO3CPU = dynamic_cast<FullO3CPU<Impl>*>(oldCPU);
1229 if (oldO3CPU)
1230 globalSeqNum = oldO3CPU->globalSeqNum;
1231
1232 lastRunningCycle = curCycle();
1233 _status = Idle;
1234}
1235
1236template <class Impl>
1237void
1238FullO3CPU<Impl>::verifyMemoryMode() const
1239{
1240 if (!system->isTimingMode()) {
1241 fatal("The O3 CPU requires the memory system to be in "
1242 "'timing' mode.\n");
1243 }
1244}
1245
1246template <class Impl>
1247TheISA::MiscReg
1248FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
1249{
1250 return this->isa[tid]->readMiscRegNoEffect(misc_reg);
1251}
1252
1253template <class Impl>
1254TheISA::MiscReg
1255FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
1256{
1257 miscRegfileReads++;
1258 return this->isa[tid]->readMiscReg(misc_reg, tcBase(tid));
1259}
1260
1261template <class Impl>
1262void
1263FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
1264 const TheISA::MiscReg &val, ThreadID tid)
1265{
1266 this->isa[tid]->setMiscRegNoEffect(misc_reg, val);
1267}
1268
1269template <class Impl>
1270void
1271FullO3CPU<Impl>::setMiscReg(int misc_reg,
1272 const TheISA::MiscReg &val, ThreadID tid)
1273{
1274 miscRegfileWrites++;
1275 this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid));
1276}
1277
1278template <class Impl>
1279uint64_t
1280FullO3CPU<Impl>::readIntReg(PhysRegIdPtr phys_reg)
1281{
1282 intRegfileReads++;
1283 return regFile.readIntReg(phys_reg);
1284}
1285
1286template <class Impl>
1287FloatReg
1288FullO3CPU<Impl>::readFloatReg(PhysRegIdPtr phys_reg)
1289{
1290 fpRegfileReads++;
1291 return regFile.readFloatReg(phys_reg);
1292}
1293
1294template <class Impl>
1295FloatRegBits
1296FullO3CPU<Impl>::readFloatRegBits(PhysRegIdPtr phys_reg)
1297{
1298 fpRegfileReads++;
1299 return regFile.readFloatRegBits(phys_reg);
1300}
1301
1302template <class Impl>
1303auto
1304FullO3CPU<Impl>::readVecReg(PhysRegIdPtr phys_reg) const
1305 -> const VecRegContainer&
1306{
1307 vecRegfileReads++;
1308 return regFile.readVecReg(phys_reg);
1309}
1310
1311template <class Impl>
1312auto
1313FullO3CPU<Impl>::getWritableVecReg(PhysRegIdPtr phys_reg)
1314 -> VecRegContainer&
1315{
1316 vecRegfileWrites++;
1317 return regFile.getWritableVecReg(phys_reg);
1318}
1319
1320template <class Impl>
1321auto
1322FullO3CPU<Impl>::readVecElem(PhysRegIdPtr phys_reg) const -> const VecElem&
1323{
1324 vecRegfileReads++;
1325 return regFile.readVecElem(phys_reg);
1326}
1327
1328template <class Impl>
1329CCReg
1330FullO3CPU<Impl>::readCCReg(PhysRegIdPtr phys_reg)
1331{
1332 ccRegfileReads++;
1333 return regFile.readCCReg(phys_reg);
1334}
1335
1336template <class Impl>
1337void
1338FullO3CPU<Impl>::setIntReg(PhysRegIdPtr phys_reg, uint64_t val)
1339{
1340 intRegfileWrites++;
1341 regFile.setIntReg(phys_reg, val);
1342}
1343
1344template <class Impl>
1345void
1346FullO3CPU<Impl>::setFloatReg(PhysRegIdPtr phys_reg, FloatReg val)
1347{
1348 fpRegfileWrites++;
1349 regFile.setFloatReg(phys_reg, val);
1350}
1351
1352template <class Impl>
1353void
1354FullO3CPU<Impl>::setFloatRegBits(PhysRegIdPtr phys_reg, FloatRegBits val)
1355{
1356 fpRegfileWrites++;
1357 regFile.setFloatRegBits(phys_reg, val);
1358}
1359
1360template <class Impl>
1361void
1362FullO3CPU<Impl>::setVecReg(PhysRegIdPtr phys_reg, const VecRegContainer& val)
1363{
1364 vecRegfileWrites++;
1365 regFile.setVecReg(phys_reg, val);
1366}
1367
1368template <class Impl>
1369void
1370FullO3CPU<Impl>::setVecElem(PhysRegIdPtr phys_reg, const VecElem& val)
1371{
1372 vecRegfileWrites++;
1373 regFile.setVecElem(phys_reg, val);
1374}
1375
1376template <class Impl>
1377void
1378FullO3CPU<Impl>::setCCReg(PhysRegIdPtr phys_reg, CCReg val)
1379{
1380 ccRegfileWrites++;
1381 regFile.setCCReg(phys_reg, val);
1382}
1383
1384template <class Impl>
1385uint64_t
1386FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1387{
1388 intRegfileReads++;
1389 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1390 RegId(IntRegClass, reg_idx));
1391
1392 return regFile.readIntReg(phys_reg);
1393}
1394
1395template <class Impl>
1396float
1397FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
1398{
1399 fpRegfileReads++;
1400 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1401 RegId(FloatRegClass, reg_idx));
1402
1403 return regFile.readFloatReg(phys_reg);
1404}
1405
1406template <class Impl>
1407uint64_t
1408FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid)
1409{
1410 fpRegfileReads++;
1411 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1412 RegId(FloatRegClass, reg_idx));
1413
1414 return regFile.readFloatRegBits(phys_reg);
1415}
1416
1417template <class Impl>
1418auto
1419FullO3CPU<Impl>::readArchVecReg(int reg_idx, ThreadID tid) const
1420 -> const VecRegContainer&
1421{
1422 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1423 RegId(VecRegClass, reg_idx));
1424 return readVecReg(phys_reg);
1425}
1426
1427template <class Impl>
1428auto
1429FullO3CPU<Impl>::getWritableArchVecReg(int reg_idx, ThreadID tid)
1430 -> VecRegContainer&
1431{
1432 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1433 RegId(VecRegClass, reg_idx));
1434 return getWritableVecReg(phys_reg);
1435}
1436
1437template <class Impl>
1438auto
1439FullO3CPU<Impl>::readArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
1440 ThreadID tid) const -> const VecElem&
1441{
1442 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1443 RegId(VecRegClass, reg_idx, ldx));
1444 return readVecElem(phys_reg);
1445}
1446
1447template <class Impl>
1448CCReg
1449FullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid)
1450{
1451 ccRegfileReads++;
1452 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1453 RegId(CCRegClass, reg_idx));
1454
1455 return regFile.readCCReg(phys_reg);
1456}
1457
1458template <class Impl>
1459void
1460FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
1461{
1462 intRegfileWrites++;
1463 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1464 RegId(IntRegClass, reg_idx));
1465
1466 regFile.setIntReg(phys_reg, val);
1467}
1468
1469template <class Impl>
1470void
1471FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid)
1472{
1473 fpRegfileWrites++;
1474 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1475 RegId(FloatRegClass, reg_idx));
1476
1477 regFile.setFloatReg(phys_reg, val);
1478}
1479
1480template <class Impl>
1481void
1482FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid)
1483{
1484 fpRegfileWrites++;
1485 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1486 RegId(FloatRegClass, reg_idx));
1487
1488 regFile.setFloatRegBits(phys_reg, val);
1489}
1490
1491template <class Impl>
1492void
1493FullO3CPU<Impl>::setArchVecReg(int reg_idx, const VecRegContainer& val,
1494 ThreadID tid)
1495{
1496 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1497 RegId(VecRegClass, reg_idx));
1498 setVecReg(phys_reg, val);
1499}
1500
1501template <class Impl>
1502void
1503FullO3CPU<Impl>::setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
1504 const VecElem& val, ThreadID tid)
1505{
1506 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1507 RegId(VecRegClass, reg_idx, ldx));
1508 setVecElem(phys_reg, val);
1509}
1510
1511template <class Impl>
1512void
1513FullO3CPU<Impl>::setArchCCReg(int reg_idx, CCReg val, ThreadID tid)
1514{
1515 ccRegfileWrites++;
1516 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1517 RegId(CCRegClass, reg_idx));
1518
1519 regFile.setCCReg(phys_reg, val);
1520}
1521
1522template <class Impl>
1523TheISA::PCState
1524FullO3CPU<Impl>::pcState(ThreadID tid)
1525{
1526 return commit.pcState(tid);
1527}
1528
1529template <class Impl>
1530void
1531FullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid)
1532{
1533 commit.pcState(val, tid);
1534}
1535
1536template <class Impl>
1537Addr
1538FullO3CPU<Impl>::instAddr(ThreadID tid)
1539{
1540 return commit.instAddr(tid);
1541}
1542
1543template <class Impl>
1544Addr
1545FullO3CPU<Impl>::nextInstAddr(ThreadID tid)
1546{
1547 return commit.nextInstAddr(tid);
1548}
1549
1550template <class Impl>
1551MicroPC
1552FullO3CPU<Impl>::microPC(ThreadID tid)
1553{
1554 return commit.microPC(tid);
1555}
1556
1557template <class Impl>
1558void
1559FullO3CPU<Impl>::squashFromTC(ThreadID tid)
1560{
1561 this->thread[tid]->noSquashFromTC = true;
1562 this->commit.generateTCEvent(tid);
1563}
1564
1565template <class Impl>
1566typename FullO3CPU<Impl>::ListIt
1567FullO3CPU<Impl>::addInst(DynInstPtr &inst)
1568{
1569 instList.push_back(inst);
1570
1571 return --(instList.end());
1572}
1573
1574template <class Impl>
1575void
1576FullO3CPU<Impl>::instDone(ThreadID tid, DynInstPtr &inst)
1577{
1578 // Keep an instruction count.
1579 if (!inst->isMicroop() || inst->isLastMicroop()) {
1580 thread[tid]->numInst++;
1581 thread[tid]->numInsts++;
1582 committedInsts[tid]++;
1583 system->totalNumInsts++;
1584
1585 // Check for instruction-count-based events.
1586 comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1587 system->instEventQueue.serviceEvents(system->totalNumInsts);
1588 }
1589 thread[tid]->numOp++;
1590 thread[tid]->numOps++;
1591 committedOps[tid]++;
1592
1593 probeInstCommit(inst->staticInst);
1594}
1595
1596template <class Impl>
1597void
1598FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
1599{
1600 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s "
1601 "[sn:%lli]\n",
1602 inst->threadNumber, inst->pcState(), inst->seqNum);
1603
1604 removeInstsThisCycle = true;
1605
1606 // Remove the front instruction.
1607 removeList.push(inst->getInstListIt());
1608}
1609
1610template <class Impl>
1611void
1612FullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid)
1613{
1614 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1615 " list.\n", tid);
1616
1617 ListIt end_it;
1618
1619 bool rob_empty = false;
1620
1621 if (instList.empty()) {
1622 return;
1623 } else if (rob.isEmpty(tid)) {
1624 DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1625 end_it = instList.begin();
1626 rob_empty = true;
1627 } else {
1628 end_it = (rob.readTailInst(tid))->getInstListIt();
1629 DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1630 }
1631
1632 removeInstsThisCycle = true;
1633
1634 ListIt inst_it = instList.end();
1635
1636 inst_it--;
1637
1638 // Walk through the instruction list, removing any instructions
1639 // that were inserted after the given instruction iterator, end_it.
1640 while (inst_it != end_it) {
1641 assert(!instList.empty());
1642
1643 squashInstIt(inst_it, tid);
1644
1645 inst_it--;
1646 }
1647
1648 // If the ROB was empty, then we actually need to remove the first
1649 // instruction as well.
1650 if (rob_empty) {
1651 squashInstIt(inst_it, tid);
1652 }
1653}
1654
1655template <class Impl>
1656void
1657FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1658{
1659 assert(!instList.empty());
1660
1661 removeInstsThisCycle = true;
1662
1663 ListIt inst_iter = instList.end();
1664
1665 inst_iter--;
1666
1667 DPRINTF(O3CPU, "Deleting instructions from instruction "
1668 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1669 tid, seq_num, (*inst_iter)->seqNum);
1670
1671 while ((*inst_iter)->seqNum > seq_num) {
1672
1673 bool break_loop = (inst_iter == instList.begin());
1674
1675 squashInstIt(inst_iter, tid);
1676
1677 inst_iter--;
1678
1679 if (break_loop)
1680 break;
1681 }
1682}
1683
1684template <class Impl>
1685inline void
1686FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid)
1687{
1688 if ((*instIt)->threadNumber == tid) {
1689 DPRINTF(O3CPU, "Squashing instruction, "
1690 "[tid:%i] [sn:%lli] PC %s\n",
1691 (*instIt)->threadNumber,
1692 (*instIt)->seqNum,
1693 (*instIt)->pcState());
1694
1695 // Mark it as squashed.
1696 (*instIt)->setSquashed();
1697
1698 // @todo: Formulate a consistent method for deleting
1699 // instructions from the instruction list
1700 // Remove the instruction from the list.
1701 removeList.push(instIt);
1702 }
1703}
1704
1705template <class Impl>
1706void
1707FullO3CPU<Impl>::cleanUpRemovedInsts()
1708{
1709 while (!removeList.empty()) {
1710 DPRINTF(O3CPU, "Removing instruction, "
1711 "[tid:%i] [sn:%lli] PC %s\n",
1712 (*removeList.front())->threadNumber,
1713 (*removeList.front())->seqNum,
1714 (*removeList.front())->pcState());
1715
1716 instList.erase(removeList.front());
1717
1718 removeList.pop();
1719 }
1720
1721 removeInstsThisCycle = false;
1722}
1723/*
1724template <class Impl>
1725void
1726FullO3CPU<Impl>::removeAllInsts()
1727{
1728 instList.clear();
1729}
1730*/
1731template <class Impl>
1732void
1733FullO3CPU<Impl>::dumpInsts()
1734{
1735 int num = 0;
1736
1737 ListIt inst_list_it = instList.begin();
1738
1739 cprintf("Dumping Instruction List\n");
1740
1741 while (inst_list_it != instList.end()) {
1742 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1743 "Squashed:%i\n\n",
1744 num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber,
1745 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1746 (*inst_list_it)->isSquashed());
1747 inst_list_it++;
1748 ++num;
1749 }
1750}
1751/*
1752template <class Impl>
1753void
1754FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
1755{
1756 iew.wakeDependents(inst);
1757}
1758*/
1759template <class Impl>
1760void
1761FullO3CPU<Impl>::wakeCPU()
1762{
1763 if (activityRec.active() || tickEvent.scheduled()) {
1764 DPRINTF(Activity, "CPU already running.\n");
1765 return;
1766 }
1767
1768 DPRINTF(Activity, "Waking up CPU\n");
1769
1770 Cycles cycles(curCycle() - lastRunningCycle);
1771 // @todo: This is an oddity that is only here to match the stats
1772 if (cycles > 1) {
1773 --cycles;
1774 idleCycles += cycles;
1775 numCycles += cycles;
|