165#ifndef NDEBUG
166 instcount(0),
167#endif
168 removeInstsThisCycle(false),
169 fetch(this, params),
170 decode(this, params),
171 rename(this, params),
172 iew(this, params),
173 commit(this, params),
174
175 /* It is mandatory that all SMT threads use the same renaming mode as
176 * they are sharing registers and rename */
177 vecMode(initRenameMode<TheISA::ISA>::mode(params->isa[0])),
178 regFile(params->numPhysIntRegs,
179 params->numPhysFloatRegs,
180 params->numPhysVecRegs,
181 params->numPhysCCRegs,
182 vecMode),
183
184 freeList(name() + ".freelist", ®File),
185
186 rob(this, params),
187
188 scoreboard(name() + ".scoreboard",
189 regFile.totalNumPhysRegs()),
190
191 isa(numThreads, NULL),
192
193 icachePort(&fetch, this),
194 dcachePort(&iew.ldstQueue, this),
195
196 timeBuffer(params->backComSize, params->forwardComSize),
197 fetchQueue(params->backComSize, params->forwardComSize),
198 decodeQueue(params->backComSize, params->forwardComSize),
199 renameQueue(params->backComSize, params->forwardComSize),
200 iewQueue(params->backComSize, params->forwardComSize),
201 activityRec(name(), NumStages,
202 params->backComSize + params->forwardComSize,
203 params->activity),
204
205 globalSeqNum(1),
206 system(params->system),
207 lastRunningCycle(curCycle())
208{
209 if (!params->switched_out) {
210 _status = Running;
211 } else {
212 _status = SwitchedOut;
213 }
214
215 if (params->checker) {
216 BaseCPU *temp_checker = params->checker;
217 checker = dynamic_cast<Checker<Impl> *>(temp_checker);
218 checker->setIcachePort(&icachePort);
219 checker->setSystem(params->system);
220 } else {
221 checker = NULL;
222 }
223
224 if (!FullSystem) {
225 thread.resize(numThreads);
226 tids.resize(numThreads);
227 }
228
229 // The stages also need their CPU pointer setup. However this
230 // must be done at the upper level CPU because they have pointers
231 // to the upper level CPU, and not this FullO3CPU.
232
233 // Set up Pointers to the activeThreads list for each stage
234 fetch.setActiveThreads(&activeThreads);
235 decode.setActiveThreads(&activeThreads);
236 rename.setActiveThreads(&activeThreads);
237 iew.setActiveThreads(&activeThreads);
238 commit.setActiveThreads(&activeThreads);
239
240 // Give each of the stages the time buffer they will use.
241 fetch.setTimeBuffer(&timeBuffer);
242 decode.setTimeBuffer(&timeBuffer);
243 rename.setTimeBuffer(&timeBuffer);
244 iew.setTimeBuffer(&timeBuffer);
245 commit.setTimeBuffer(&timeBuffer);
246
247 // Also setup each of the stages' queues.
248 fetch.setFetchQueue(&fetchQueue);
249 decode.setFetchQueue(&fetchQueue);
250 commit.setFetchQueue(&fetchQueue);
251 decode.setDecodeQueue(&decodeQueue);
252 rename.setDecodeQueue(&decodeQueue);
253 rename.setRenameQueue(&renameQueue);
254 iew.setRenameQueue(&renameQueue);
255 iew.setIEWQueue(&iewQueue);
256 commit.setIEWQueue(&iewQueue);
257 commit.setRenameQueue(&renameQueue);
258
259 commit.setIEWStage(&iew);
260 rename.setIEWStage(&iew);
261 rename.setCommitStage(&commit);
262
263 ThreadID active_threads;
264 if (FullSystem) {
265 active_threads = 1;
266 } else {
267 active_threads = params->workload.size();
268
269 if (active_threads > Impl::MaxThreads) {
270 panic("Workload Size too large. Increase the 'MaxThreads' "
271 "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) "
272 "or edit your workload size.");
273 }
274 }
275
276 //Make Sure That this a Valid Architeture
277 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs);
278 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
279 assert(params->numPhysVecRegs >= numThreads * TheISA::NumVecRegs);
280 assert(params->numPhysCCRegs >= numThreads * TheISA::NumCCRegs);
281
282 rename.setScoreboard(&scoreboard);
283 iew.setScoreboard(&scoreboard);
284
285 // Setup the rename map for whichever stages need it.
286 for (ThreadID tid = 0; tid < numThreads; tid++) {
287 isa[tid] = params->isa[tid];
288 assert(initRenameMode<TheISA::ISA>::equals(isa[tid], isa[0]));
289
290 // Only Alpha has an FP zero register, so for other ISAs we
291 // use an invalid FP register index to avoid special treatment
292 // of any valid FP reg.
293 RegIndex invalidFPReg = TheISA::NumFloatRegs + 1;
294 RegIndex fpZeroReg =
295 (THE_ISA == ALPHA_ISA) ? TheISA::ZeroReg : invalidFPReg;
296
297 commitRenameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg,
298 &freeList,
299 vecMode);
300
301 renameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg,
302 &freeList, vecMode);
303 }
304
305 // Initialize rename map to assign physical registers to the
306 // architectural registers for active threads only.
307 for (ThreadID tid = 0; tid < active_threads; tid++) {
308 for (RegIndex ridx = 0; ridx < TheISA::NumIntRegs; ++ridx) {
309 // Note that we can't use the rename() method because we don't
310 // want special treatment for the zero register at this point
311 PhysRegIdPtr phys_reg = freeList.getIntReg();
312 renameMap[tid].setEntry(RegId(IntRegClass, ridx), phys_reg);
313 commitRenameMap[tid].setEntry(RegId(IntRegClass, ridx), phys_reg);
314 }
315
316 for (RegIndex ridx = 0; ridx < TheISA::NumFloatRegs; ++ridx) {
317 PhysRegIdPtr phys_reg = freeList.getFloatReg();
318 renameMap[tid].setEntry(RegId(FloatRegClass, ridx), phys_reg);
319 commitRenameMap[tid].setEntry(
320 RegId(FloatRegClass, ridx), phys_reg);
321 }
322
323 /* Here we need two 'interfaces' the 'whole register' and the
324 * 'register element'. At any point only one of them will be
325 * active. */
326 if (vecMode == Enums::Full) {
327 /* Initialize the full-vector interface */
328 for (RegIndex ridx = 0; ridx < TheISA::NumVecRegs; ++ridx) {
329 RegId rid = RegId(VecRegClass, ridx);
330 PhysRegIdPtr phys_reg = freeList.getVecReg();
331 renameMap[tid].setEntry(rid, phys_reg);
332 commitRenameMap[tid].setEntry(rid, phys_reg);
333 }
334 } else {
335 /* Initialize the vector-element interface */
336 for (RegIndex ridx = 0; ridx < TheISA::NumVecRegs; ++ridx) {
337 for (ElemIndex ldx = 0; ldx < TheISA::NumVecElemPerVecReg;
338 ++ldx) {
339 RegId lrid = RegId(VecElemClass, ridx, ldx);
340 PhysRegIdPtr phys_elem = freeList.getVecElem();
341 renameMap[tid].setEntry(lrid, phys_elem);
342 commitRenameMap[tid].setEntry(lrid, phys_elem);
343 }
344 }
345 }
346
347 for (RegIndex ridx = 0; ridx < TheISA::NumCCRegs; ++ridx) {
348 PhysRegIdPtr phys_reg = freeList.getCCReg();
349 renameMap[tid].setEntry(RegId(CCRegClass, ridx), phys_reg);
350 commitRenameMap[tid].setEntry(RegId(CCRegClass, ridx), phys_reg);
351 }
352 }
353
354 rename.setRenameMap(renameMap);
355 commit.setRenameMap(commitRenameMap);
356 rename.setFreeList(&freeList);
357
358 // Setup the ROB for whichever stages need it.
359 commit.setROB(&rob);
360
361 lastActivatedCycle = 0;
362#if 0
363 // Give renameMap & rename stage access to the freeList;
364 for (ThreadID tid = 0; tid < numThreads; tid++)
365 globalSeqNum[tid] = 1;
366#endif
367
368 DPRINTF(O3CPU, "Creating O3CPU object.\n");
369
370 // Setup any thread state.
371 this->thread.resize(this->numThreads);
372
373 for (ThreadID tid = 0; tid < this->numThreads; ++tid) {
374 if (FullSystem) {
375 // SMT is not supported in FS mode yet.
376 assert(this->numThreads == 1);
377 this->thread[tid] = new Thread(this, 0, NULL);
378 } else {
379 if (tid < params->workload.size()) {
380 DPRINTF(O3CPU, "Workload[%i] process is %#x",
381 tid, this->thread[tid]);
382 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
383 (typename Impl::O3CPU *)(this),
384 tid, params->workload[tid]);
385
386 //usedTids[tid] = true;
387 //threadMap[tid] = tid;
388 } else {
389 //Allocate Empty thread so M5 can use later
390 //when scheduling threads to CPU
391 Process* dummy_proc = NULL;
392
393 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
394 (typename Impl::O3CPU *)(this),
395 tid, dummy_proc);
396 //usedTids[tid] = false;
397 }
398 }
399
400 ThreadContext *tc;
401
402 // Setup the TC that will serve as the interface to the threads/CPU.
403 O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>;
404
405 tc = o3_tc;
406
407 // If we're using a checker, then the TC should be the
408 // CheckerThreadContext.
409 if (params->checker) {
410 tc = new CheckerThreadContext<O3ThreadContext<Impl> >(
411 o3_tc, this->checker);
412 }
413
414 o3_tc->cpu = (typename Impl::O3CPU *)(this);
415 assert(o3_tc->cpu);
416 o3_tc->thread = this->thread[tid];
417
418 // Setup quiesce event.
419 this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
420
421 // Give the thread the TC.
422 this->thread[tid]->tc = tc;
423
424 // Add the TC to the CPU's list of TC's.
425 this->threadContexts.push_back(tc);
426 }
427
428 // FullO3CPU always requires an interrupt controller.
429 if (!params->switched_out && interrupts.empty()) {
430 fatal("FullO3CPU %s has no interrupt controller.\n"
431 "Ensure createInterruptController() is called.\n", name());
432 }
433
434 for (ThreadID tid = 0; tid < this->numThreads; tid++)
435 this->thread[tid]->setFuncExeInst(0);
436}
437
438template <class Impl>
439FullO3CPU<Impl>::~FullO3CPU()
440{
441}
442
443template <class Impl>
444void
445FullO3CPU<Impl>::regProbePoints()
446{
447 BaseCPU::regProbePoints();
448
449 ppInstAccessComplete = new ProbePointArg<PacketPtr>(getProbeManager(), "InstAccessComplete");
450 ppDataAccessComplete = new ProbePointArg<std::pair<DynInstPtr, PacketPtr> >(getProbeManager(), "DataAccessComplete");
451
452 fetch.regProbePoints();
453 rename.regProbePoints();
454 iew.regProbePoints();
455 commit.regProbePoints();
456}
457
458template <class Impl>
459void
460FullO3CPU<Impl>::regStats()
461{
462 BaseO3CPU::regStats();
463
464 // Register any of the O3CPU's stats here.
465 timesIdled
466 .name(name() + ".timesIdled")
467 .desc("Number of times that the entire CPU went into an idle state and"
468 " unscheduled itself")
469 .prereq(timesIdled);
470
471 idleCycles
472 .name(name() + ".idleCycles")
473 .desc("Total number of cycles that the CPU has spent unscheduled due "
474 "to idling")
475 .prereq(idleCycles);
476
477 quiesceCycles
478 .name(name() + ".quiesceCycles")
479 .desc("Total number of cycles that CPU has spent quiesced or waiting "
480 "for an interrupt")
481 .prereq(quiesceCycles);
482
483 // Number of Instructions simulated
484 // --------------------------------
485 // Should probably be in Base CPU but need templated
486 // MaxThreads so put in here instead
487 committedInsts
488 .init(numThreads)
489 .name(name() + ".committedInsts")
490 .desc("Number of Instructions Simulated")
491 .flags(Stats::total);
492
493 committedOps
494 .init(numThreads)
495 .name(name() + ".committedOps")
496 .desc("Number of Ops (including micro ops) Simulated")
497 .flags(Stats::total);
498
499 cpi
500 .name(name() + ".cpi")
501 .desc("CPI: Cycles Per Instruction")
502 .precision(6);
503 cpi = numCycles / committedInsts;
504
505 totalCpi
506 .name(name() + ".cpi_total")
507 .desc("CPI: Total CPI of All Threads")
508 .precision(6);
509 totalCpi = numCycles / sum(committedInsts);
510
511 ipc
512 .name(name() + ".ipc")
513 .desc("IPC: Instructions Per Cycle")
514 .precision(6);
515 ipc = committedInsts / numCycles;
516
517 totalIpc
518 .name(name() + ".ipc_total")
519 .desc("IPC: Total IPC of All Threads")
520 .precision(6);
521 totalIpc = sum(committedInsts) / numCycles;
522
523 this->fetch.regStats();
524 this->decode.regStats();
525 this->rename.regStats();
526 this->iew.regStats();
527 this->commit.regStats();
528 this->rob.regStats();
529
530 intRegfileReads
531 .name(name() + ".int_regfile_reads")
532 .desc("number of integer regfile reads")
533 .prereq(intRegfileReads);
534
535 intRegfileWrites
536 .name(name() + ".int_regfile_writes")
537 .desc("number of integer regfile writes")
538 .prereq(intRegfileWrites);
539
540 fpRegfileReads
541 .name(name() + ".fp_regfile_reads")
542 .desc("number of floating regfile reads")
543 .prereq(fpRegfileReads);
544
545 fpRegfileWrites
546 .name(name() + ".fp_regfile_writes")
547 .desc("number of floating regfile writes")
548 .prereq(fpRegfileWrites);
549
550 vecRegfileReads
551 .name(name() + ".vec_regfile_reads")
552 .desc("number of vector regfile reads")
553 .prereq(vecRegfileReads);
554
555 vecRegfileWrites
556 .name(name() + ".vec_regfile_writes")
557 .desc("number of vector regfile writes")
558 .prereq(vecRegfileWrites);
559
560 ccRegfileReads
561 .name(name() + ".cc_regfile_reads")
562 .desc("number of cc regfile reads")
563 .prereq(ccRegfileReads);
564
565 ccRegfileWrites
566 .name(name() + ".cc_regfile_writes")
567 .desc("number of cc regfile writes")
568 .prereq(ccRegfileWrites);
569
570 miscRegfileReads
571 .name(name() + ".misc_regfile_reads")
572 .desc("number of misc regfile reads")
573 .prereq(miscRegfileReads);
574
575 miscRegfileWrites
576 .name(name() + ".misc_regfile_writes")
577 .desc("number of misc regfile writes")
578 .prereq(miscRegfileWrites);
579}
580
581template <class Impl>
582void
583FullO3CPU<Impl>::tick()
584{
585 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
586 assert(!switchedOut());
587 assert(drainState() != DrainState::Drained);
588
589 ++numCycles;
590 ppCycles->notify(1);
591
592// activity = false;
593
594 //Tick each of the stages
595 fetch.tick();
596
597 decode.tick();
598
599 rename.tick();
600
601 iew.tick();
602
603 commit.tick();
604
605 // Now advance the time buffers
606 timeBuffer.advance();
607
608 fetchQueue.advance();
609 decodeQueue.advance();
610 renameQueue.advance();
611 iewQueue.advance();
612
613 activityRec.advance();
614
615 if (removeInstsThisCycle) {
616 cleanUpRemovedInsts();
617 }
618
619 if (!tickEvent.scheduled()) {
620 if (_status == SwitchedOut) {
621 DPRINTF(O3CPU, "Switched out!\n");
622 // increment stat
623 lastRunningCycle = curCycle();
624 } else if (!activityRec.active() || _status == Idle) {
625 DPRINTF(O3CPU, "Idle!\n");
626 lastRunningCycle = curCycle();
627 timesIdled++;
628 } else {
629 schedule(tickEvent, clockEdge(Cycles(1)));
630 DPRINTF(O3CPU, "Scheduling next tick!\n");
631 }
632 }
633
634 if (!FullSystem)
635 updateThreadPriority();
636
637 tryDrain();
638}
639
640template <class Impl>
641void
642FullO3CPU<Impl>::init()
643{
644 BaseCPU::init();
645
646 for (ThreadID tid = 0; tid < numThreads; ++tid) {
647 // Set noSquashFromTC so that the CPU doesn't squash when initially
648 // setting up registers.
649 thread[tid]->noSquashFromTC = true;
650 // Initialise the ThreadContext's memory proxies
651 thread[tid]->initMemProxies(thread[tid]->getTC());
652 }
653
654 if (FullSystem && !params()->switched_out) {
655 for (ThreadID tid = 0; tid < numThreads; tid++) {
656 ThreadContext *src_tc = threadContexts[tid];
657 TheISA::initCPU(src_tc, src_tc->contextId());
658 }
659 }
660
661 // Clear noSquashFromTC.
662 for (int tid = 0; tid < numThreads; ++tid)
663 thread[tid]->noSquashFromTC = false;
664
665 commit.setThreads(thread);
666}
667
668template <class Impl>
669void
670FullO3CPU<Impl>::startup()
671{
672 BaseCPU::startup();
673 for (int tid = 0; tid < numThreads; ++tid)
674 isa[tid]->startup(threadContexts[tid]);
675
676 fetch.startupStage();
677 decode.startupStage();
678 iew.startupStage();
679 rename.startupStage();
680 commit.startupStage();
681}
682
683template <class Impl>
684void
685FullO3CPU<Impl>::activateThread(ThreadID tid)
686{
687 list<ThreadID>::iterator isActive =
688 std::find(activeThreads.begin(), activeThreads.end(), tid);
689
690 DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid);
691 assert(!switchedOut());
692
693 if (isActive == activeThreads.end()) {
694 DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n",
695 tid);
696
697 activeThreads.push_back(tid);
698 }
699}
700
701template <class Impl>
702void
703FullO3CPU<Impl>::deactivateThread(ThreadID tid)
704{
705 //Remove From Active List, if Active
706 list<ThreadID>::iterator thread_it =
707 std::find(activeThreads.begin(), activeThreads.end(), tid);
708
709 DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid);
710 assert(!switchedOut());
711
712 if (thread_it != activeThreads.end()) {
713 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
714 tid);
715 activeThreads.erase(thread_it);
716 }
717
718 fetch.deactivateThread(tid);
719 commit.deactivateThread(tid);
720}
721
722template <class Impl>
723Counter
724FullO3CPU<Impl>::totalInsts() const
725{
726 Counter total(0);
727
728 ThreadID size = thread.size();
729 for (ThreadID i = 0; i < size; i++)
730 total += thread[i]->numInst;
731
732 return total;
733}
734
735template <class Impl>
736Counter
737FullO3CPU<Impl>::totalOps() const
738{
739 Counter total(0);
740
741 ThreadID size = thread.size();
742 for (ThreadID i = 0; i < size; i++)
743 total += thread[i]->numOp;
744
745 return total;
746}
747
748template <class Impl>
749void
750FullO3CPU<Impl>::activateContext(ThreadID tid)
751{
752 assert(!switchedOut());
753
754 // Needs to set each stage to running as well.
755 activateThread(tid);
756
757 // We don't want to wake the CPU if it is drained. In that case,
758 // we just want to flag the thread as active and schedule the tick
759 // event from drainResume() instead.
760 if (drainState() == DrainState::Drained)
761 return;
762
763 // If we are time 0 or if the last activation time is in the past,
764 // schedule the next tick and wake up the fetch unit
765 if (lastActivatedCycle == 0 || lastActivatedCycle < curTick()) {
766 scheduleTickEvent(Cycles(0));
767
768 // Be sure to signal that there's some activity so the CPU doesn't
769 // deschedule itself.
770 activityRec.activity();
771 fetch.wakeFromQuiesce();
772
773 Cycles cycles(curCycle() - lastRunningCycle);
774 // @todo: This is an oddity that is only here to match the stats
775 if (cycles != 0)
776 --cycles;
777 quiesceCycles += cycles;
778
779 lastActivatedCycle = curTick();
780
781 _status = Running;
782
783 BaseCPU::activateContext(tid);
784 }
785}
786
787template <class Impl>
788void
789FullO3CPU<Impl>::suspendContext(ThreadID tid)
790{
791 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
792 assert(!switchedOut());
793
794 deactivateThread(tid);
795
796 // If this was the last thread then unschedule the tick event.
797 if (activeThreads.size() == 0) {
798 unscheduleTickEvent();
799 lastRunningCycle = curCycle();
800 _status = Idle;
801 }
802
803 DPRINTF(Quiesce, "Suspending Context\n");
804
805 BaseCPU::suspendContext(tid);
806}
807
808template <class Impl>
809void
810FullO3CPU<Impl>::haltContext(ThreadID tid)
811{
812 //For now, this is the same as deallocate
813 DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
814 assert(!switchedOut());
815
816 deactivateThread(tid);
817 removeThread(tid);
818}
819
820template <class Impl>
821void
822FullO3CPU<Impl>::insertThread(ThreadID tid)
823{
824 DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
825 // Will change now that the PC and thread state is internal to the CPU
826 // and not in the ThreadContext.
827 ThreadContext *src_tc;
828 if (FullSystem)
829 src_tc = system->threadContexts[tid];
830 else
831 src_tc = tcBase(tid);
832
833 //Bind Int Regs to Rename Map
834
835 for (RegId reg_id(IntRegClass, 0); reg_id.index() < TheISA::NumIntRegs;
836 reg_id.index()++) {
837 PhysRegIdPtr phys_reg = freeList.getIntReg();
838 renameMap[tid].setEntry(reg_id, phys_reg);
839 scoreboard.setReg(phys_reg);
840 }
841
842 //Bind Float Regs to Rename Map
843 for (RegId reg_id(FloatRegClass, 0); reg_id.index() < TheISA::NumFloatRegs;
844 reg_id.index()++) {
845 PhysRegIdPtr phys_reg = freeList.getFloatReg();
846 renameMap[tid].setEntry(reg_id, phys_reg);
847 scoreboard.setReg(phys_reg);
848 }
849
850 //Bind condition-code Regs to Rename Map
851 for (RegId reg_id(CCRegClass, 0); reg_id.index() < TheISA::NumCCRegs;
852 reg_id.index()++) {
853 PhysRegIdPtr phys_reg = freeList.getCCReg();
854 renameMap[tid].setEntry(reg_id, phys_reg);
855 scoreboard.setReg(phys_reg);
856 }
857
858 //Copy Thread Data Into RegFile
859 //this->copyFromTC(tid);
860
861 //Set PC/NPC/NNPC
862 pcState(src_tc->pcState(), tid);
863
864 src_tc->setStatus(ThreadContext::Active);
865
866 activateContext(tid);
867
868 //Reset ROB/IQ/LSQ Entries
869 commit.rob->resetEntries();
870 iew.resetEntries();
871}
872
873template <class Impl>
874void
875FullO3CPU<Impl>::removeThread(ThreadID tid)
876{
877 DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
878
879 // Copy Thread Data From RegFile
880 // If thread is suspended, it might be re-allocated
881 // this->copyToTC(tid);
882
883
884 // @todo: 2-27-2008: Fix how we free up rename mappings
885 // here to alleviate the case for double-freeing registers
886 // in SMT workloads.
887
888 // Unbind Int Regs from Rename Map
889 for (RegId reg_id(IntRegClass, 0); reg_id.index() < TheISA::NumIntRegs;
890 reg_id.index()++) {
891 PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id);
892 scoreboard.unsetReg(phys_reg);
893 freeList.addReg(phys_reg);
894 }
895
896 // Unbind Float Regs from Rename Map
897 for (RegId reg_id(FloatRegClass, 0); reg_id.index() < TheISA::NumFloatRegs;
898 reg_id.index()++) {
899 PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id);
900 scoreboard.unsetReg(phys_reg);
901 freeList.addReg(phys_reg);
902 }
903
904 // Unbind condition-code Regs from Rename Map
905 for (RegId reg_id(CCRegClass, 0); reg_id.index() < TheISA::NumCCRegs;
906 reg_id.index()++) {
907 PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id);
908 scoreboard.unsetReg(phys_reg);
909 freeList.addReg(phys_reg);
910 }
911
912 // Squash Throughout Pipeline
913 DynInstPtr inst = commit.rob->readHeadInst(tid);
914 InstSeqNum squash_seq_num = inst->seqNum;
915 fetch.squash(0, squash_seq_num, inst, tid);
916 decode.squash(tid);
917 rename.squash(squash_seq_num, tid);
918 iew.squash(tid);
919 iew.ldstQueue.squash(squash_seq_num, tid);
920 commit.rob->squash(squash_seq_num, tid);
921
922
923 assert(iew.instQueue.getCount(tid) == 0);
924 assert(iew.ldstQueue.getCount(tid) == 0);
925
926 // Reset ROB/IQ/LSQ Entries
927
928 // Commented out for now. This should be possible to do by
929 // telling all the pipeline stages to drain first, and then
930 // checking until the drain completes. Once the pipeline is
931 // drained, call resetEntries(). - 10-09-06 ktlim
932/*
933 if (activeThreads.size() >= 1) {
934 commit.rob->resetEntries();
935 iew.resetEntries();
936 }
937*/
938}
939
940template <class Impl>
941Fault
942FullO3CPU<Impl>::hwrei(ThreadID tid)
943{
944#if THE_ISA == ALPHA_ISA
945 // Need to clear the lock flag upon returning from an interrupt.
946 this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
947
948 this->thread[tid]->kernelStats->hwrei();
949
950 // FIXME: XXX check for interrupts? XXX
951#endif
952 return NoFault;
953}
954
955template <class Impl>
956bool
957FullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid)
958{
959#if THE_ISA == ALPHA_ISA
960 if (this->thread[tid]->kernelStats)
961 this->thread[tid]->kernelStats->callpal(palFunc,
962 this->threadContexts[tid]);
963
964 switch (palFunc) {
965 case PAL::halt:
966 halt();
967 if (--System::numSystemsRunning == 0)
968 exitSimLoop("all cpus halted");
969 break;
970
971 case PAL::bpt:
972 case PAL::bugchk:
973 if (this->system->breakpoint())
974 return false;
975 break;
976 }
977#endif
978 return true;
979}
980
981template <class Impl>
982Fault
983FullO3CPU<Impl>::getInterrupts()
984{
985 // Check if there are any outstanding interrupts
986 return this->interrupts[0]->getInterrupt(this->threadContexts[0]);
987}
988
989template <class Impl>
990void
991FullO3CPU<Impl>::processInterrupts(const Fault &interrupt)
992{
993 // Check for interrupts here. For now can copy the code that
994 // exists within isa_fullsys_traits.hh. Also assume that thread 0
995 // is the one that handles the interrupts.
996 // @todo: Possibly consolidate the interrupt checking code.
997 // @todo: Allow other threads to handle interrupts.
998
999 assert(interrupt != NoFault);
1000 this->interrupts[0]->updateIntrInfo(this->threadContexts[0]);
1001
1002 DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
1003 this->trap(interrupt, 0, nullptr);
1004}
1005
1006template <class Impl>
1007void
1008FullO3CPU<Impl>::trap(const Fault &fault, ThreadID tid,
1009 const StaticInstPtr &inst)
1010{
1011 // Pass the thread's TC into the invoke method.
1012 fault->invoke(this->threadContexts[tid], inst);
1013}
1014
1015template <class Impl>
1016void
1017FullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid, Fault *fault)
1018{
1019 DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid);
1020
1021 DPRINTF(Activity,"Activity: syscall() called.\n");
1022
1023 // Temporarily increase this by one to account for the syscall
1024 // instruction.
1025 ++(this->thread[tid]->funcExeInst);
1026
1027 // Execute the actual syscall.
1028 this->thread[tid]->syscall(callnum, fault);
1029
1030 // Decrease funcExeInst by one as the normal commit will handle
1031 // incrementing it.
1032 --(this->thread[tid]->funcExeInst);
1033}
1034
1035template <class Impl>
1036void
1037FullO3CPU<Impl>::serializeThread(CheckpointOut &cp, ThreadID tid) const
1038{
1039 thread[tid]->serialize(cp);
1040}
1041
1042template <class Impl>
1043void
1044FullO3CPU<Impl>::unserializeThread(CheckpointIn &cp, ThreadID tid)
1045{
1046 thread[tid]->unserialize(cp);
1047}
1048
1049template <class Impl>
1050DrainState
1051FullO3CPU<Impl>::drain()
1052{
1053 // If the CPU isn't doing anything, then return immediately.
1054 if (switchedOut())
1055 return DrainState::Drained;
1056
1057 DPRINTF(Drain, "Draining...\n");
1058
1059 // We only need to signal a drain to the commit stage as this
1060 // initiates squashing controls the draining. Once the commit
1061 // stage commits an instruction where it is safe to stop, it'll
1062 // squash the rest of the instructions in the pipeline and force
1063 // the fetch stage to stall. The pipeline will be drained once all
1064 // in-flight instructions have retired.
1065 commit.drain();
1066
1067 // Wake the CPU and record activity so everything can drain out if
1068 // the CPU was not able to immediately drain.
1069 if (!isDrained()) {
1070 wakeCPU();
1071 activityRec.activity();
1072
1073 DPRINTF(Drain, "CPU not drained\n");
1074
1075 return DrainState::Draining;
1076 } else {
1077 DPRINTF(Drain, "CPU is already drained\n");
1078 if (tickEvent.scheduled())
1079 deschedule(tickEvent);
1080
1081 // Flush out any old data from the time buffers. In
1082 // particular, there might be some data in flight from the
1083 // fetch stage that isn't visible in any of the CPU buffers we
1084 // test in isDrained().
1085 for (int i = 0; i < timeBuffer.getSize(); ++i) {
1086 timeBuffer.advance();
1087 fetchQueue.advance();
1088 decodeQueue.advance();
1089 renameQueue.advance();
1090 iewQueue.advance();
1091 }
1092
1093 drainSanityCheck();
1094 return DrainState::Drained;
1095 }
1096}
1097
1098template <class Impl>
1099bool
1100FullO3CPU<Impl>::tryDrain()
1101{
1102 if (drainState() != DrainState::Draining || !isDrained())
1103 return false;
1104
1105 if (tickEvent.scheduled())
1106 deschedule(tickEvent);
1107
1108 DPRINTF(Drain, "CPU done draining, processing drain event\n");
1109 signalDrainDone();
1110
1111 return true;
1112}
1113
1114template <class Impl>
1115void
1116FullO3CPU<Impl>::drainSanityCheck() const
1117{
1118 assert(isDrained());
1119 fetch.drainSanityCheck();
1120 decode.drainSanityCheck();
1121 rename.drainSanityCheck();
1122 iew.drainSanityCheck();
1123 commit.drainSanityCheck();
1124}
1125
1126template <class Impl>
1127bool
1128FullO3CPU<Impl>::isDrained() const
1129{
1130 bool drained(true);
1131
1132 if (!instList.empty() || !removeList.empty()) {
1133 DPRINTF(Drain, "Main CPU structures not drained.\n");
1134 drained = false;
1135 }
1136
1137 if (!fetch.isDrained()) {
1138 DPRINTF(Drain, "Fetch not drained.\n");
1139 drained = false;
1140 }
1141
1142 if (!decode.isDrained()) {
1143 DPRINTF(Drain, "Decode not drained.\n");
1144 drained = false;
1145 }
1146
1147 if (!rename.isDrained()) {
1148 DPRINTF(Drain, "Rename not drained.\n");
1149 drained = false;
1150 }
1151
1152 if (!iew.isDrained()) {
1153 DPRINTF(Drain, "IEW not drained.\n");
1154 drained = false;
1155 }
1156
1157 if (!commit.isDrained()) {
1158 DPRINTF(Drain, "Commit not drained.\n");
1159 drained = false;
1160 }
1161
1162 return drained;
1163}
1164
1165template <class Impl>
1166void
1167FullO3CPU<Impl>::commitDrained(ThreadID tid)
1168{
1169 fetch.drainStall(tid);
1170}
1171
1172template <class Impl>
1173void
1174FullO3CPU<Impl>::drainResume()
1175{
1176 if (switchedOut())
1177 return;
1178
1179 DPRINTF(Drain, "Resuming...\n");
1180 verifyMemoryMode();
1181
1182 fetch.drainResume();
1183 commit.drainResume();
1184
1185 _status = Idle;
1186 for (ThreadID i = 0; i < thread.size(); i++) {
1187 if (thread[i]->status() == ThreadContext::Active) {
1188 DPRINTF(Drain, "Activating thread: %i\n", i);
1189 activateThread(i);
1190 _status = Running;
1191 }
1192 }
1193
1194 assert(!tickEvent.scheduled());
1195 if (_status == Running)
1196 schedule(tickEvent, nextCycle());
1197}
1198
1199template <class Impl>
1200void
1201FullO3CPU<Impl>::switchOut()
1202{
1203 DPRINTF(O3CPU, "Switching out\n");
1204 BaseCPU::switchOut();
1205
1206 activityRec.reset();
1207
1208 _status = SwitchedOut;
1209
1210 if (checker)
1211 checker->switchOut();
1212}
1213
1214template <class Impl>
1215void
1216FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
1217{
1218 BaseCPU::takeOverFrom(oldCPU);
1219
1220 fetch.takeOverFrom();
1221 decode.takeOverFrom();
1222 rename.takeOverFrom();
1223 iew.takeOverFrom();
1224 commit.takeOverFrom();
1225
1226 assert(!tickEvent.scheduled());
1227
1228 FullO3CPU<Impl> *oldO3CPU = dynamic_cast<FullO3CPU<Impl>*>(oldCPU);
1229 if (oldO3CPU)
1230 globalSeqNum = oldO3CPU->globalSeqNum;
1231
1232 lastRunningCycle = curCycle();
1233 _status = Idle;
1234}
1235
1236template <class Impl>
1237void
1238FullO3CPU<Impl>::verifyMemoryMode() const
1239{
1240 if (!system->isTimingMode()) {
1241 fatal("The O3 CPU requires the memory system to be in "
1242 "'timing' mode.\n");
1243 }
1244}
1245
1246template <class Impl>
1247TheISA::MiscReg
1248FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
1249{
1250 return this->isa[tid]->readMiscRegNoEffect(misc_reg);
1251}
1252
1253template <class Impl>
1254TheISA::MiscReg
1255FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
1256{
1257 miscRegfileReads++;
1258 return this->isa[tid]->readMiscReg(misc_reg, tcBase(tid));
1259}
1260
1261template <class Impl>
1262void
1263FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
1264 const TheISA::MiscReg &val, ThreadID tid)
1265{
1266 this->isa[tid]->setMiscRegNoEffect(misc_reg, val);
1267}
1268
1269template <class Impl>
1270void
1271FullO3CPU<Impl>::setMiscReg(int misc_reg,
1272 const TheISA::MiscReg &val, ThreadID tid)
1273{
1274 miscRegfileWrites++;
1275 this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid));
1276}
1277
1278template <class Impl>
1279uint64_t
1280FullO3CPU<Impl>::readIntReg(PhysRegIdPtr phys_reg)
1281{
1282 intRegfileReads++;
1283 return regFile.readIntReg(phys_reg);
1284}
1285
1286template <class Impl>
1287FloatReg
1288FullO3CPU<Impl>::readFloatReg(PhysRegIdPtr phys_reg)
1289{
1290 fpRegfileReads++;
1291 return regFile.readFloatReg(phys_reg);
1292}
1293
1294template <class Impl>
1295FloatRegBits
1296FullO3CPU<Impl>::readFloatRegBits(PhysRegIdPtr phys_reg)
1297{
1298 fpRegfileReads++;
1299 return regFile.readFloatRegBits(phys_reg);
1300}
1301
1302template <class Impl>
1303auto
1304FullO3CPU<Impl>::readVecReg(PhysRegIdPtr phys_reg) const
1305 -> const VecRegContainer&
1306{
1307 vecRegfileReads++;
1308 return regFile.readVecReg(phys_reg);
1309}
1310
1311template <class Impl>
1312auto
1313FullO3CPU<Impl>::getWritableVecReg(PhysRegIdPtr phys_reg)
1314 -> VecRegContainer&
1315{
1316 vecRegfileWrites++;
1317 return regFile.getWritableVecReg(phys_reg);
1318}
1319
1320template <class Impl>
1321auto
1322FullO3CPU<Impl>::readVecElem(PhysRegIdPtr phys_reg) const -> const VecElem&
1323{
1324 vecRegfileReads++;
1325 return regFile.readVecElem(phys_reg);
1326}
1327
1328template <class Impl>
1329CCReg
1330FullO3CPU<Impl>::readCCReg(PhysRegIdPtr phys_reg)
1331{
1332 ccRegfileReads++;
1333 return regFile.readCCReg(phys_reg);
1334}
1335
1336template <class Impl>
1337void
1338FullO3CPU<Impl>::setIntReg(PhysRegIdPtr phys_reg, uint64_t val)
1339{
1340 intRegfileWrites++;
1341 regFile.setIntReg(phys_reg, val);
1342}
1343
1344template <class Impl>
1345void
1346FullO3CPU<Impl>::setFloatReg(PhysRegIdPtr phys_reg, FloatReg val)
1347{
1348 fpRegfileWrites++;
1349 regFile.setFloatReg(phys_reg, val);
1350}
1351
1352template <class Impl>
1353void
1354FullO3CPU<Impl>::setFloatRegBits(PhysRegIdPtr phys_reg, FloatRegBits val)
1355{
1356 fpRegfileWrites++;
1357 regFile.setFloatRegBits(phys_reg, val);
1358}
1359
1360template <class Impl>
1361void
1362FullO3CPU<Impl>::setVecReg(PhysRegIdPtr phys_reg, const VecRegContainer& val)
1363{
1364 vecRegfileWrites++;
1365 regFile.setVecReg(phys_reg, val);
1366}
1367
1368template <class Impl>
1369void
1370FullO3CPU<Impl>::setVecElem(PhysRegIdPtr phys_reg, const VecElem& val)
1371{
1372 vecRegfileWrites++;
1373 regFile.setVecElem(phys_reg, val);
1374}
1375
1376template <class Impl>
1377void
1378FullO3CPU<Impl>::setCCReg(PhysRegIdPtr phys_reg, CCReg val)
1379{
1380 ccRegfileWrites++;
1381 regFile.setCCReg(phys_reg, val);
1382}
1383
1384template <class Impl>
1385uint64_t
1386FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1387{
1388 intRegfileReads++;
1389 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1390 RegId(IntRegClass, reg_idx));
1391
1392 return regFile.readIntReg(phys_reg);
1393}
1394
1395template <class Impl>
1396float
1397FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
1398{
1399 fpRegfileReads++;
1400 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1401 RegId(FloatRegClass, reg_idx));
1402
1403 return regFile.readFloatReg(phys_reg);
1404}
1405
1406template <class Impl>
1407uint64_t
1408FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid)
1409{
1410 fpRegfileReads++;
1411 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1412 RegId(FloatRegClass, reg_idx));
1413
1414 return regFile.readFloatRegBits(phys_reg);
1415}
1416
1417template <class Impl>
1418auto
1419FullO3CPU<Impl>::readArchVecReg(int reg_idx, ThreadID tid) const
1420 -> const VecRegContainer&
1421{
1422 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1423 RegId(VecRegClass, reg_idx));
1424 return readVecReg(phys_reg);
1425}
1426
1427template <class Impl>
1428auto
1429FullO3CPU<Impl>::getWritableArchVecReg(int reg_idx, ThreadID tid)
1430 -> VecRegContainer&
1431{
1432 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1433 RegId(VecRegClass, reg_idx));
1434 return getWritableVecReg(phys_reg);
1435}
1436
1437template <class Impl>
1438auto
1439FullO3CPU<Impl>::readArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
1440 ThreadID tid) const -> const VecElem&
1441{
1442 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1443 RegId(VecRegClass, reg_idx, ldx));
1444 return readVecElem(phys_reg);
1445}
1446
1447template <class Impl>
1448CCReg
1449FullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid)
1450{
1451 ccRegfileReads++;
1452 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1453 RegId(CCRegClass, reg_idx));
1454
1455 return regFile.readCCReg(phys_reg);
1456}
1457
1458template <class Impl>
1459void
1460FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
1461{
1462 intRegfileWrites++;
1463 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1464 RegId(IntRegClass, reg_idx));
1465
1466 regFile.setIntReg(phys_reg, val);
1467}
1468
1469template <class Impl>
1470void
1471FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid)
1472{
1473 fpRegfileWrites++;
1474 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1475 RegId(FloatRegClass, reg_idx));
1476
1477 regFile.setFloatReg(phys_reg, val);
1478}
1479
1480template <class Impl>
1481void
1482FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid)
1483{
1484 fpRegfileWrites++;
1485 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1486 RegId(FloatRegClass, reg_idx));
1487
1488 regFile.setFloatRegBits(phys_reg, val);
1489}
1490
1491template <class Impl>
1492void
1493FullO3CPU<Impl>::setArchVecReg(int reg_idx, const VecRegContainer& val,
1494 ThreadID tid)
1495{
1496 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1497 RegId(VecRegClass, reg_idx));
1498 setVecReg(phys_reg, val);
1499}
1500
1501template <class Impl>
1502void
1503FullO3CPU<Impl>::setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
1504 const VecElem& val, ThreadID tid)
1505{
1506 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1507 RegId(VecRegClass, reg_idx, ldx));
1508 setVecElem(phys_reg, val);
1509}
1510
1511template <class Impl>
1512void
1513FullO3CPU<Impl>::setArchCCReg(int reg_idx, CCReg val, ThreadID tid)
1514{
1515 ccRegfileWrites++;
1516 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1517 RegId(CCRegClass, reg_idx));
1518
1519 regFile.setCCReg(phys_reg, val);
1520}
1521
1522template <class Impl>
1523TheISA::PCState
1524FullO3CPU<Impl>::pcState(ThreadID tid)
1525{
1526 return commit.pcState(tid);
1527}
1528
1529template <class Impl>
1530void
1531FullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid)
1532{
1533 commit.pcState(val, tid);
1534}
1535
1536template <class Impl>
1537Addr
1538FullO3CPU<Impl>::instAddr(ThreadID tid)
1539{
1540 return commit.instAddr(tid);
1541}
1542
1543template <class Impl>
1544Addr
1545FullO3CPU<Impl>::nextInstAddr(ThreadID tid)
1546{
1547 return commit.nextInstAddr(tid);
1548}
1549
1550template <class Impl>
1551MicroPC
1552FullO3CPU<Impl>::microPC(ThreadID tid)
1553{
1554 return commit.microPC(tid);
1555}
1556
1557template <class Impl>
1558void
1559FullO3CPU<Impl>::squashFromTC(ThreadID tid)
1560{
1561 this->thread[tid]->noSquashFromTC = true;
1562 this->commit.generateTCEvent(tid);
1563}
1564
1565template <class Impl>
1566typename FullO3CPU<Impl>::ListIt
1567FullO3CPU<Impl>::addInst(DynInstPtr &inst)
1568{
1569 instList.push_back(inst);
1570
1571 return --(instList.end());
1572}
1573
1574template <class Impl>
1575void
1576FullO3CPU<Impl>::instDone(ThreadID tid, DynInstPtr &inst)
1577{
1578 // Keep an instruction count.
1579 if (!inst->isMicroop() || inst->isLastMicroop()) {
1580 thread[tid]->numInst++;
1581 thread[tid]->numInsts++;
1582 committedInsts[tid]++;
1583 system->totalNumInsts++;
1584
1585 // Check for instruction-count-based events.
1586 comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1587 system->instEventQueue.serviceEvents(system->totalNumInsts);
1588 }
1589 thread[tid]->numOp++;
1590 thread[tid]->numOps++;
1591 committedOps[tid]++;
1592
1593 probeInstCommit(inst->staticInst);
1594}
1595
1596template <class Impl>
1597void
1598FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
1599{
1600 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s "
1601 "[sn:%lli]\n",
1602 inst->threadNumber, inst->pcState(), inst->seqNum);
1603
1604 removeInstsThisCycle = true;
1605
1606 // Remove the front instruction.
1607 removeList.push(inst->getInstListIt());
1608}
1609
1610template <class Impl>
1611void
1612FullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid)
1613{
1614 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1615 " list.\n", tid);
1616
1617 ListIt end_it;
1618
1619 bool rob_empty = false;
1620
1621 if (instList.empty()) {
1622 return;
1623 } else if (rob.isEmpty(tid)) {
1624 DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1625 end_it = instList.begin();
1626 rob_empty = true;
1627 } else {
1628 end_it = (rob.readTailInst(tid))->getInstListIt();
1629 DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1630 }
1631
1632 removeInstsThisCycle = true;
1633
1634 ListIt inst_it = instList.end();
1635
1636 inst_it--;
1637
1638 // Walk through the instruction list, removing any instructions
1639 // that were inserted after the given instruction iterator, end_it.
1640 while (inst_it != end_it) {
1641 assert(!instList.empty());
1642
1643 squashInstIt(inst_it, tid);
1644
1645 inst_it--;
1646 }
1647
1648 // If the ROB was empty, then we actually need to remove the first
1649 // instruction as well.
1650 if (rob_empty) {
1651 squashInstIt(inst_it, tid);
1652 }
1653}
1654
1655template <class Impl>
1656void
1657FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1658{
1659 assert(!instList.empty());
1660
1661 removeInstsThisCycle = true;
1662
1663 ListIt inst_iter = instList.end();
1664
1665 inst_iter--;
1666
1667 DPRINTF(O3CPU, "Deleting instructions from instruction "
1668 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1669 tid, seq_num, (*inst_iter)->seqNum);
1670
1671 while ((*inst_iter)->seqNum > seq_num) {
1672
1673 bool break_loop = (inst_iter == instList.begin());
1674
1675 squashInstIt(inst_iter, tid);
1676
1677 inst_iter--;
1678
1679 if (break_loop)
1680 break;
1681 }
1682}
1683
1684template <class Impl>
1685inline void
1686FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid)
1687{
1688 if ((*instIt)->threadNumber == tid) {
1689 DPRINTF(O3CPU, "Squashing instruction, "
1690 "[tid:%i] [sn:%lli] PC %s\n",
1691 (*instIt)->threadNumber,
1692 (*instIt)->seqNum,
1693 (*instIt)->pcState());
1694
1695 // Mark it as squashed.
1696 (*instIt)->setSquashed();
1697
1698 // @todo: Formulate a consistent method for deleting
1699 // instructions from the instruction list
1700 // Remove the instruction from the list.
1701 removeList.push(instIt);
1702 }
1703}
1704
1705template <class Impl>
1706void
1707FullO3CPU<Impl>::cleanUpRemovedInsts()
1708{
1709 while (!removeList.empty()) {
1710 DPRINTF(O3CPU, "Removing instruction, "
1711 "[tid:%i] [sn:%lli] PC %s\n",
1712 (*removeList.front())->threadNumber,
1713 (*removeList.front())->seqNum,
1714 (*removeList.front())->pcState());
1715
1716 instList.erase(removeList.front());
1717
1718 removeList.pop();
1719 }
1720
1721 removeInstsThisCycle = false;
1722}
1723/*
1724template <class Impl>
1725void
1726FullO3CPU<Impl>::removeAllInsts()
1727{
1728 instList.clear();
1729}
1730*/
1731template <class Impl>
1732void
1733FullO3CPU<Impl>::dumpInsts()
1734{
1735 int num = 0;
1736
1737 ListIt inst_list_it = instList.begin();
1738
1739 cprintf("Dumping Instruction List\n");
1740
1741 while (inst_list_it != instList.end()) {
1742 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1743 "Squashed:%i\n\n",
1744 num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber,
1745 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1746 (*inst_list_it)->isSquashed());
1747 inst_list_it++;
1748 ++num;
1749 }
1750}
1751/*
1752template <class Impl>
1753void
1754FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
1755{
1756 iew.wakeDependents(inst);
1757}
1758*/
1759template <class Impl>
1760void
1761FullO3CPU<Impl>::wakeCPU()
1762{
1763 if (activityRec.active() || tickEvent.scheduled()) {
1764 DPRINTF(Activity, "CPU already running.\n");
1765 return;
1766 }
1767
1768 DPRINTF(Activity, "Waking up CPU\n");
1769
1770 Cycles cycles(curCycle() - lastRunningCycle);
1771 // @todo: This is an oddity that is only here to match the stats
1772 if (cycles > 1) {
1773 --cycles;
1774 idleCycles += cycles;
1775 numCycles += cycles;
1776 ppCycles->notify(cycles);
1777 }
1778
1779 schedule(tickEvent, clockEdge());
1780}
1781
1782template <class Impl>
1783void
1784FullO3CPU<Impl>::wakeup(ThreadID tid)
1785{
1786 if (this->thread[tid]->status() != ThreadContext::Suspended)
1787 return;
1788
1789 this->wakeCPU();
1790
1791 DPRINTF(Quiesce, "Suspended Processor woken\n");
1792 this->threadContexts[tid]->activate();
1793}
1794
1795template <class Impl>
1796ThreadID
1797FullO3CPU<Impl>::getFreeTid()
1798{
1799 for (ThreadID tid = 0; tid < numThreads; tid++) {
1800 if (!tids[tid]) {
1801 tids[tid] = true;
1802 return tid;
1803 }
1804 }
1805
1806 return InvalidThreadID;
1807}
1808
1809template <class Impl>
1810void
1811FullO3CPU<Impl>::updateThreadPriority()
1812{
1813 if (activeThreads.size() > 1) {
1814 //DEFAULT TO ROUND ROBIN SCHEME
1815 //e.g. Move highest priority to end of thread list
1816 list<ThreadID>::iterator list_begin = activeThreads.begin();
1817
1818 unsigned high_thread = *list_begin;
1819
1820 activeThreads.erase(list_begin);
1821
1822 activeThreads.push_back(high_thread);
1823 }
1824}
1825
1826// Forward declaration of FullO3CPU.
1827template class FullO3CPU<O3CPUImpl>;
| 146#ifndef NDEBUG
147 instcount(0),
148#endif
149 removeInstsThisCycle(false),
150 fetch(this, params),
151 decode(this, params),
152 rename(this, params),
153 iew(this, params),
154 commit(this, params),
155
156 /* It is mandatory that all SMT threads use the same renaming mode as
157 * they are sharing registers and rename */
158 vecMode(initRenameMode<TheISA::ISA>::mode(params->isa[0])),
159 regFile(params->numPhysIntRegs,
160 params->numPhysFloatRegs,
161 params->numPhysVecRegs,
162 params->numPhysCCRegs,
163 vecMode),
164
165 freeList(name() + ".freelist", ®File),
166
167 rob(this, params),
168
169 scoreboard(name() + ".scoreboard",
170 regFile.totalNumPhysRegs()),
171
172 isa(numThreads, NULL),
173
174 icachePort(&fetch, this),
175 dcachePort(&iew.ldstQueue, this),
176
177 timeBuffer(params->backComSize, params->forwardComSize),
178 fetchQueue(params->backComSize, params->forwardComSize),
179 decodeQueue(params->backComSize, params->forwardComSize),
180 renameQueue(params->backComSize, params->forwardComSize),
181 iewQueue(params->backComSize, params->forwardComSize),
182 activityRec(name(), NumStages,
183 params->backComSize + params->forwardComSize,
184 params->activity),
185
186 globalSeqNum(1),
187 system(params->system),
188 lastRunningCycle(curCycle())
189{
190 if (!params->switched_out) {
191 _status = Running;
192 } else {
193 _status = SwitchedOut;
194 }
195
196 if (params->checker) {
197 BaseCPU *temp_checker = params->checker;
198 checker = dynamic_cast<Checker<Impl> *>(temp_checker);
199 checker->setIcachePort(&icachePort);
200 checker->setSystem(params->system);
201 } else {
202 checker = NULL;
203 }
204
205 if (!FullSystem) {
206 thread.resize(numThreads);
207 tids.resize(numThreads);
208 }
209
210 // The stages also need their CPU pointer setup. However this
211 // must be done at the upper level CPU because they have pointers
212 // to the upper level CPU, and not this FullO3CPU.
213
214 // Set up Pointers to the activeThreads list for each stage
215 fetch.setActiveThreads(&activeThreads);
216 decode.setActiveThreads(&activeThreads);
217 rename.setActiveThreads(&activeThreads);
218 iew.setActiveThreads(&activeThreads);
219 commit.setActiveThreads(&activeThreads);
220
221 // Give each of the stages the time buffer they will use.
222 fetch.setTimeBuffer(&timeBuffer);
223 decode.setTimeBuffer(&timeBuffer);
224 rename.setTimeBuffer(&timeBuffer);
225 iew.setTimeBuffer(&timeBuffer);
226 commit.setTimeBuffer(&timeBuffer);
227
228 // Also setup each of the stages' queues.
229 fetch.setFetchQueue(&fetchQueue);
230 decode.setFetchQueue(&fetchQueue);
231 commit.setFetchQueue(&fetchQueue);
232 decode.setDecodeQueue(&decodeQueue);
233 rename.setDecodeQueue(&decodeQueue);
234 rename.setRenameQueue(&renameQueue);
235 iew.setRenameQueue(&renameQueue);
236 iew.setIEWQueue(&iewQueue);
237 commit.setIEWQueue(&iewQueue);
238 commit.setRenameQueue(&renameQueue);
239
240 commit.setIEWStage(&iew);
241 rename.setIEWStage(&iew);
242 rename.setCommitStage(&commit);
243
244 ThreadID active_threads;
245 if (FullSystem) {
246 active_threads = 1;
247 } else {
248 active_threads = params->workload.size();
249
250 if (active_threads > Impl::MaxThreads) {
251 panic("Workload Size too large. Increase the 'MaxThreads' "
252 "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) "
253 "or edit your workload size.");
254 }
255 }
256
257 //Make Sure That this a Valid Architeture
258 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs);
259 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
260 assert(params->numPhysVecRegs >= numThreads * TheISA::NumVecRegs);
261 assert(params->numPhysCCRegs >= numThreads * TheISA::NumCCRegs);
262
263 rename.setScoreboard(&scoreboard);
264 iew.setScoreboard(&scoreboard);
265
266 // Setup the rename map for whichever stages need it.
267 for (ThreadID tid = 0; tid < numThreads; tid++) {
268 isa[tid] = params->isa[tid];
269 assert(initRenameMode<TheISA::ISA>::equals(isa[tid], isa[0]));
270
271 // Only Alpha has an FP zero register, so for other ISAs we
272 // use an invalid FP register index to avoid special treatment
273 // of any valid FP reg.
274 RegIndex invalidFPReg = TheISA::NumFloatRegs + 1;
275 RegIndex fpZeroReg =
276 (THE_ISA == ALPHA_ISA) ? TheISA::ZeroReg : invalidFPReg;
277
278 commitRenameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg,
279 &freeList,
280 vecMode);
281
282 renameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg,
283 &freeList, vecMode);
284 }
285
286 // Initialize rename map to assign physical registers to the
287 // architectural registers for active threads only.
288 for (ThreadID tid = 0; tid < active_threads; tid++) {
289 for (RegIndex ridx = 0; ridx < TheISA::NumIntRegs; ++ridx) {
290 // Note that we can't use the rename() method because we don't
291 // want special treatment for the zero register at this point
292 PhysRegIdPtr phys_reg = freeList.getIntReg();
293 renameMap[tid].setEntry(RegId(IntRegClass, ridx), phys_reg);
294 commitRenameMap[tid].setEntry(RegId(IntRegClass, ridx), phys_reg);
295 }
296
297 for (RegIndex ridx = 0; ridx < TheISA::NumFloatRegs; ++ridx) {
298 PhysRegIdPtr phys_reg = freeList.getFloatReg();
299 renameMap[tid].setEntry(RegId(FloatRegClass, ridx), phys_reg);
300 commitRenameMap[tid].setEntry(
301 RegId(FloatRegClass, ridx), phys_reg);
302 }
303
304 /* Here we need two 'interfaces' the 'whole register' and the
305 * 'register element'. At any point only one of them will be
306 * active. */
307 if (vecMode == Enums::Full) {
308 /* Initialize the full-vector interface */
309 for (RegIndex ridx = 0; ridx < TheISA::NumVecRegs; ++ridx) {
310 RegId rid = RegId(VecRegClass, ridx);
311 PhysRegIdPtr phys_reg = freeList.getVecReg();
312 renameMap[tid].setEntry(rid, phys_reg);
313 commitRenameMap[tid].setEntry(rid, phys_reg);
314 }
315 } else {
316 /* Initialize the vector-element interface */
317 for (RegIndex ridx = 0; ridx < TheISA::NumVecRegs; ++ridx) {
318 for (ElemIndex ldx = 0; ldx < TheISA::NumVecElemPerVecReg;
319 ++ldx) {
320 RegId lrid = RegId(VecElemClass, ridx, ldx);
321 PhysRegIdPtr phys_elem = freeList.getVecElem();
322 renameMap[tid].setEntry(lrid, phys_elem);
323 commitRenameMap[tid].setEntry(lrid, phys_elem);
324 }
325 }
326 }
327
328 for (RegIndex ridx = 0; ridx < TheISA::NumCCRegs; ++ridx) {
329 PhysRegIdPtr phys_reg = freeList.getCCReg();
330 renameMap[tid].setEntry(RegId(CCRegClass, ridx), phys_reg);
331 commitRenameMap[tid].setEntry(RegId(CCRegClass, ridx), phys_reg);
332 }
333 }
334
335 rename.setRenameMap(renameMap);
336 commit.setRenameMap(commitRenameMap);
337 rename.setFreeList(&freeList);
338
339 // Setup the ROB for whichever stages need it.
340 commit.setROB(&rob);
341
342 lastActivatedCycle = 0;
343#if 0
344 // Give renameMap & rename stage access to the freeList;
345 for (ThreadID tid = 0; tid < numThreads; tid++)
346 globalSeqNum[tid] = 1;
347#endif
348
349 DPRINTF(O3CPU, "Creating O3CPU object.\n");
350
351 // Setup any thread state.
352 this->thread.resize(this->numThreads);
353
354 for (ThreadID tid = 0; tid < this->numThreads; ++tid) {
355 if (FullSystem) {
356 // SMT is not supported in FS mode yet.
357 assert(this->numThreads == 1);
358 this->thread[tid] = new Thread(this, 0, NULL);
359 } else {
360 if (tid < params->workload.size()) {
361 DPRINTF(O3CPU, "Workload[%i] process is %#x",
362 tid, this->thread[tid]);
363 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
364 (typename Impl::O3CPU *)(this),
365 tid, params->workload[tid]);
366
367 //usedTids[tid] = true;
368 //threadMap[tid] = tid;
369 } else {
370 //Allocate Empty thread so M5 can use later
371 //when scheduling threads to CPU
372 Process* dummy_proc = NULL;
373
374 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
375 (typename Impl::O3CPU *)(this),
376 tid, dummy_proc);
377 //usedTids[tid] = false;
378 }
379 }
380
381 ThreadContext *tc;
382
383 // Setup the TC that will serve as the interface to the threads/CPU.
384 O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>;
385
386 tc = o3_tc;
387
388 // If we're using a checker, then the TC should be the
389 // CheckerThreadContext.
390 if (params->checker) {
391 tc = new CheckerThreadContext<O3ThreadContext<Impl> >(
392 o3_tc, this->checker);
393 }
394
395 o3_tc->cpu = (typename Impl::O3CPU *)(this);
396 assert(o3_tc->cpu);
397 o3_tc->thread = this->thread[tid];
398
399 // Setup quiesce event.
400 this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
401
402 // Give the thread the TC.
403 this->thread[tid]->tc = tc;
404
405 // Add the TC to the CPU's list of TC's.
406 this->threadContexts.push_back(tc);
407 }
408
409 // FullO3CPU always requires an interrupt controller.
410 if (!params->switched_out && interrupts.empty()) {
411 fatal("FullO3CPU %s has no interrupt controller.\n"
412 "Ensure createInterruptController() is called.\n", name());
413 }
414
415 for (ThreadID tid = 0; tid < this->numThreads; tid++)
416 this->thread[tid]->setFuncExeInst(0);
417}
418
419template <class Impl>
420FullO3CPU<Impl>::~FullO3CPU()
421{
422}
423
424template <class Impl>
425void
426FullO3CPU<Impl>::regProbePoints()
427{
428 BaseCPU::regProbePoints();
429
430 ppInstAccessComplete = new ProbePointArg<PacketPtr>(getProbeManager(), "InstAccessComplete");
431 ppDataAccessComplete = new ProbePointArg<std::pair<DynInstPtr, PacketPtr> >(getProbeManager(), "DataAccessComplete");
432
433 fetch.regProbePoints();
434 rename.regProbePoints();
435 iew.regProbePoints();
436 commit.regProbePoints();
437}
438
439template <class Impl>
440void
441FullO3CPU<Impl>::regStats()
442{
443 BaseO3CPU::regStats();
444
445 // Register any of the O3CPU's stats here.
446 timesIdled
447 .name(name() + ".timesIdled")
448 .desc("Number of times that the entire CPU went into an idle state and"
449 " unscheduled itself")
450 .prereq(timesIdled);
451
452 idleCycles
453 .name(name() + ".idleCycles")
454 .desc("Total number of cycles that the CPU has spent unscheduled due "
455 "to idling")
456 .prereq(idleCycles);
457
458 quiesceCycles
459 .name(name() + ".quiesceCycles")
460 .desc("Total number of cycles that CPU has spent quiesced or waiting "
461 "for an interrupt")
462 .prereq(quiesceCycles);
463
464 // Number of Instructions simulated
465 // --------------------------------
466 // Should probably be in Base CPU but need templated
467 // MaxThreads so put in here instead
468 committedInsts
469 .init(numThreads)
470 .name(name() + ".committedInsts")
471 .desc("Number of Instructions Simulated")
472 .flags(Stats::total);
473
474 committedOps
475 .init(numThreads)
476 .name(name() + ".committedOps")
477 .desc("Number of Ops (including micro ops) Simulated")
478 .flags(Stats::total);
479
480 cpi
481 .name(name() + ".cpi")
482 .desc("CPI: Cycles Per Instruction")
483 .precision(6);
484 cpi = numCycles / committedInsts;
485
486 totalCpi
487 .name(name() + ".cpi_total")
488 .desc("CPI: Total CPI of All Threads")
489 .precision(6);
490 totalCpi = numCycles / sum(committedInsts);
491
492 ipc
493 .name(name() + ".ipc")
494 .desc("IPC: Instructions Per Cycle")
495 .precision(6);
496 ipc = committedInsts / numCycles;
497
498 totalIpc
499 .name(name() + ".ipc_total")
500 .desc("IPC: Total IPC of All Threads")
501 .precision(6);
502 totalIpc = sum(committedInsts) / numCycles;
503
504 this->fetch.regStats();
505 this->decode.regStats();
506 this->rename.regStats();
507 this->iew.regStats();
508 this->commit.regStats();
509 this->rob.regStats();
510
511 intRegfileReads
512 .name(name() + ".int_regfile_reads")
513 .desc("number of integer regfile reads")
514 .prereq(intRegfileReads);
515
516 intRegfileWrites
517 .name(name() + ".int_regfile_writes")
518 .desc("number of integer regfile writes")
519 .prereq(intRegfileWrites);
520
521 fpRegfileReads
522 .name(name() + ".fp_regfile_reads")
523 .desc("number of floating regfile reads")
524 .prereq(fpRegfileReads);
525
526 fpRegfileWrites
527 .name(name() + ".fp_regfile_writes")
528 .desc("number of floating regfile writes")
529 .prereq(fpRegfileWrites);
530
531 vecRegfileReads
532 .name(name() + ".vec_regfile_reads")
533 .desc("number of vector regfile reads")
534 .prereq(vecRegfileReads);
535
536 vecRegfileWrites
537 .name(name() + ".vec_regfile_writes")
538 .desc("number of vector regfile writes")
539 .prereq(vecRegfileWrites);
540
541 ccRegfileReads
542 .name(name() + ".cc_regfile_reads")
543 .desc("number of cc regfile reads")
544 .prereq(ccRegfileReads);
545
546 ccRegfileWrites
547 .name(name() + ".cc_regfile_writes")
548 .desc("number of cc regfile writes")
549 .prereq(ccRegfileWrites);
550
551 miscRegfileReads
552 .name(name() + ".misc_regfile_reads")
553 .desc("number of misc regfile reads")
554 .prereq(miscRegfileReads);
555
556 miscRegfileWrites
557 .name(name() + ".misc_regfile_writes")
558 .desc("number of misc regfile writes")
559 .prereq(miscRegfileWrites);
560}
561
562template <class Impl>
563void
564FullO3CPU<Impl>::tick()
565{
566 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
567 assert(!switchedOut());
568 assert(drainState() != DrainState::Drained);
569
570 ++numCycles;
571 ppCycles->notify(1);
572
573// activity = false;
574
575 //Tick each of the stages
576 fetch.tick();
577
578 decode.tick();
579
580 rename.tick();
581
582 iew.tick();
583
584 commit.tick();
585
586 // Now advance the time buffers
587 timeBuffer.advance();
588
589 fetchQueue.advance();
590 decodeQueue.advance();
591 renameQueue.advance();
592 iewQueue.advance();
593
594 activityRec.advance();
595
596 if (removeInstsThisCycle) {
597 cleanUpRemovedInsts();
598 }
599
600 if (!tickEvent.scheduled()) {
601 if (_status == SwitchedOut) {
602 DPRINTF(O3CPU, "Switched out!\n");
603 // increment stat
604 lastRunningCycle = curCycle();
605 } else if (!activityRec.active() || _status == Idle) {
606 DPRINTF(O3CPU, "Idle!\n");
607 lastRunningCycle = curCycle();
608 timesIdled++;
609 } else {
610 schedule(tickEvent, clockEdge(Cycles(1)));
611 DPRINTF(O3CPU, "Scheduling next tick!\n");
612 }
613 }
614
615 if (!FullSystem)
616 updateThreadPriority();
617
618 tryDrain();
619}
620
621template <class Impl>
622void
623FullO3CPU<Impl>::init()
624{
625 BaseCPU::init();
626
627 for (ThreadID tid = 0; tid < numThreads; ++tid) {
628 // Set noSquashFromTC so that the CPU doesn't squash when initially
629 // setting up registers.
630 thread[tid]->noSquashFromTC = true;
631 // Initialise the ThreadContext's memory proxies
632 thread[tid]->initMemProxies(thread[tid]->getTC());
633 }
634
635 if (FullSystem && !params()->switched_out) {
636 for (ThreadID tid = 0; tid < numThreads; tid++) {
637 ThreadContext *src_tc = threadContexts[tid];
638 TheISA::initCPU(src_tc, src_tc->contextId());
639 }
640 }
641
642 // Clear noSquashFromTC.
643 for (int tid = 0; tid < numThreads; ++tid)
644 thread[tid]->noSquashFromTC = false;
645
646 commit.setThreads(thread);
647}
648
649template <class Impl>
650void
651FullO3CPU<Impl>::startup()
652{
653 BaseCPU::startup();
654 for (int tid = 0; tid < numThreads; ++tid)
655 isa[tid]->startup(threadContexts[tid]);
656
657 fetch.startupStage();
658 decode.startupStage();
659 iew.startupStage();
660 rename.startupStage();
661 commit.startupStage();
662}
663
664template <class Impl>
665void
666FullO3CPU<Impl>::activateThread(ThreadID tid)
667{
668 list<ThreadID>::iterator isActive =
669 std::find(activeThreads.begin(), activeThreads.end(), tid);
670
671 DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid);
672 assert(!switchedOut());
673
674 if (isActive == activeThreads.end()) {
675 DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n",
676 tid);
677
678 activeThreads.push_back(tid);
679 }
680}
681
682template <class Impl>
683void
684FullO3CPU<Impl>::deactivateThread(ThreadID tid)
685{
686 //Remove From Active List, if Active
687 list<ThreadID>::iterator thread_it =
688 std::find(activeThreads.begin(), activeThreads.end(), tid);
689
690 DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid);
691 assert(!switchedOut());
692
693 if (thread_it != activeThreads.end()) {
694 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
695 tid);
696 activeThreads.erase(thread_it);
697 }
698
699 fetch.deactivateThread(tid);
700 commit.deactivateThread(tid);
701}
702
703template <class Impl>
704Counter
705FullO3CPU<Impl>::totalInsts() const
706{
707 Counter total(0);
708
709 ThreadID size = thread.size();
710 for (ThreadID i = 0; i < size; i++)
711 total += thread[i]->numInst;
712
713 return total;
714}
715
716template <class Impl>
717Counter
718FullO3CPU<Impl>::totalOps() const
719{
720 Counter total(0);
721
722 ThreadID size = thread.size();
723 for (ThreadID i = 0; i < size; i++)
724 total += thread[i]->numOp;
725
726 return total;
727}
728
729template <class Impl>
730void
731FullO3CPU<Impl>::activateContext(ThreadID tid)
732{
733 assert(!switchedOut());
734
735 // Needs to set each stage to running as well.
736 activateThread(tid);
737
738 // We don't want to wake the CPU if it is drained. In that case,
739 // we just want to flag the thread as active and schedule the tick
740 // event from drainResume() instead.
741 if (drainState() == DrainState::Drained)
742 return;
743
744 // If we are time 0 or if the last activation time is in the past,
745 // schedule the next tick and wake up the fetch unit
746 if (lastActivatedCycle == 0 || lastActivatedCycle < curTick()) {
747 scheduleTickEvent(Cycles(0));
748
749 // Be sure to signal that there's some activity so the CPU doesn't
750 // deschedule itself.
751 activityRec.activity();
752 fetch.wakeFromQuiesce();
753
754 Cycles cycles(curCycle() - lastRunningCycle);
755 // @todo: This is an oddity that is only here to match the stats
756 if (cycles != 0)
757 --cycles;
758 quiesceCycles += cycles;
759
760 lastActivatedCycle = curTick();
761
762 _status = Running;
763
764 BaseCPU::activateContext(tid);
765 }
766}
767
768template <class Impl>
769void
770FullO3CPU<Impl>::suspendContext(ThreadID tid)
771{
772 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
773 assert(!switchedOut());
774
775 deactivateThread(tid);
776
777 // If this was the last thread then unschedule the tick event.
778 if (activeThreads.size() == 0) {
779 unscheduleTickEvent();
780 lastRunningCycle = curCycle();
781 _status = Idle;
782 }
783
784 DPRINTF(Quiesce, "Suspending Context\n");
785
786 BaseCPU::suspendContext(tid);
787}
788
789template <class Impl>
790void
791FullO3CPU<Impl>::haltContext(ThreadID tid)
792{
793 //For now, this is the same as deallocate
794 DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
795 assert(!switchedOut());
796
797 deactivateThread(tid);
798 removeThread(tid);
799}
800
801template <class Impl>
802void
803FullO3CPU<Impl>::insertThread(ThreadID tid)
804{
805 DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
806 // Will change now that the PC and thread state is internal to the CPU
807 // and not in the ThreadContext.
808 ThreadContext *src_tc;
809 if (FullSystem)
810 src_tc = system->threadContexts[tid];
811 else
812 src_tc = tcBase(tid);
813
814 //Bind Int Regs to Rename Map
815
816 for (RegId reg_id(IntRegClass, 0); reg_id.index() < TheISA::NumIntRegs;
817 reg_id.index()++) {
818 PhysRegIdPtr phys_reg = freeList.getIntReg();
819 renameMap[tid].setEntry(reg_id, phys_reg);
820 scoreboard.setReg(phys_reg);
821 }
822
823 //Bind Float Regs to Rename Map
824 for (RegId reg_id(FloatRegClass, 0); reg_id.index() < TheISA::NumFloatRegs;
825 reg_id.index()++) {
826 PhysRegIdPtr phys_reg = freeList.getFloatReg();
827 renameMap[tid].setEntry(reg_id, phys_reg);
828 scoreboard.setReg(phys_reg);
829 }
830
831 //Bind condition-code Regs to Rename Map
832 for (RegId reg_id(CCRegClass, 0); reg_id.index() < TheISA::NumCCRegs;
833 reg_id.index()++) {
834 PhysRegIdPtr phys_reg = freeList.getCCReg();
835 renameMap[tid].setEntry(reg_id, phys_reg);
836 scoreboard.setReg(phys_reg);
837 }
838
839 //Copy Thread Data Into RegFile
840 //this->copyFromTC(tid);
841
842 //Set PC/NPC/NNPC
843 pcState(src_tc->pcState(), tid);
844
845 src_tc->setStatus(ThreadContext::Active);
846
847 activateContext(tid);
848
849 //Reset ROB/IQ/LSQ Entries
850 commit.rob->resetEntries();
851 iew.resetEntries();
852}
853
854template <class Impl>
855void
856FullO3CPU<Impl>::removeThread(ThreadID tid)
857{
858 DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
859
860 // Copy Thread Data From RegFile
861 // If thread is suspended, it might be re-allocated
862 // this->copyToTC(tid);
863
864
865 // @todo: 2-27-2008: Fix how we free up rename mappings
866 // here to alleviate the case for double-freeing registers
867 // in SMT workloads.
868
869 // Unbind Int Regs from Rename Map
870 for (RegId reg_id(IntRegClass, 0); reg_id.index() < TheISA::NumIntRegs;
871 reg_id.index()++) {
872 PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id);
873 scoreboard.unsetReg(phys_reg);
874 freeList.addReg(phys_reg);
875 }
876
877 // Unbind Float Regs from Rename Map
878 for (RegId reg_id(FloatRegClass, 0); reg_id.index() < TheISA::NumFloatRegs;
879 reg_id.index()++) {
880 PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id);
881 scoreboard.unsetReg(phys_reg);
882 freeList.addReg(phys_reg);
883 }
884
885 // Unbind condition-code Regs from Rename Map
886 for (RegId reg_id(CCRegClass, 0); reg_id.index() < TheISA::NumCCRegs;
887 reg_id.index()++) {
888 PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id);
889 scoreboard.unsetReg(phys_reg);
890 freeList.addReg(phys_reg);
891 }
892
893 // Squash Throughout Pipeline
894 DynInstPtr inst = commit.rob->readHeadInst(tid);
895 InstSeqNum squash_seq_num = inst->seqNum;
896 fetch.squash(0, squash_seq_num, inst, tid);
897 decode.squash(tid);
898 rename.squash(squash_seq_num, tid);
899 iew.squash(tid);
900 iew.ldstQueue.squash(squash_seq_num, tid);
901 commit.rob->squash(squash_seq_num, tid);
902
903
904 assert(iew.instQueue.getCount(tid) == 0);
905 assert(iew.ldstQueue.getCount(tid) == 0);
906
907 // Reset ROB/IQ/LSQ Entries
908
909 // Commented out for now. This should be possible to do by
910 // telling all the pipeline stages to drain first, and then
911 // checking until the drain completes. Once the pipeline is
912 // drained, call resetEntries(). - 10-09-06 ktlim
913/*
914 if (activeThreads.size() >= 1) {
915 commit.rob->resetEntries();
916 iew.resetEntries();
917 }
918*/
919}
920
921template <class Impl>
922Fault
923FullO3CPU<Impl>::hwrei(ThreadID tid)
924{
925#if THE_ISA == ALPHA_ISA
926 // Need to clear the lock flag upon returning from an interrupt.
927 this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
928
929 this->thread[tid]->kernelStats->hwrei();
930
931 // FIXME: XXX check for interrupts? XXX
932#endif
933 return NoFault;
934}
935
936template <class Impl>
937bool
938FullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid)
939{
940#if THE_ISA == ALPHA_ISA
941 if (this->thread[tid]->kernelStats)
942 this->thread[tid]->kernelStats->callpal(palFunc,
943 this->threadContexts[tid]);
944
945 switch (palFunc) {
946 case PAL::halt:
947 halt();
948 if (--System::numSystemsRunning == 0)
949 exitSimLoop("all cpus halted");
950 break;
951
952 case PAL::bpt:
953 case PAL::bugchk:
954 if (this->system->breakpoint())
955 return false;
956 break;
957 }
958#endif
959 return true;
960}
961
962template <class Impl>
963Fault
964FullO3CPU<Impl>::getInterrupts()
965{
966 // Check if there are any outstanding interrupts
967 return this->interrupts[0]->getInterrupt(this->threadContexts[0]);
968}
969
970template <class Impl>
971void
972FullO3CPU<Impl>::processInterrupts(const Fault &interrupt)
973{
974 // Check for interrupts here. For now can copy the code that
975 // exists within isa_fullsys_traits.hh. Also assume that thread 0
976 // is the one that handles the interrupts.
977 // @todo: Possibly consolidate the interrupt checking code.
978 // @todo: Allow other threads to handle interrupts.
979
980 assert(interrupt != NoFault);
981 this->interrupts[0]->updateIntrInfo(this->threadContexts[0]);
982
983 DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
984 this->trap(interrupt, 0, nullptr);
985}
986
987template <class Impl>
988void
989FullO3CPU<Impl>::trap(const Fault &fault, ThreadID tid,
990 const StaticInstPtr &inst)
991{
992 // Pass the thread's TC into the invoke method.
993 fault->invoke(this->threadContexts[tid], inst);
994}
995
996template <class Impl>
997void
998FullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid, Fault *fault)
999{
1000 DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid);
1001
1002 DPRINTF(Activity,"Activity: syscall() called.\n");
1003
1004 // Temporarily increase this by one to account for the syscall
1005 // instruction.
1006 ++(this->thread[tid]->funcExeInst);
1007
1008 // Execute the actual syscall.
1009 this->thread[tid]->syscall(callnum, fault);
1010
1011 // Decrease funcExeInst by one as the normal commit will handle
1012 // incrementing it.
1013 --(this->thread[tid]->funcExeInst);
1014}
1015
1016template <class Impl>
1017void
1018FullO3CPU<Impl>::serializeThread(CheckpointOut &cp, ThreadID tid) const
1019{
1020 thread[tid]->serialize(cp);
1021}
1022
1023template <class Impl>
1024void
1025FullO3CPU<Impl>::unserializeThread(CheckpointIn &cp, ThreadID tid)
1026{
1027 thread[tid]->unserialize(cp);
1028}
1029
1030template <class Impl>
1031DrainState
1032FullO3CPU<Impl>::drain()
1033{
1034 // If the CPU isn't doing anything, then return immediately.
1035 if (switchedOut())
1036 return DrainState::Drained;
1037
1038 DPRINTF(Drain, "Draining...\n");
1039
1040 // We only need to signal a drain to the commit stage as this
1041 // initiates squashing controls the draining. Once the commit
1042 // stage commits an instruction where it is safe to stop, it'll
1043 // squash the rest of the instructions in the pipeline and force
1044 // the fetch stage to stall. The pipeline will be drained once all
1045 // in-flight instructions have retired.
1046 commit.drain();
1047
1048 // Wake the CPU and record activity so everything can drain out if
1049 // the CPU was not able to immediately drain.
1050 if (!isDrained()) {
1051 wakeCPU();
1052 activityRec.activity();
1053
1054 DPRINTF(Drain, "CPU not drained\n");
1055
1056 return DrainState::Draining;
1057 } else {
1058 DPRINTF(Drain, "CPU is already drained\n");
1059 if (tickEvent.scheduled())
1060 deschedule(tickEvent);
1061
1062 // Flush out any old data from the time buffers. In
1063 // particular, there might be some data in flight from the
1064 // fetch stage that isn't visible in any of the CPU buffers we
1065 // test in isDrained().
1066 for (int i = 0; i < timeBuffer.getSize(); ++i) {
1067 timeBuffer.advance();
1068 fetchQueue.advance();
1069 decodeQueue.advance();
1070 renameQueue.advance();
1071 iewQueue.advance();
1072 }
1073
1074 drainSanityCheck();
1075 return DrainState::Drained;
1076 }
1077}
1078
1079template <class Impl>
1080bool
1081FullO3CPU<Impl>::tryDrain()
1082{
1083 if (drainState() != DrainState::Draining || !isDrained())
1084 return false;
1085
1086 if (tickEvent.scheduled())
1087 deschedule(tickEvent);
1088
1089 DPRINTF(Drain, "CPU done draining, processing drain event\n");
1090 signalDrainDone();
1091
1092 return true;
1093}
1094
1095template <class Impl>
1096void
1097FullO3CPU<Impl>::drainSanityCheck() const
1098{
1099 assert(isDrained());
1100 fetch.drainSanityCheck();
1101 decode.drainSanityCheck();
1102 rename.drainSanityCheck();
1103 iew.drainSanityCheck();
1104 commit.drainSanityCheck();
1105}
1106
1107template <class Impl>
1108bool
1109FullO3CPU<Impl>::isDrained() const
1110{
1111 bool drained(true);
1112
1113 if (!instList.empty() || !removeList.empty()) {
1114 DPRINTF(Drain, "Main CPU structures not drained.\n");
1115 drained = false;
1116 }
1117
1118 if (!fetch.isDrained()) {
1119 DPRINTF(Drain, "Fetch not drained.\n");
1120 drained = false;
1121 }
1122
1123 if (!decode.isDrained()) {
1124 DPRINTF(Drain, "Decode not drained.\n");
1125 drained = false;
1126 }
1127
1128 if (!rename.isDrained()) {
1129 DPRINTF(Drain, "Rename not drained.\n");
1130 drained = false;
1131 }
1132
1133 if (!iew.isDrained()) {
1134 DPRINTF(Drain, "IEW not drained.\n");
1135 drained = false;
1136 }
1137
1138 if (!commit.isDrained()) {
1139 DPRINTF(Drain, "Commit not drained.\n");
1140 drained = false;
1141 }
1142
1143 return drained;
1144}
1145
1146template <class Impl>
1147void
1148FullO3CPU<Impl>::commitDrained(ThreadID tid)
1149{
1150 fetch.drainStall(tid);
1151}
1152
1153template <class Impl>
1154void
1155FullO3CPU<Impl>::drainResume()
1156{
1157 if (switchedOut())
1158 return;
1159
1160 DPRINTF(Drain, "Resuming...\n");
1161 verifyMemoryMode();
1162
1163 fetch.drainResume();
1164 commit.drainResume();
1165
1166 _status = Idle;
1167 for (ThreadID i = 0; i < thread.size(); i++) {
1168 if (thread[i]->status() == ThreadContext::Active) {
1169 DPRINTF(Drain, "Activating thread: %i\n", i);
1170 activateThread(i);
1171 _status = Running;
1172 }
1173 }
1174
1175 assert(!tickEvent.scheduled());
1176 if (_status == Running)
1177 schedule(tickEvent, nextCycle());
1178}
1179
1180template <class Impl>
1181void
1182FullO3CPU<Impl>::switchOut()
1183{
1184 DPRINTF(O3CPU, "Switching out\n");
1185 BaseCPU::switchOut();
1186
1187 activityRec.reset();
1188
1189 _status = SwitchedOut;
1190
1191 if (checker)
1192 checker->switchOut();
1193}
1194
1195template <class Impl>
1196void
1197FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
1198{
1199 BaseCPU::takeOverFrom(oldCPU);
1200
1201 fetch.takeOverFrom();
1202 decode.takeOverFrom();
1203 rename.takeOverFrom();
1204 iew.takeOverFrom();
1205 commit.takeOverFrom();
1206
1207 assert(!tickEvent.scheduled());
1208
1209 FullO3CPU<Impl> *oldO3CPU = dynamic_cast<FullO3CPU<Impl>*>(oldCPU);
1210 if (oldO3CPU)
1211 globalSeqNum = oldO3CPU->globalSeqNum;
1212
1213 lastRunningCycle = curCycle();
1214 _status = Idle;
1215}
1216
1217template <class Impl>
1218void
1219FullO3CPU<Impl>::verifyMemoryMode() const
1220{
1221 if (!system->isTimingMode()) {
1222 fatal("The O3 CPU requires the memory system to be in "
1223 "'timing' mode.\n");
1224 }
1225}
1226
1227template <class Impl>
1228TheISA::MiscReg
1229FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
1230{
1231 return this->isa[tid]->readMiscRegNoEffect(misc_reg);
1232}
1233
1234template <class Impl>
1235TheISA::MiscReg
1236FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
1237{
1238 miscRegfileReads++;
1239 return this->isa[tid]->readMiscReg(misc_reg, tcBase(tid));
1240}
1241
1242template <class Impl>
1243void
1244FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
1245 const TheISA::MiscReg &val, ThreadID tid)
1246{
1247 this->isa[tid]->setMiscRegNoEffect(misc_reg, val);
1248}
1249
1250template <class Impl>
1251void
1252FullO3CPU<Impl>::setMiscReg(int misc_reg,
1253 const TheISA::MiscReg &val, ThreadID tid)
1254{
1255 miscRegfileWrites++;
1256 this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid));
1257}
1258
1259template <class Impl>
1260uint64_t
1261FullO3CPU<Impl>::readIntReg(PhysRegIdPtr phys_reg)
1262{
1263 intRegfileReads++;
1264 return regFile.readIntReg(phys_reg);
1265}
1266
1267template <class Impl>
1268FloatReg
1269FullO3CPU<Impl>::readFloatReg(PhysRegIdPtr phys_reg)
1270{
1271 fpRegfileReads++;
1272 return regFile.readFloatReg(phys_reg);
1273}
1274
1275template <class Impl>
1276FloatRegBits
1277FullO3CPU<Impl>::readFloatRegBits(PhysRegIdPtr phys_reg)
1278{
1279 fpRegfileReads++;
1280 return regFile.readFloatRegBits(phys_reg);
1281}
1282
1283template <class Impl>
1284auto
1285FullO3CPU<Impl>::readVecReg(PhysRegIdPtr phys_reg) const
1286 -> const VecRegContainer&
1287{
1288 vecRegfileReads++;
1289 return regFile.readVecReg(phys_reg);
1290}
1291
1292template <class Impl>
1293auto
1294FullO3CPU<Impl>::getWritableVecReg(PhysRegIdPtr phys_reg)
1295 -> VecRegContainer&
1296{
1297 vecRegfileWrites++;
1298 return regFile.getWritableVecReg(phys_reg);
1299}
1300
1301template <class Impl>
1302auto
1303FullO3CPU<Impl>::readVecElem(PhysRegIdPtr phys_reg) const -> const VecElem&
1304{
1305 vecRegfileReads++;
1306 return regFile.readVecElem(phys_reg);
1307}
1308
1309template <class Impl>
1310CCReg
1311FullO3CPU<Impl>::readCCReg(PhysRegIdPtr phys_reg)
1312{
1313 ccRegfileReads++;
1314 return regFile.readCCReg(phys_reg);
1315}
1316
1317template <class Impl>
1318void
1319FullO3CPU<Impl>::setIntReg(PhysRegIdPtr phys_reg, uint64_t val)
1320{
1321 intRegfileWrites++;
1322 regFile.setIntReg(phys_reg, val);
1323}
1324
1325template <class Impl>
1326void
1327FullO3CPU<Impl>::setFloatReg(PhysRegIdPtr phys_reg, FloatReg val)
1328{
1329 fpRegfileWrites++;
1330 regFile.setFloatReg(phys_reg, val);
1331}
1332
1333template <class Impl>
1334void
1335FullO3CPU<Impl>::setFloatRegBits(PhysRegIdPtr phys_reg, FloatRegBits val)
1336{
1337 fpRegfileWrites++;
1338 regFile.setFloatRegBits(phys_reg, val);
1339}
1340
1341template <class Impl>
1342void
1343FullO3CPU<Impl>::setVecReg(PhysRegIdPtr phys_reg, const VecRegContainer& val)
1344{
1345 vecRegfileWrites++;
1346 regFile.setVecReg(phys_reg, val);
1347}
1348
1349template <class Impl>
1350void
1351FullO3CPU<Impl>::setVecElem(PhysRegIdPtr phys_reg, const VecElem& val)
1352{
1353 vecRegfileWrites++;
1354 regFile.setVecElem(phys_reg, val);
1355}
1356
1357template <class Impl>
1358void
1359FullO3CPU<Impl>::setCCReg(PhysRegIdPtr phys_reg, CCReg val)
1360{
1361 ccRegfileWrites++;
1362 regFile.setCCReg(phys_reg, val);
1363}
1364
1365template <class Impl>
1366uint64_t
1367FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1368{
1369 intRegfileReads++;
1370 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1371 RegId(IntRegClass, reg_idx));
1372
1373 return regFile.readIntReg(phys_reg);
1374}
1375
1376template <class Impl>
1377float
1378FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
1379{
1380 fpRegfileReads++;
1381 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1382 RegId(FloatRegClass, reg_idx));
1383
1384 return regFile.readFloatReg(phys_reg);
1385}
1386
1387template <class Impl>
1388uint64_t
1389FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid)
1390{
1391 fpRegfileReads++;
1392 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1393 RegId(FloatRegClass, reg_idx));
1394
1395 return regFile.readFloatRegBits(phys_reg);
1396}
1397
1398template <class Impl>
1399auto
1400FullO3CPU<Impl>::readArchVecReg(int reg_idx, ThreadID tid) const
1401 -> const VecRegContainer&
1402{
1403 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1404 RegId(VecRegClass, reg_idx));
1405 return readVecReg(phys_reg);
1406}
1407
1408template <class Impl>
1409auto
1410FullO3CPU<Impl>::getWritableArchVecReg(int reg_idx, ThreadID tid)
1411 -> VecRegContainer&
1412{
1413 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1414 RegId(VecRegClass, reg_idx));
1415 return getWritableVecReg(phys_reg);
1416}
1417
1418template <class Impl>
1419auto
1420FullO3CPU<Impl>::readArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
1421 ThreadID tid) const -> const VecElem&
1422{
1423 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1424 RegId(VecRegClass, reg_idx, ldx));
1425 return readVecElem(phys_reg);
1426}
1427
1428template <class Impl>
1429CCReg
1430FullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid)
1431{
1432 ccRegfileReads++;
1433 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1434 RegId(CCRegClass, reg_idx));
1435
1436 return regFile.readCCReg(phys_reg);
1437}
1438
1439template <class Impl>
1440void
1441FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
1442{
1443 intRegfileWrites++;
1444 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1445 RegId(IntRegClass, reg_idx));
1446
1447 regFile.setIntReg(phys_reg, val);
1448}
1449
1450template <class Impl>
1451void
1452FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid)
1453{
1454 fpRegfileWrites++;
1455 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1456 RegId(FloatRegClass, reg_idx));
1457
1458 regFile.setFloatReg(phys_reg, val);
1459}
1460
1461template <class Impl>
1462void
1463FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid)
1464{
1465 fpRegfileWrites++;
1466 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1467 RegId(FloatRegClass, reg_idx));
1468
1469 regFile.setFloatRegBits(phys_reg, val);
1470}
1471
1472template <class Impl>
1473void
1474FullO3CPU<Impl>::setArchVecReg(int reg_idx, const VecRegContainer& val,
1475 ThreadID tid)
1476{
1477 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1478 RegId(VecRegClass, reg_idx));
1479 setVecReg(phys_reg, val);
1480}
1481
1482template <class Impl>
1483void
1484FullO3CPU<Impl>::setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
1485 const VecElem& val, ThreadID tid)
1486{
1487 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1488 RegId(VecRegClass, reg_idx, ldx));
1489 setVecElem(phys_reg, val);
1490}
1491
1492template <class Impl>
1493void
1494FullO3CPU<Impl>::setArchCCReg(int reg_idx, CCReg val, ThreadID tid)
1495{
1496 ccRegfileWrites++;
1497 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1498 RegId(CCRegClass, reg_idx));
1499
1500 regFile.setCCReg(phys_reg, val);
1501}
1502
1503template <class Impl>
1504TheISA::PCState
1505FullO3CPU<Impl>::pcState(ThreadID tid)
1506{
1507 return commit.pcState(tid);
1508}
1509
1510template <class Impl>
1511void
1512FullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid)
1513{
1514 commit.pcState(val, tid);
1515}
1516
1517template <class Impl>
1518Addr
1519FullO3CPU<Impl>::instAddr(ThreadID tid)
1520{
1521 return commit.instAddr(tid);
1522}
1523
1524template <class Impl>
1525Addr
1526FullO3CPU<Impl>::nextInstAddr(ThreadID tid)
1527{
1528 return commit.nextInstAddr(tid);
1529}
1530
1531template <class Impl>
1532MicroPC
1533FullO3CPU<Impl>::microPC(ThreadID tid)
1534{
1535 return commit.microPC(tid);
1536}
1537
1538template <class Impl>
1539void
1540FullO3CPU<Impl>::squashFromTC(ThreadID tid)
1541{
1542 this->thread[tid]->noSquashFromTC = true;
1543 this->commit.generateTCEvent(tid);
1544}
1545
1546template <class Impl>
1547typename FullO3CPU<Impl>::ListIt
1548FullO3CPU<Impl>::addInst(DynInstPtr &inst)
1549{
1550 instList.push_back(inst);
1551
1552 return --(instList.end());
1553}
1554
1555template <class Impl>
1556void
1557FullO3CPU<Impl>::instDone(ThreadID tid, DynInstPtr &inst)
1558{
1559 // Keep an instruction count.
1560 if (!inst->isMicroop() || inst->isLastMicroop()) {
1561 thread[tid]->numInst++;
1562 thread[tid]->numInsts++;
1563 committedInsts[tid]++;
1564 system->totalNumInsts++;
1565
1566 // Check for instruction-count-based events.
1567 comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1568 system->instEventQueue.serviceEvents(system->totalNumInsts);
1569 }
1570 thread[tid]->numOp++;
1571 thread[tid]->numOps++;
1572 committedOps[tid]++;
1573
1574 probeInstCommit(inst->staticInst);
1575}
1576
1577template <class Impl>
1578void
1579FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
1580{
1581 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s "
1582 "[sn:%lli]\n",
1583 inst->threadNumber, inst->pcState(), inst->seqNum);
1584
1585 removeInstsThisCycle = true;
1586
1587 // Remove the front instruction.
1588 removeList.push(inst->getInstListIt());
1589}
1590
1591template <class Impl>
1592void
1593FullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid)
1594{
1595 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1596 " list.\n", tid);
1597
1598 ListIt end_it;
1599
1600 bool rob_empty = false;
1601
1602 if (instList.empty()) {
1603 return;
1604 } else if (rob.isEmpty(tid)) {
1605 DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1606 end_it = instList.begin();
1607 rob_empty = true;
1608 } else {
1609 end_it = (rob.readTailInst(tid))->getInstListIt();
1610 DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1611 }
1612
1613 removeInstsThisCycle = true;
1614
1615 ListIt inst_it = instList.end();
1616
1617 inst_it--;
1618
1619 // Walk through the instruction list, removing any instructions
1620 // that were inserted after the given instruction iterator, end_it.
1621 while (inst_it != end_it) {
1622 assert(!instList.empty());
1623
1624 squashInstIt(inst_it, tid);
1625
1626 inst_it--;
1627 }
1628
1629 // If the ROB was empty, then we actually need to remove the first
1630 // instruction as well.
1631 if (rob_empty) {
1632 squashInstIt(inst_it, tid);
1633 }
1634}
1635
1636template <class Impl>
1637void
1638FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1639{
1640 assert(!instList.empty());
1641
1642 removeInstsThisCycle = true;
1643
1644 ListIt inst_iter = instList.end();
1645
1646 inst_iter--;
1647
1648 DPRINTF(O3CPU, "Deleting instructions from instruction "
1649 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1650 tid, seq_num, (*inst_iter)->seqNum);
1651
1652 while ((*inst_iter)->seqNum > seq_num) {
1653
1654 bool break_loop = (inst_iter == instList.begin());
1655
1656 squashInstIt(inst_iter, tid);
1657
1658 inst_iter--;
1659
1660 if (break_loop)
1661 break;
1662 }
1663}
1664
1665template <class Impl>
1666inline void
1667FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid)
1668{
1669 if ((*instIt)->threadNumber == tid) {
1670 DPRINTF(O3CPU, "Squashing instruction, "
1671 "[tid:%i] [sn:%lli] PC %s\n",
1672 (*instIt)->threadNumber,
1673 (*instIt)->seqNum,
1674 (*instIt)->pcState());
1675
1676 // Mark it as squashed.
1677 (*instIt)->setSquashed();
1678
1679 // @todo: Formulate a consistent method for deleting
1680 // instructions from the instruction list
1681 // Remove the instruction from the list.
1682 removeList.push(instIt);
1683 }
1684}
1685
1686template <class Impl>
1687void
1688FullO3CPU<Impl>::cleanUpRemovedInsts()
1689{
1690 while (!removeList.empty()) {
1691 DPRINTF(O3CPU, "Removing instruction, "
1692 "[tid:%i] [sn:%lli] PC %s\n",
1693 (*removeList.front())->threadNumber,
1694 (*removeList.front())->seqNum,
1695 (*removeList.front())->pcState());
1696
1697 instList.erase(removeList.front());
1698
1699 removeList.pop();
1700 }
1701
1702 removeInstsThisCycle = false;
1703}
1704/*
1705template <class Impl>
1706void
1707FullO3CPU<Impl>::removeAllInsts()
1708{
1709 instList.clear();
1710}
1711*/
1712template <class Impl>
1713void
1714FullO3CPU<Impl>::dumpInsts()
1715{
1716 int num = 0;
1717
1718 ListIt inst_list_it = instList.begin();
1719
1720 cprintf("Dumping Instruction List\n");
1721
1722 while (inst_list_it != instList.end()) {
1723 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1724 "Squashed:%i\n\n",
1725 num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber,
1726 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1727 (*inst_list_it)->isSquashed());
1728 inst_list_it++;
1729 ++num;
1730 }
1731}
1732/*
1733template <class Impl>
1734void
1735FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
1736{
1737 iew.wakeDependents(inst);
1738}
1739*/
1740template <class Impl>
1741void
1742FullO3CPU<Impl>::wakeCPU()
1743{
1744 if (activityRec.active() || tickEvent.scheduled()) {
1745 DPRINTF(Activity, "CPU already running.\n");
1746 return;
1747 }
1748
1749 DPRINTF(Activity, "Waking up CPU\n");
1750
1751 Cycles cycles(curCycle() - lastRunningCycle);
1752 // @todo: This is an oddity that is only here to match the stats
1753 if (cycles > 1) {
1754 --cycles;
1755 idleCycles += cycles;
1756 numCycles += cycles;
1757 ppCycles->notify(cycles);
1758 }
1759
1760 schedule(tickEvent, clockEdge());
1761}
1762
1763template <class Impl>
1764void
1765FullO3CPU<Impl>::wakeup(ThreadID tid)
1766{
1767 if (this->thread[tid]->status() != ThreadContext::Suspended)
1768 return;
1769
1770 this->wakeCPU();
1771
1772 DPRINTF(Quiesce, "Suspended Processor woken\n");
1773 this->threadContexts[tid]->activate();
1774}
1775
1776template <class Impl>
1777ThreadID
1778FullO3CPU<Impl>::getFreeTid()
1779{
1780 for (ThreadID tid = 0; tid < numThreads; tid++) {
1781 if (!tids[tid]) {
1782 tids[tid] = true;
1783 return tid;
1784 }
1785 }
1786
1787 return InvalidThreadID;
1788}
1789
1790template <class Impl>
1791void
1792FullO3CPU<Impl>::updateThreadPriority()
1793{
1794 if (activeThreads.size() > 1) {
1795 //DEFAULT TO ROUND ROBIN SCHEME
1796 //e.g. Move highest priority to end of thread list
1797 list<ThreadID>::iterator list_begin = activeThreads.begin();
1798
1799 unsigned high_thread = *list_begin;
1800
1801 activeThreads.erase(list_begin);
1802
1803 activeThreads.push_back(high_thread);
1804 }
1805}
1806
1807// Forward declaration of FullO3CPU.
1808template class FullO3CPU<O3CPUImpl>;
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