98 fetch->processCacheCompletion(pkt);
99
100 return true;
101}
102
103template<class Impl>
104void
105FullO3CPU<Impl>::IcachePort::recvReqRetry()
106{
107 fetch->recvReqRetry();
108}
109
110template <class Impl>
111bool
112FullO3CPU<Impl>::DcachePort::recvTimingResp(PacketPtr pkt)
113{
114 return lsq->recvTimingResp(pkt);
115}
116
117template <class Impl>
118void
119FullO3CPU<Impl>::DcachePort::recvTimingSnoopReq(PacketPtr pkt)
120{
121 for (ThreadID tid = 0; tid < cpu->numThreads; tid++) {
122 if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) {
123 cpu->wakeup(tid);
124 }
125 }
126 lsq->recvTimingSnoopReq(pkt);
127}
128
129template <class Impl>
130void
131FullO3CPU<Impl>::DcachePort::recvReqRetry()
132{
133 lsq->recvReqRetry();
134}
135
136template <class Impl>
137FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
138 : Event(CPU_Tick_Pri), cpu(c)
139{
140}
141
142template <class Impl>
143void
144FullO3CPU<Impl>::TickEvent::process()
145{
146 cpu->tick();
147}
148
149template <class Impl>
150const char *
151FullO3CPU<Impl>::TickEvent::description() const
152{
153 return "FullO3CPU tick";
154}
155
156template <class Impl>
157FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
158 : BaseO3CPU(params),
159 itb(params->itb),
160 dtb(params->dtb),
161 tickEvent(this),
162#ifndef NDEBUG
163 instcount(0),
164#endif
165 removeInstsThisCycle(false),
166 fetch(this, params),
167 decode(this, params),
168 rename(this, params),
169 iew(this, params),
170 commit(this, params),
171
172 regFile(params->numPhysIntRegs,
173 params->numPhysFloatRegs,
174 params->numPhysCCRegs),
175
176 freeList(name() + ".freelist", ®File),
177
178 rob(this, params),
179
180 scoreboard(name() + ".scoreboard",
181 regFile.totalNumPhysRegs(), TheISA::NumMiscRegs,
182 TheISA::ZeroReg, TheISA::ZeroReg),
183
184 isa(numThreads, NULL),
185
186 icachePort(&fetch, this),
187 dcachePort(&iew.ldstQueue, this),
188
189 timeBuffer(params->backComSize, params->forwardComSize),
190 fetchQueue(params->backComSize, params->forwardComSize),
191 decodeQueue(params->backComSize, params->forwardComSize),
192 renameQueue(params->backComSize, params->forwardComSize),
193 iewQueue(params->backComSize, params->forwardComSize),
194 activityRec(name(), NumStages,
195 params->backComSize + params->forwardComSize,
196 params->activity),
197
198 globalSeqNum(1),
199 system(params->system),
200 lastRunningCycle(curCycle())
201{
202 if (!params->switched_out) {
203 _status = Running;
204 } else {
205 _status = SwitchedOut;
206 }
207
208 if (params->checker) {
209 BaseCPU *temp_checker = params->checker;
210 checker = dynamic_cast<Checker<Impl> *>(temp_checker);
211 checker->setIcachePort(&icachePort);
212 checker->setSystem(params->system);
213 } else {
214 checker = NULL;
215 }
216
217 if (!FullSystem) {
218 thread.resize(numThreads);
219 tids.resize(numThreads);
220 }
221
222 // The stages also need their CPU pointer setup. However this
223 // must be done at the upper level CPU because they have pointers
224 // to the upper level CPU, and not this FullO3CPU.
225
226 // Set up Pointers to the activeThreads list for each stage
227 fetch.setActiveThreads(&activeThreads);
228 decode.setActiveThreads(&activeThreads);
229 rename.setActiveThreads(&activeThreads);
230 iew.setActiveThreads(&activeThreads);
231 commit.setActiveThreads(&activeThreads);
232
233 // Give each of the stages the time buffer they will use.
234 fetch.setTimeBuffer(&timeBuffer);
235 decode.setTimeBuffer(&timeBuffer);
236 rename.setTimeBuffer(&timeBuffer);
237 iew.setTimeBuffer(&timeBuffer);
238 commit.setTimeBuffer(&timeBuffer);
239
240 // Also setup each of the stages' queues.
241 fetch.setFetchQueue(&fetchQueue);
242 decode.setFetchQueue(&fetchQueue);
243 commit.setFetchQueue(&fetchQueue);
244 decode.setDecodeQueue(&decodeQueue);
245 rename.setDecodeQueue(&decodeQueue);
246 rename.setRenameQueue(&renameQueue);
247 iew.setRenameQueue(&renameQueue);
248 iew.setIEWQueue(&iewQueue);
249 commit.setIEWQueue(&iewQueue);
250 commit.setRenameQueue(&renameQueue);
251
252 commit.setIEWStage(&iew);
253 rename.setIEWStage(&iew);
254 rename.setCommitStage(&commit);
255
256 ThreadID active_threads;
257 if (FullSystem) {
258 active_threads = 1;
259 } else {
260 active_threads = params->workload.size();
261
262 if (active_threads > Impl::MaxThreads) {
263 panic("Workload Size too large. Increase the 'MaxThreads' "
264 "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) "
265 "or edit your workload size.");
266 }
267 }
268
269 //Make Sure That this a Valid Architeture
270 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs);
271 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
272 assert(params->numPhysCCRegs >= numThreads * TheISA::NumCCRegs);
273
274 rename.setScoreboard(&scoreboard);
275 iew.setScoreboard(&scoreboard);
276
277 // Setup the rename map for whichever stages need it.
278 for (ThreadID tid = 0; tid < numThreads; tid++) {
279 isa[tid] = params->isa[tid];
280
281 // Only Alpha has an FP zero register, so for other ISAs we
282 // use an invalid FP register index to avoid special treatment
283 // of any valid FP reg.
284 RegIndex invalidFPReg = TheISA::NumFloatRegs + 1;
285 RegIndex fpZeroReg =
286 (THE_ISA == ALPHA_ISA) ? TheISA::ZeroReg : invalidFPReg;
287
288 commitRenameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg,
289 &freeList);
290
291 renameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg,
292 &freeList);
293 }
294
295 // Initialize rename map to assign physical registers to the
296 // architectural registers for active threads only.
297 for (ThreadID tid = 0; tid < active_threads; tid++) {
298 for (RegIndex ridx = 0; ridx < TheISA::NumIntRegs; ++ridx) {
299 // Note that we can't use the rename() method because we don't
300 // want special treatment for the zero register at this point
301 PhysRegIndex phys_reg = freeList.getIntReg();
302 renameMap[tid].setIntEntry(ridx, phys_reg);
303 commitRenameMap[tid].setIntEntry(ridx, phys_reg);
304 }
305
306 for (RegIndex ridx = 0; ridx < TheISA::NumFloatRegs; ++ridx) {
307 PhysRegIndex phys_reg = freeList.getFloatReg();
308 renameMap[tid].setFloatEntry(ridx, phys_reg);
309 commitRenameMap[tid].setFloatEntry(ridx, phys_reg);
310 }
311
312 for (RegIndex ridx = 0; ridx < TheISA::NumCCRegs; ++ridx) {
313 PhysRegIndex phys_reg = freeList.getCCReg();
314 renameMap[tid].setCCEntry(ridx, phys_reg);
315 commitRenameMap[tid].setCCEntry(ridx, phys_reg);
316 }
317 }
318
319 rename.setRenameMap(renameMap);
320 commit.setRenameMap(commitRenameMap);
321 rename.setFreeList(&freeList);
322
323 // Setup the ROB for whichever stages need it.
324 commit.setROB(&rob);
325
326 lastActivatedCycle = 0;
327#if 0
328 // Give renameMap & rename stage access to the freeList;
329 for (ThreadID tid = 0; tid < numThreads; tid++)
330 globalSeqNum[tid] = 1;
331#endif
332
333 DPRINTF(O3CPU, "Creating O3CPU object.\n");
334
335 // Setup any thread state.
336 this->thread.resize(this->numThreads);
337
338 for (ThreadID tid = 0; tid < this->numThreads; ++tid) {
339 if (FullSystem) {
340 // SMT is not supported in FS mode yet.
341 assert(this->numThreads == 1);
342 this->thread[tid] = new Thread(this, 0, NULL);
343 } else {
344 if (tid < params->workload.size()) {
345 DPRINTF(O3CPU, "Workload[%i] process is %#x",
346 tid, this->thread[tid]);
347 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
348 (typename Impl::O3CPU *)(this),
349 tid, params->workload[tid]);
350
351 //usedTids[tid] = true;
352 //threadMap[tid] = tid;
353 } else {
354 //Allocate Empty thread so M5 can use later
355 //when scheduling threads to CPU
356 Process* dummy_proc = NULL;
357
358 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
359 (typename Impl::O3CPU *)(this),
360 tid, dummy_proc);
361 //usedTids[tid] = false;
362 }
363 }
364
365 ThreadContext *tc;
366
367 // Setup the TC that will serve as the interface to the threads/CPU.
368 O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>;
369
370 tc = o3_tc;
371
372 // If we're using a checker, then the TC should be the
373 // CheckerThreadContext.
374 if (params->checker) {
375 tc = new CheckerThreadContext<O3ThreadContext<Impl> >(
376 o3_tc, this->checker);
377 }
378
379 o3_tc->cpu = (typename Impl::O3CPU *)(this);
380 assert(o3_tc->cpu);
381 o3_tc->thread = this->thread[tid];
382
383 if (FullSystem) {
384 // Setup quiesce event.
385 this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
386 }
387 // Give the thread the TC.
388 this->thread[tid]->tc = tc;
389
390 // Add the TC to the CPU's list of TC's.
391 this->threadContexts.push_back(tc);
392 }
393
394 // FullO3CPU always requires an interrupt controller.
395 if (!params->switched_out && interrupts.empty()) {
396 fatal("FullO3CPU %s has no interrupt controller.\n"
397 "Ensure createInterruptController() is called.\n", name());
398 }
399
400 for (ThreadID tid = 0; tid < this->numThreads; tid++)
401 this->thread[tid]->setFuncExeInst(0);
402}
403
404template <class Impl>
405FullO3CPU<Impl>::~FullO3CPU()
406{
407}
408
409template <class Impl>
410void
411FullO3CPU<Impl>::regProbePoints()
412{
413 BaseCPU::regProbePoints();
414
415 ppInstAccessComplete = new ProbePointArg<PacketPtr>(getProbeManager(), "InstAccessComplete");
416 ppDataAccessComplete = new ProbePointArg<std::pair<DynInstPtr, PacketPtr> >(getProbeManager(), "DataAccessComplete");
417
418 fetch.regProbePoints();
419 rename.regProbePoints();
420 iew.regProbePoints();
421 commit.regProbePoints();
422}
423
424template <class Impl>
425void
426FullO3CPU<Impl>::regStats()
427{
428 BaseO3CPU::regStats();
429
430 // Register any of the O3CPU's stats here.
431 timesIdled
432 .name(name() + ".timesIdled")
433 .desc("Number of times that the entire CPU went into an idle state and"
434 " unscheduled itself")
435 .prereq(timesIdled);
436
437 idleCycles
438 .name(name() + ".idleCycles")
439 .desc("Total number of cycles that the CPU has spent unscheduled due "
440 "to idling")
441 .prereq(idleCycles);
442
443 quiesceCycles
444 .name(name() + ".quiesceCycles")
445 .desc("Total number of cycles that CPU has spent quiesced or waiting "
446 "for an interrupt")
447 .prereq(quiesceCycles);
448
449 // Number of Instructions simulated
450 // --------------------------------
451 // Should probably be in Base CPU but need templated
452 // MaxThreads so put in here instead
453 committedInsts
454 .init(numThreads)
455 .name(name() + ".committedInsts")
456 .desc("Number of Instructions Simulated")
457 .flags(Stats::total);
458
459 committedOps
460 .init(numThreads)
461 .name(name() + ".committedOps")
462 .desc("Number of Ops (including micro ops) Simulated")
463 .flags(Stats::total);
464
465 cpi
466 .name(name() + ".cpi")
467 .desc("CPI: Cycles Per Instruction")
468 .precision(6);
469 cpi = numCycles / committedInsts;
470
471 totalCpi
472 .name(name() + ".cpi_total")
473 .desc("CPI: Total CPI of All Threads")
474 .precision(6);
475 totalCpi = numCycles / sum(committedInsts);
476
477 ipc
478 .name(name() + ".ipc")
479 .desc("IPC: Instructions Per Cycle")
480 .precision(6);
481 ipc = committedInsts / numCycles;
482
483 totalIpc
484 .name(name() + ".ipc_total")
485 .desc("IPC: Total IPC of All Threads")
486 .precision(6);
487 totalIpc = sum(committedInsts) / numCycles;
488
489 this->fetch.regStats();
490 this->decode.regStats();
491 this->rename.regStats();
492 this->iew.regStats();
493 this->commit.regStats();
494 this->rob.regStats();
495
496 intRegfileReads
497 .name(name() + ".int_regfile_reads")
498 .desc("number of integer regfile reads")
499 .prereq(intRegfileReads);
500
501 intRegfileWrites
502 .name(name() + ".int_regfile_writes")
503 .desc("number of integer regfile writes")
504 .prereq(intRegfileWrites);
505
506 fpRegfileReads
507 .name(name() + ".fp_regfile_reads")
508 .desc("number of floating regfile reads")
509 .prereq(fpRegfileReads);
510
511 fpRegfileWrites
512 .name(name() + ".fp_regfile_writes")
513 .desc("number of floating regfile writes")
514 .prereq(fpRegfileWrites);
515
516 ccRegfileReads
517 .name(name() + ".cc_regfile_reads")
518 .desc("number of cc regfile reads")
519 .prereq(ccRegfileReads);
520
521 ccRegfileWrites
522 .name(name() + ".cc_regfile_writes")
523 .desc("number of cc regfile writes")
524 .prereq(ccRegfileWrites);
525
526 miscRegfileReads
527 .name(name() + ".misc_regfile_reads")
528 .desc("number of misc regfile reads")
529 .prereq(miscRegfileReads);
530
531 miscRegfileWrites
532 .name(name() + ".misc_regfile_writes")
533 .desc("number of misc regfile writes")
534 .prereq(miscRegfileWrites);
535}
536
537template <class Impl>
538void
539FullO3CPU<Impl>::tick()
540{
541 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
542 assert(!switchedOut());
543 assert(drainState() != DrainState::Drained);
544
545 ++numCycles;
546 ppCycles->notify(1);
547
548// activity = false;
549
550 //Tick each of the stages
551 fetch.tick();
552
553 decode.tick();
554
555 rename.tick();
556
557 iew.tick();
558
559 commit.tick();
560
561 // Now advance the time buffers
562 timeBuffer.advance();
563
564 fetchQueue.advance();
565 decodeQueue.advance();
566 renameQueue.advance();
567 iewQueue.advance();
568
569 activityRec.advance();
570
571 if (removeInstsThisCycle) {
572 cleanUpRemovedInsts();
573 }
574
575 if (!tickEvent.scheduled()) {
576 if (_status == SwitchedOut) {
577 DPRINTF(O3CPU, "Switched out!\n");
578 // increment stat
579 lastRunningCycle = curCycle();
580 } else if (!activityRec.active() || _status == Idle) {
581 DPRINTF(O3CPU, "Idle!\n");
582 lastRunningCycle = curCycle();
583 timesIdled++;
584 } else {
585 schedule(tickEvent, clockEdge(Cycles(1)));
586 DPRINTF(O3CPU, "Scheduling next tick!\n");
587 }
588 }
589
590 if (!FullSystem)
591 updateThreadPriority();
592
593 tryDrain();
594}
595
596template <class Impl>
597void
598FullO3CPU<Impl>::init()
599{
600 BaseCPU::init();
601
602 for (ThreadID tid = 0; tid < numThreads; ++tid) {
603 // Set noSquashFromTC so that the CPU doesn't squash when initially
604 // setting up registers.
605 thread[tid]->noSquashFromTC = true;
606 // Initialise the ThreadContext's memory proxies
607 thread[tid]->initMemProxies(thread[tid]->getTC());
608 }
609
610 if (FullSystem && !params()->switched_out) {
611 for (ThreadID tid = 0; tid < numThreads; tid++) {
612 ThreadContext *src_tc = threadContexts[tid];
613 TheISA::initCPU(src_tc, src_tc->contextId());
614 }
615 }
616
617 // Clear noSquashFromTC.
618 for (int tid = 0; tid < numThreads; ++tid)
619 thread[tid]->noSquashFromTC = false;
620
621 commit.setThreads(thread);
622}
623
624template <class Impl>
625void
626FullO3CPU<Impl>::startup()
627{
628 BaseCPU::startup();
629 for (int tid = 0; tid < numThreads; ++tid)
630 isa[tid]->startup(threadContexts[tid]);
631
632 fetch.startupStage();
633 decode.startupStage();
634 iew.startupStage();
635 rename.startupStage();
636 commit.startupStage();
637}
638
639template <class Impl>
640void
641FullO3CPU<Impl>::activateThread(ThreadID tid)
642{
643 list<ThreadID>::iterator isActive =
644 std::find(activeThreads.begin(), activeThreads.end(), tid);
645
646 DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid);
647 assert(!switchedOut());
648
649 if (isActive == activeThreads.end()) {
650 DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n",
651 tid);
652
653 activeThreads.push_back(tid);
654 }
655}
656
657template <class Impl>
658void
659FullO3CPU<Impl>::deactivateThread(ThreadID tid)
660{
661 //Remove From Active List, if Active
662 list<ThreadID>::iterator thread_it =
663 std::find(activeThreads.begin(), activeThreads.end(), tid);
664
665 DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid);
666 assert(!switchedOut());
667
668 if (thread_it != activeThreads.end()) {
669 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
670 tid);
671 activeThreads.erase(thread_it);
672 }
673
674 fetch.deactivateThread(tid);
675 commit.deactivateThread(tid);
676}
677
678template <class Impl>
679Counter
680FullO3CPU<Impl>::totalInsts() const
681{
682 Counter total(0);
683
684 ThreadID size = thread.size();
685 for (ThreadID i = 0; i < size; i++)
686 total += thread[i]->numInst;
687
688 return total;
689}
690
691template <class Impl>
692Counter
693FullO3CPU<Impl>::totalOps() const
694{
695 Counter total(0);
696
697 ThreadID size = thread.size();
698 for (ThreadID i = 0; i < size; i++)
699 total += thread[i]->numOp;
700
701 return total;
702}
703
704template <class Impl>
705void
706FullO3CPU<Impl>::activateContext(ThreadID tid)
707{
708 assert(!switchedOut());
709
710 // Needs to set each stage to running as well.
711 activateThread(tid);
712
713 // We don't want to wake the CPU if it is drained. In that case,
714 // we just want to flag the thread as active and schedule the tick
715 // event from drainResume() instead.
716 if (drainState() == DrainState::Drained)
717 return;
718
719 // If we are time 0 or if the last activation time is in the past,
720 // schedule the next tick and wake up the fetch unit
721 if (lastActivatedCycle == 0 || lastActivatedCycle < curTick()) {
722 scheduleTickEvent(Cycles(0));
723
724 // Be sure to signal that there's some activity so the CPU doesn't
725 // deschedule itself.
726 activityRec.activity();
727 fetch.wakeFromQuiesce();
728
729 Cycles cycles(curCycle() - lastRunningCycle);
730 // @todo: This is an oddity that is only here to match the stats
731 if (cycles != 0)
732 --cycles;
733 quiesceCycles += cycles;
734
735 lastActivatedCycle = curTick();
736
737 _status = Running;
738 }
739}
740
741template <class Impl>
742void
743FullO3CPU<Impl>::suspendContext(ThreadID tid)
744{
745 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
746 assert(!switchedOut());
747
748 deactivateThread(tid);
749
750 // If this was the last thread then unschedule the tick event.
751 if (activeThreads.size() == 0) {
752 unscheduleTickEvent();
753 lastRunningCycle = curCycle();
754 _status = Idle;
755 }
756
757 DPRINTF(Quiesce, "Suspending Context\n");
758}
759
760template <class Impl>
761void
762FullO3CPU<Impl>::haltContext(ThreadID tid)
763{
764 //For now, this is the same as deallocate
765 DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
766 assert(!switchedOut());
767
768 deactivateThread(tid);
769 removeThread(tid);
770}
771
772template <class Impl>
773void
774FullO3CPU<Impl>::insertThread(ThreadID tid)
775{
776 DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
777 // Will change now that the PC and thread state is internal to the CPU
778 // and not in the ThreadContext.
779 ThreadContext *src_tc;
780 if (FullSystem)
781 src_tc = system->threadContexts[tid];
782 else
783 src_tc = tcBase(tid);
784
785 //Bind Int Regs to Rename Map
786 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
787 PhysRegIndex phys_reg = freeList.getIntReg();
788
789 renameMap[tid].setEntry(ireg,phys_reg);
790 scoreboard.setReg(phys_reg);
791 }
792
793 //Bind Float Regs to Rename Map
794 int max_reg = TheISA::FP_Reg_Base + TheISA::NumFloatRegs;
795 for (int freg = TheISA::FP_Reg_Base; freg < max_reg; freg++) {
796 PhysRegIndex phys_reg = freeList.getFloatReg();
797
798 renameMap[tid].setEntry(freg,phys_reg);
799 scoreboard.setReg(phys_reg);
800 }
801
802 //Bind condition-code Regs to Rename Map
803 max_reg = TheISA::CC_Reg_Base + TheISA::NumCCRegs;
804 for (int creg = TheISA::CC_Reg_Base;
805 creg < max_reg; creg++) {
806 PhysRegIndex phys_reg = freeList.getCCReg();
807
808 renameMap[tid].setEntry(creg,phys_reg);
809 scoreboard.setReg(phys_reg);
810 }
811
812 //Copy Thread Data Into RegFile
813 //this->copyFromTC(tid);
814
815 //Set PC/NPC/NNPC
816 pcState(src_tc->pcState(), tid);
817
818 src_tc->setStatus(ThreadContext::Active);
819
820 activateContext(tid);
821
822 //Reset ROB/IQ/LSQ Entries
823 commit.rob->resetEntries();
824 iew.resetEntries();
825}
826
827template <class Impl>
828void
829FullO3CPU<Impl>::removeThread(ThreadID tid)
830{
831 DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
832
833 // Copy Thread Data From RegFile
834 // If thread is suspended, it might be re-allocated
835 // this->copyToTC(tid);
836
837
838 // @todo: 2-27-2008: Fix how we free up rename mappings
839 // here to alleviate the case for double-freeing registers
840 // in SMT workloads.
841
842 // Unbind Int Regs from Rename Map
843 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
844 PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
845 scoreboard.unsetReg(phys_reg);
846 freeList.addReg(phys_reg);
847 }
848
849 // Unbind Float Regs from Rename Map
850 int max_reg = TheISA::FP_Reg_Base + TheISA::NumFloatRegs;
851 for (int freg = TheISA::FP_Reg_Base; freg < max_reg; freg++) {
852 PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
853 scoreboard.unsetReg(phys_reg);
854 freeList.addReg(phys_reg);
855 }
856
857 // Unbind condition-code Regs from Rename Map
858 max_reg = TheISA::CC_Reg_Base + TheISA::NumCCRegs;
859 for (int creg = TheISA::CC_Reg_Base; creg < max_reg; creg++) {
860 PhysRegIndex phys_reg = renameMap[tid].lookup(creg);
861 scoreboard.unsetReg(phys_reg);
862 freeList.addReg(phys_reg);
863 }
864
865 // Squash Throughout Pipeline
866 DynInstPtr inst = commit.rob->readHeadInst(tid);
867 InstSeqNum squash_seq_num = inst->seqNum;
868 fetch.squash(0, squash_seq_num, inst, tid);
869 decode.squash(tid);
870 rename.squash(squash_seq_num, tid);
871 iew.squash(tid);
872 iew.ldstQueue.squash(squash_seq_num, tid);
873 commit.rob->squash(squash_seq_num, tid);
874
875
876 assert(iew.instQueue.getCount(tid) == 0);
877 assert(iew.ldstQueue.getCount(tid) == 0);
878
879 // Reset ROB/IQ/LSQ Entries
880
881 // Commented out for now. This should be possible to do by
882 // telling all the pipeline stages to drain first, and then
883 // checking until the drain completes. Once the pipeline is
884 // drained, call resetEntries(). - 10-09-06 ktlim
885/*
886 if (activeThreads.size() >= 1) {
887 commit.rob->resetEntries();
888 iew.resetEntries();
889 }
890*/
891}
892
893template <class Impl>
894Fault
895FullO3CPU<Impl>::hwrei(ThreadID tid)
896{
897#if THE_ISA == ALPHA_ISA
898 // Need to clear the lock flag upon returning from an interrupt.
899 this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
900
901 this->thread[tid]->kernelStats->hwrei();
902
903 // FIXME: XXX check for interrupts? XXX
904#endif
905 return NoFault;
906}
907
908template <class Impl>
909bool
910FullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid)
911{
912#if THE_ISA == ALPHA_ISA
913 if (this->thread[tid]->kernelStats)
914 this->thread[tid]->kernelStats->callpal(palFunc,
915 this->threadContexts[tid]);
916
917 switch (palFunc) {
918 case PAL::halt:
919 halt();
920 if (--System::numSystemsRunning == 0)
921 exitSimLoop("all cpus halted");
922 break;
923
924 case PAL::bpt:
925 case PAL::bugchk:
926 if (this->system->breakpoint())
927 return false;
928 break;
929 }
930#endif
931 return true;
932}
933
934template <class Impl>
935Fault
936FullO3CPU<Impl>::getInterrupts()
937{
938 // Check if there are any outstanding interrupts
939 return this->interrupts[0]->getInterrupt(this->threadContexts[0]);
940}
941
942template <class Impl>
943void
944FullO3CPU<Impl>::processInterrupts(const Fault &interrupt)
945{
946 // Check for interrupts here. For now can copy the code that
947 // exists within isa_fullsys_traits.hh. Also assume that thread 0
948 // is the one that handles the interrupts.
949 // @todo: Possibly consolidate the interrupt checking code.
950 // @todo: Allow other threads to handle interrupts.
951
952 assert(interrupt != NoFault);
953 this->interrupts[0]->updateIntrInfo(this->threadContexts[0]);
954
955 DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
956 this->trap(interrupt, 0, nullptr);
957}
958
959template <class Impl>
960void
961FullO3CPU<Impl>::trap(const Fault &fault, ThreadID tid,
962 const StaticInstPtr &inst)
963{
964 // Pass the thread's TC into the invoke method.
965 fault->invoke(this->threadContexts[tid], inst);
966}
967
968template <class Impl>
969void
970FullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid)
971{
972 DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid);
973
974 DPRINTF(Activity,"Activity: syscall() called.\n");
975
976 // Temporarily increase this by one to account for the syscall
977 // instruction.
978 ++(this->thread[tid]->funcExeInst);
979
980 // Execute the actual syscall.
981 this->thread[tid]->syscall(callnum);
982
983 // Decrease funcExeInst by one as the normal commit will handle
984 // incrementing it.
985 --(this->thread[tid]->funcExeInst);
986}
987
988template <class Impl>
989void
990FullO3CPU<Impl>::serializeThread(CheckpointOut &cp, ThreadID tid) const
991{
992 thread[tid]->serialize(cp);
993}
994
995template <class Impl>
996void
997FullO3CPU<Impl>::unserializeThread(CheckpointIn &cp, ThreadID tid)
998{
999 thread[tid]->unserialize(cp);
1000}
1001
1002template <class Impl>
1003DrainState
1004FullO3CPU<Impl>::drain()
1005{
1006 // If the CPU isn't doing anything, then return immediately.
1007 if (switchedOut())
1008 return DrainState::Drained;
1009
1010 DPRINTF(Drain, "Draining...\n");
1011
1012 // We only need to signal a drain to the commit stage as this
1013 // initiates squashing controls the draining. Once the commit
1014 // stage commits an instruction where it is safe to stop, it'll
1015 // squash the rest of the instructions in the pipeline and force
1016 // the fetch stage to stall. The pipeline will be drained once all
1017 // in-flight instructions have retired.
1018 commit.drain();
1019
1020 // Wake the CPU and record activity so everything can drain out if
1021 // the CPU was not able to immediately drain.
1022 if (!isDrained()) {
1023 wakeCPU();
1024 activityRec.activity();
1025
1026 DPRINTF(Drain, "CPU not drained\n");
1027
1028 return DrainState::Draining;
1029 } else {
1030 DPRINTF(Drain, "CPU is already drained\n");
1031 if (tickEvent.scheduled())
1032 deschedule(tickEvent);
1033
1034 // Flush out any old data from the time buffers. In
1035 // particular, there might be some data in flight from the
1036 // fetch stage that isn't visible in any of the CPU buffers we
1037 // test in isDrained().
1038 for (int i = 0; i < timeBuffer.getSize(); ++i) {
1039 timeBuffer.advance();
1040 fetchQueue.advance();
1041 decodeQueue.advance();
1042 renameQueue.advance();
1043 iewQueue.advance();
1044 }
1045
1046 drainSanityCheck();
1047 return DrainState::Drained;
1048 }
1049}
1050
1051template <class Impl>
1052bool
1053FullO3CPU<Impl>::tryDrain()
1054{
1055 if (drainState() != DrainState::Draining || !isDrained())
1056 return false;
1057
1058 if (tickEvent.scheduled())
1059 deschedule(tickEvent);
1060
1061 DPRINTF(Drain, "CPU done draining, processing drain event\n");
1062 signalDrainDone();
1063
1064 return true;
1065}
1066
1067template <class Impl>
1068void
1069FullO3CPU<Impl>::drainSanityCheck() const
1070{
1071 assert(isDrained());
1072 fetch.drainSanityCheck();
1073 decode.drainSanityCheck();
1074 rename.drainSanityCheck();
1075 iew.drainSanityCheck();
1076 commit.drainSanityCheck();
1077}
1078
1079template <class Impl>
1080bool
1081FullO3CPU<Impl>::isDrained() const
1082{
1083 bool drained(true);
1084
1085 if (!instList.empty() || !removeList.empty()) {
1086 DPRINTF(Drain, "Main CPU structures not drained.\n");
1087 drained = false;
1088 }
1089
1090 if (!fetch.isDrained()) {
1091 DPRINTF(Drain, "Fetch not drained.\n");
1092 drained = false;
1093 }
1094
1095 if (!decode.isDrained()) {
1096 DPRINTF(Drain, "Decode not drained.\n");
1097 drained = false;
1098 }
1099
1100 if (!rename.isDrained()) {
1101 DPRINTF(Drain, "Rename not drained.\n");
1102 drained = false;
1103 }
1104
1105 if (!iew.isDrained()) {
1106 DPRINTF(Drain, "IEW not drained.\n");
1107 drained = false;
1108 }
1109
1110 if (!commit.isDrained()) {
1111 DPRINTF(Drain, "Commit not drained.\n");
1112 drained = false;
1113 }
1114
1115 return drained;
1116}
1117
1118template <class Impl>
1119void
1120FullO3CPU<Impl>::commitDrained(ThreadID tid)
1121{
1122 fetch.drainStall(tid);
1123}
1124
1125template <class Impl>
1126void
1127FullO3CPU<Impl>::drainResume()
1128{
1129 if (switchedOut())
1130 return;
1131
1132 DPRINTF(Drain, "Resuming...\n");
1133 verifyMemoryMode();
1134
1135 fetch.drainResume();
1136 commit.drainResume();
1137
1138 _status = Idle;
1139 for (ThreadID i = 0; i < thread.size(); i++) {
1140 if (thread[i]->status() == ThreadContext::Active) {
1141 DPRINTF(Drain, "Activating thread: %i\n", i);
1142 activateThread(i);
1143 _status = Running;
1144 }
1145 }
1146
1147 assert(!tickEvent.scheduled());
1148 if (_status == Running)
1149 schedule(tickEvent, nextCycle());
1150}
1151
1152template <class Impl>
1153void
1154FullO3CPU<Impl>::switchOut()
1155{
1156 DPRINTF(O3CPU, "Switching out\n");
1157 BaseCPU::switchOut();
1158
1159 activityRec.reset();
1160
1161 _status = SwitchedOut;
1162
1163 if (checker)
1164 checker->switchOut();
1165}
1166
1167template <class Impl>
1168void
1169FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
1170{
1171 BaseCPU::takeOverFrom(oldCPU);
1172
1173 fetch.takeOverFrom();
1174 decode.takeOverFrom();
1175 rename.takeOverFrom();
1176 iew.takeOverFrom();
1177 commit.takeOverFrom();
1178
1179 assert(!tickEvent.scheduled());
1180
1181 FullO3CPU<Impl> *oldO3CPU = dynamic_cast<FullO3CPU<Impl>*>(oldCPU);
1182 if (oldO3CPU)
1183 globalSeqNum = oldO3CPU->globalSeqNum;
1184
1185 lastRunningCycle = curCycle();
1186 _status = Idle;
1187}
1188
1189template <class Impl>
1190void
1191FullO3CPU<Impl>::verifyMemoryMode() const
1192{
1193 if (!system->isTimingMode()) {
1194 fatal("The O3 CPU requires the memory system to be in "
1195 "'timing' mode.\n");
1196 }
1197}
1198
1199template <class Impl>
1200TheISA::MiscReg
1201FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
1202{
1203 return this->isa[tid]->readMiscRegNoEffect(misc_reg);
1204}
1205
1206template <class Impl>
1207TheISA::MiscReg
1208FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
1209{
1210 miscRegfileReads++;
1211 return this->isa[tid]->readMiscReg(misc_reg, tcBase(tid));
1212}
1213
1214template <class Impl>
1215void
1216FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
1217 const TheISA::MiscReg &val, ThreadID tid)
1218{
1219 this->isa[tid]->setMiscRegNoEffect(misc_reg, val);
1220}
1221
1222template <class Impl>
1223void
1224FullO3CPU<Impl>::setMiscReg(int misc_reg,
1225 const TheISA::MiscReg &val, ThreadID tid)
1226{
1227 miscRegfileWrites++;
1228 this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid));
1229}
1230
1231template <class Impl>
1232uint64_t
1233FullO3CPU<Impl>::readIntReg(int reg_idx)
1234{
1235 intRegfileReads++;
1236 return regFile.readIntReg(reg_idx);
1237}
1238
1239template <class Impl>
1240FloatReg
1241FullO3CPU<Impl>::readFloatReg(int reg_idx)
1242{
1243 fpRegfileReads++;
1244 return regFile.readFloatReg(reg_idx);
1245}
1246
1247template <class Impl>
1248FloatRegBits
1249FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
1250{
1251 fpRegfileReads++;
1252 return regFile.readFloatRegBits(reg_idx);
1253}
1254
1255template <class Impl>
1256CCReg
1257FullO3CPU<Impl>::readCCReg(int reg_idx)
1258{
1259 ccRegfileReads++;
1260 return regFile.readCCReg(reg_idx);
1261}
1262
1263template <class Impl>
1264void
1265FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
1266{
1267 intRegfileWrites++;
1268 regFile.setIntReg(reg_idx, val);
1269}
1270
1271template <class Impl>
1272void
1273FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
1274{
1275 fpRegfileWrites++;
1276 regFile.setFloatReg(reg_idx, val);
1277}
1278
1279template <class Impl>
1280void
1281FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
1282{
1283 fpRegfileWrites++;
1284 regFile.setFloatRegBits(reg_idx, val);
1285}
1286
1287template <class Impl>
1288void
1289FullO3CPU<Impl>::setCCReg(int reg_idx, CCReg val)
1290{
1291 ccRegfileWrites++;
1292 regFile.setCCReg(reg_idx, val);
1293}
1294
1295template <class Impl>
1296uint64_t
1297FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1298{
1299 intRegfileReads++;
1300 PhysRegIndex phys_reg = commitRenameMap[tid].lookupInt(reg_idx);
1301
1302 return regFile.readIntReg(phys_reg);
1303}
1304
1305template <class Impl>
1306float
1307FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
1308{
1309 fpRegfileReads++;
1310 PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1311
1312 return regFile.readFloatReg(phys_reg);
1313}
1314
1315template <class Impl>
1316uint64_t
1317FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid)
1318{
1319 fpRegfileReads++;
1320 PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1321
1322 return regFile.readFloatRegBits(phys_reg);
1323}
1324
1325template <class Impl>
1326CCReg
1327FullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid)
1328{
1329 ccRegfileReads++;
1330 PhysRegIndex phys_reg = commitRenameMap[tid].lookupCC(reg_idx);
1331
1332 return regFile.readCCReg(phys_reg);
1333}
1334
1335template <class Impl>
1336void
1337FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
1338{
1339 intRegfileWrites++;
1340 PhysRegIndex phys_reg = commitRenameMap[tid].lookupInt(reg_idx);
1341
1342 regFile.setIntReg(phys_reg, val);
1343}
1344
1345template <class Impl>
1346void
1347FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid)
1348{
1349 fpRegfileWrites++;
1350 PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1351
1352 regFile.setFloatReg(phys_reg, val);
1353}
1354
1355template <class Impl>
1356void
1357FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid)
1358{
1359 fpRegfileWrites++;
1360 PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1361
1362 regFile.setFloatRegBits(phys_reg, val);
1363}
1364
1365template <class Impl>
1366void
1367FullO3CPU<Impl>::setArchCCReg(int reg_idx, CCReg val, ThreadID tid)
1368{
1369 ccRegfileWrites++;
1370 PhysRegIndex phys_reg = commitRenameMap[tid].lookupCC(reg_idx);
1371
1372 regFile.setCCReg(phys_reg, val);
1373}
1374
1375template <class Impl>
1376TheISA::PCState
1377FullO3CPU<Impl>::pcState(ThreadID tid)
1378{
1379 return commit.pcState(tid);
1380}
1381
1382template <class Impl>
1383void
1384FullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid)
1385{
1386 commit.pcState(val, tid);
1387}
1388
1389template <class Impl>
1390Addr
1391FullO3CPU<Impl>::instAddr(ThreadID tid)
1392{
1393 return commit.instAddr(tid);
1394}
1395
1396template <class Impl>
1397Addr
1398FullO3CPU<Impl>::nextInstAddr(ThreadID tid)
1399{
1400 return commit.nextInstAddr(tid);
1401}
1402
1403template <class Impl>
1404MicroPC
1405FullO3CPU<Impl>::microPC(ThreadID tid)
1406{
1407 return commit.microPC(tid);
1408}
1409
1410template <class Impl>
1411void
1412FullO3CPU<Impl>::squashFromTC(ThreadID tid)
1413{
1414 this->thread[tid]->noSquashFromTC = true;
1415 this->commit.generateTCEvent(tid);
1416}
1417
1418template <class Impl>
1419typename FullO3CPU<Impl>::ListIt
1420FullO3CPU<Impl>::addInst(DynInstPtr &inst)
1421{
1422 instList.push_back(inst);
1423
1424 return --(instList.end());
1425}
1426
1427template <class Impl>
1428void
1429FullO3CPU<Impl>::instDone(ThreadID tid, DynInstPtr &inst)
1430{
1431 // Keep an instruction count.
1432 if (!inst->isMicroop() || inst->isLastMicroop()) {
1433 thread[tid]->numInst++;
1434 thread[tid]->numInsts++;
1435 committedInsts[tid]++;
1436 system->totalNumInsts++;
1437
1438 // Check for instruction-count-based events.
1439 comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1440 system->instEventQueue.serviceEvents(system->totalNumInsts);
1441 }
1442 thread[tid]->numOp++;
1443 thread[tid]->numOps++;
1444 committedOps[tid]++;
1445
1446 probeInstCommit(inst->staticInst);
1447}
1448
1449template <class Impl>
1450void
1451FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
1452{
1453 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s "
1454 "[sn:%lli]\n",
1455 inst->threadNumber, inst->pcState(), inst->seqNum);
1456
1457 removeInstsThisCycle = true;
1458
1459 // Remove the front instruction.
1460 removeList.push(inst->getInstListIt());
1461}
1462
1463template <class Impl>
1464void
1465FullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid)
1466{
1467 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1468 " list.\n", tid);
1469
1470 ListIt end_it;
1471
1472 bool rob_empty = false;
1473
1474 if (instList.empty()) {
1475 return;
1476 } else if (rob.isEmpty(tid)) {
1477 DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1478 end_it = instList.begin();
1479 rob_empty = true;
1480 } else {
1481 end_it = (rob.readTailInst(tid))->getInstListIt();
1482 DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1483 }
1484
1485 removeInstsThisCycle = true;
1486
1487 ListIt inst_it = instList.end();
1488
1489 inst_it--;
1490
1491 // Walk through the instruction list, removing any instructions
1492 // that were inserted after the given instruction iterator, end_it.
1493 while (inst_it != end_it) {
1494 assert(!instList.empty());
1495
1496 squashInstIt(inst_it, tid);
1497
1498 inst_it--;
1499 }
1500
1501 // If the ROB was empty, then we actually need to remove the first
1502 // instruction as well.
1503 if (rob_empty) {
1504 squashInstIt(inst_it, tid);
1505 }
1506}
1507
1508template <class Impl>
1509void
1510FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1511{
1512 assert(!instList.empty());
1513
1514 removeInstsThisCycle = true;
1515
1516 ListIt inst_iter = instList.end();
1517
1518 inst_iter--;
1519
1520 DPRINTF(O3CPU, "Deleting instructions from instruction "
1521 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1522 tid, seq_num, (*inst_iter)->seqNum);
1523
1524 while ((*inst_iter)->seqNum > seq_num) {
1525
1526 bool break_loop = (inst_iter == instList.begin());
1527
1528 squashInstIt(inst_iter, tid);
1529
1530 inst_iter--;
1531
1532 if (break_loop)
1533 break;
1534 }
1535}
1536
1537template <class Impl>
1538inline void
1539FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid)
1540{
1541 if ((*instIt)->threadNumber == tid) {
1542 DPRINTF(O3CPU, "Squashing instruction, "
1543 "[tid:%i] [sn:%lli] PC %s\n",
1544 (*instIt)->threadNumber,
1545 (*instIt)->seqNum,
1546 (*instIt)->pcState());
1547
1548 // Mark it as squashed.
1549 (*instIt)->setSquashed();
1550
1551 // @todo: Formulate a consistent method for deleting
1552 // instructions from the instruction list
1553 // Remove the instruction from the list.
1554 removeList.push(instIt);
1555 }
1556}
1557
1558template <class Impl>
1559void
1560FullO3CPU<Impl>::cleanUpRemovedInsts()
1561{
1562 while (!removeList.empty()) {
1563 DPRINTF(O3CPU, "Removing instruction, "
1564 "[tid:%i] [sn:%lli] PC %s\n",
1565 (*removeList.front())->threadNumber,
1566 (*removeList.front())->seqNum,
1567 (*removeList.front())->pcState());
1568
1569 instList.erase(removeList.front());
1570
1571 removeList.pop();
1572 }
1573
1574 removeInstsThisCycle = false;
1575}
1576/*
1577template <class Impl>
1578void
1579FullO3CPU<Impl>::removeAllInsts()
1580{
1581 instList.clear();
1582}
1583*/
1584template <class Impl>
1585void
1586FullO3CPU<Impl>::dumpInsts()
1587{
1588 int num = 0;
1589
1590 ListIt inst_list_it = instList.begin();
1591
1592 cprintf("Dumping Instruction List\n");
1593
1594 while (inst_list_it != instList.end()) {
1595 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1596 "Squashed:%i\n\n",
1597 num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber,
1598 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1599 (*inst_list_it)->isSquashed());
1600 inst_list_it++;
1601 ++num;
1602 }
1603}
1604/*
1605template <class Impl>
1606void
1607FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
1608{
1609 iew.wakeDependents(inst);
1610}
1611*/
1612template <class Impl>
1613void
1614FullO3CPU<Impl>::wakeCPU()
1615{
1616 if (activityRec.active() || tickEvent.scheduled()) {
1617 DPRINTF(Activity, "CPU already running.\n");
1618 return;
1619 }
1620
1621 DPRINTF(Activity, "Waking up CPU\n");
1622
1623 Cycles cycles(curCycle() - lastRunningCycle);
1624 // @todo: This is an oddity that is only here to match the stats
1625 if (cycles > 1) {
1626 --cycles;
1627 idleCycles += cycles;
1628 numCycles += cycles;
1629 ppCycles->notify(cycles);
1630 }
1631
1632 schedule(tickEvent, clockEdge());
1633}
1634
1635template <class Impl>
1636void
1637FullO3CPU<Impl>::wakeup(ThreadID tid)
1638{
1639 if (this->thread[tid]->status() != ThreadContext::Suspended)
1640 return;
1641
1642 this->wakeCPU();
1643
1644 DPRINTF(Quiesce, "Suspended Processor woken\n");
1645 this->threadContexts[tid]->activate();
1646}
1647
1648template <class Impl>
1649ThreadID
1650FullO3CPU<Impl>::getFreeTid()
1651{
1652 for (ThreadID tid = 0; tid < numThreads; tid++) {
1653 if (!tids[tid]) {
1654 tids[tid] = true;
1655 return tid;
1656 }
1657 }
1658
1659 return InvalidThreadID;
1660}
1661
1662template <class Impl>
1663void
1664FullO3CPU<Impl>::updateThreadPriority()
1665{
1666 if (activeThreads.size() > 1) {
1667 //DEFAULT TO ROUND ROBIN SCHEME
1668 //e.g. Move highest priority to end of thread list
1669 list<ThreadID>::iterator list_begin = activeThreads.begin();
1670
1671 unsigned high_thread = *list_begin;
1672
1673 activeThreads.erase(list_begin);
1674
1675 activeThreads.push_back(high_thread);
1676 }
1677}
1678
1679// Forward declaration of FullO3CPU.
1680template class FullO3CPU<O3CPUImpl>;
| 98 fetch->processCacheCompletion(pkt);
99
100 return true;
101}
102
103template<class Impl>
104void
105FullO3CPU<Impl>::IcachePort::recvReqRetry()
106{
107 fetch->recvReqRetry();
108}
109
110template <class Impl>
111bool
112FullO3CPU<Impl>::DcachePort::recvTimingResp(PacketPtr pkt)
113{
114 return lsq->recvTimingResp(pkt);
115}
116
117template <class Impl>
118void
119FullO3CPU<Impl>::DcachePort::recvTimingSnoopReq(PacketPtr pkt)
120{
121 for (ThreadID tid = 0; tid < cpu->numThreads; tid++) {
122 if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) {
123 cpu->wakeup(tid);
124 }
125 }
126 lsq->recvTimingSnoopReq(pkt);
127}
128
129template <class Impl>
130void
131FullO3CPU<Impl>::DcachePort::recvReqRetry()
132{
133 lsq->recvReqRetry();
134}
135
136template <class Impl>
137FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
138 : Event(CPU_Tick_Pri), cpu(c)
139{
140}
141
142template <class Impl>
143void
144FullO3CPU<Impl>::TickEvent::process()
145{
146 cpu->tick();
147}
148
149template <class Impl>
150const char *
151FullO3CPU<Impl>::TickEvent::description() const
152{
153 return "FullO3CPU tick";
154}
155
156template <class Impl>
157FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
158 : BaseO3CPU(params),
159 itb(params->itb),
160 dtb(params->dtb),
161 tickEvent(this),
162#ifndef NDEBUG
163 instcount(0),
164#endif
165 removeInstsThisCycle(false),
166 fetch(this, params),
167 decode(this, params),
168 rename(this, params),
169 iew(this, params),
170 commit(this, params),
171
172 regFile(params->numPhysIntRegs,
173 params->numPhysFloatRegs,
174 params->numPhysCCRegs),
175
176 freeList(name() + ".freelist", ®File),
177
178 rob(this, params),
179
180 scoreboard(name() + ".scoreboard",
181 regFile.totalNumPhysRegs(), TheISA::NumMiscRegs,
182 TheISA::ZeroReg, TheISA::ZeroReg),
183
184 isa(numThreads, NULL),
185
186 icachePort(&fetch, this),
187 dcachePort(&iew.ldstQueue, this),
188
189 timeBuffer(params->backComSize, params->forwardComSize),
190 fetchQueue(params->backComSize, params->forwardComSize),
191 decodeQueue(params->backComSize, params->forwardComSize),
192 renameQueue(params->backComSize, params->forwardComSize),
193 iewQueue(params->backComSize, params->forwardComSize),
194 activityRec(name(), NumStages,
195 params->backComSize + params->forwardComSize,
196 params->activity),
197
198 globalSeqNum(1),
199 system(params->system),
200 lastRunningCycle(curCycle())
201{
202 if (!params->switched_out) {
203 _status = Running;
204 } else {
205 _status = SwitchedOut;
206 }
207
208 if (params->checker) {
209 BaseCPU *temp_checker = params->checker;
210 checker = dynamic_cast<Checker<Impl> *>(temp_checker);
211 checker->setIcachePort(&icachePort);
212 checker->setSystem(params->system);
213 } else {
214 checker = NULL;
215 }
216
217 if (!FullSystem) {
218 thread.resize(numThreads);
219 tids.resize(numThreads);
220 }
221
222 // The stages also need their CPU pointer setup. However this
223 // must be done at the upper level CPU because they have pointers
224 // to the upper level CPU, and not this FullO3CPU.
225
226 // Set up Pointers to the activeThreads list for each stage
227 fetch.setActiveThreads(&activeThreads);
228 decode.setActiveThreads(&activeThreads);
229 rename.setActiveThreads(&activeThreads);
230 iew.setActiveThreads(&activeThreads);
231 commit.setActiveThreads(&activeThreads);
232
233 // Give each of the stages the time buffer they will use.
234 fetch.setTimeBuffer(&timeBuffer);
235 decode.setTimeBuffer(&timeBuffer);
236 rename.setTimeBuffer(&timeBuffer);
237 iew.setTimeBuffer(&timeBuffer);
238 commit.setTimeBuffer(&timeBuffer);
239
240 // Also setup each of the stages' queues.
241 fetch.setFetchQueue(&fetchQueue);
242 decode.setFetchQueue(&fetchQueue);
243 commit.setFetchQueue(&fetchQueue);
244 decode.setDecodeQueue(&decodeQueue);
245 rename.setDecodeQueue(&decodeQueue);
246 rename.setRenameQueue(&renameQueue);
247 iew.setRenameQueue(&renameQueue);
248 iew.setIEWQueue(&iewQueue);
249 commit.setIEWQueue(&iewQueue);
250 commit.setRenameQueue(&renameQueue);
251
252 commit.setIEWStage(&iew);
253 rename.setIEWStage(&iew);
254 rename.setCommitStage(&commit);
255
256 ThreadID active_threads;
257 if (FullSystem) {
258 active_threads = 1;
259 } else {
260 active_threads = params->workload.size();
261
262 if (active_threads > Impl::MaxThreads) {
263 panic("Workload Size too large. Increase the 'MaxThreads' "
264 "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) "
265 "or edit your workload size.");
266 }
267 }
268
269 //Make Sure That this a Valid Architeture
270 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs);
271 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
272 assert(params->numPhysCCRegs >= numThreads * TheISA::NumCCRegs);
273
274 rename.setScoreboard(&scoreboard);
275 iew.setScoreboard(&scoreboard);
276
277 // Setup the rename map for whichever stages need it.
278 for (ThreadID tid = 0; tid < numThreads; tid++) {
279 isa[tid] = params->isa[tid];
280
281 // Only Alpha has an FP zero register, so for other ISAs we
282 // use an invalid FP register index to avoid special treatment
283 // of any valid FP reg.
284 RegIndex invalidFPReg = TheISA::NumFloatRegs + 1;
285 RegIndex fpZeroReg =
286 (THE_ISA == ALPHA_ISA) ? TheISA::ZeroReg : invalidFPReg;
287
288 commitRenameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg,
289 &freeList);
290
291 renameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg,
292 &freeList);
293 }
294
295 // Initialize rename map to assign physical registers to the
296 // architectural registers for active threads only.
297 for (ThreadID tid = 0; tid < active_threads; tid++) {
298 for (RegIndex ridx = 0; ridx < TheISA::NumIntRegs; ++ridx) {
299 // Note that we can't use the rename() method because we don't
300 // want special treatment for the zero register at this point
301 PhysRegIndex phys_reg = freeList.getIntReg();
302 renameMap[tid].setIntEntry(ridx, phys_reg);
303 commitRenameMap[tid].setIntEntry(ridx, phys_reg);
304 }
305
306 for (RegIndex ridx = 0; ridx < TheISA::NumFloatRegs; ++ridx) {
307 PhysRegIndex phys_reg = freeList.getFloatReg();
308 renameMap[tid].setFloatEntry(ridx, phys_reg);
309 commitRenameMap[tid].setFloatEntry(ridx, phys_reg);
310 }
311
312 for (RegIndex ridx = 0; ridx < TheISA::NumCCRegs; ++ridx) {
313 PhysRegIndex phys_reg = freeList.getCCReg();
314 renameMap[tid].setCCEntry(ridx, phys_reg);
315 commitRenameMap[tid].setCCEntry(ridx, phys_reg);
316 }
317 }
318
319 rename.setRenameMap(renameMap);
320 commit.setRenameMap(commitRenameMap);
321 rename.setFreeList(&freeList);
322
323 // Setup the ROB for whichever stages need it.
324 commit.setROB(&rob);
325
326 lastActivatedCycle = 0;
327#if 0
328 // Give renameMap & rename stage access to the freeList;
329 for (ThreadID tid = 0; tid < numThreads; tid++)
330 globalSeqNum[tid] = 1;
331#endif
332
333 DPRINTF(O3CPU, "Creating O3CPU object.\n");
334
335 // Setup any thread state.
336 this->thread.resize(this->numThreads);
337
338 for (ThreadID tid = 0; tid < this->numThreads; ++tid) {
339 if (FullSystem) {
340 // SMT is not supported in FS mode yet.
341 assert(this->numThreads == 1);
342 this->thread[tid] = new Thread(this, 0, NULL);
343 } else {
344 if (tid < params->workload.size()) {
345 DPRINTF(O3CPU, "Workload[%i] process is %#x",
346 tid, this->thread[tid]);
347 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
348 (typename Impl::O3CPU *)(this),
349 tid, params->workload[tid]);
350
351 //usedTids[tid] = true;
352 //threadMap[tid] = tid;
353 } else {
354 //Allocate Empty thread so M5 can use later
355 //when scheduling threads to CPU
356 Process* dummy_proc = NULL;
357
358 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
359 (typename Impl::O3CPU *)(this),
360 tid, dummy_proc);
361 //usedTids[tid] = false;
362 }
363 }
364
365 ThreadContext *tc;
366
367 // Setup the TC that will serve as the interface to the threads/CPU.
368 O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>;
369
370 tc = o3_tc;
371
372 // If we're using a checker, then the TC should be the
373 // CheckerThreadContext.
374 if (params->checker) {
375 tc = new CheckerThreadContext<O3ThreadContext<Impl> >(
376 o3_tc, this->checker);
377 }
378
379 o3_tc->cpu = (typename Impl::O3CPU *)(this);
380 assert(o3_tc->cpu);
381 o3_tc->thread = this->thread[tid];
382
383 if (FullSystem) {
384 // Setup quiesce event.
385 this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
386 }
387 // Give the thread the TC.
388 this->thread[tid]->tc = tc;
389
390 // Add the TC to the CPU's list of TC's.
391 this->threadContexts.push_back(tc);
392 }
393
394 // FullO3CPU always requires an interrupt controller.
395 if (!params->switched_out && interrupts.empty()) {
396 fatal("FullO3CPU %s has no interrupt controller.\n"
397 "Ensure createInterruptController() is called.\n", name());
398 }
399
400 for (ThreadID tid = 0; tid < this->numThreads; tid++)
401 this->thread[tid]->setFuncExeInst(0);
402}
403
404template <class Impl>
405FullO3CPU<Impl>::~FullO3CPU()
406{
407}
408
409template <class Impl>
410void
411FullO3CPU<Impl>::regProbePoints()
412{
413 BaseCPU::regProbePoints();
414
415 ppInstAccessComplete = new ProbePointArg<PacketPtr>(getProbeManager(), "InstAccessComplete");
416 ppDataAccessComplete = new ProbePointArg<std::pair<DynInstPtr, PacketPtr> >(getProbeManager(), "DataAccessComplete");
417
418 fetch.regProbePoints();
419 rename.regProbePoints();
420 iew.regProbePoints();
421 commit.regProbePoints();
422}
423
424template <class Impl>
425void
426FullO3CPU<Impl>::regStats()
427{
428 BaseO3CPU::regStats();
429
430 // Register any of the O3CPU's stats here.
431 timesIdled
432 .name(name() + ".timesIdled")
433 .desc("Number of times that the entire CPU went into an idle state and"
434 " unscheduled itself")
435 .prereq(timesIdled);
436
437 idleCycles
438 .name(name() + ".idleCycles")
439 .desc("Total number of cycles that the CPU has spent unscheduled due "
440 "to idling")
441 .prereq(idleCycles);
442
443 quiesceCycles
444 .name(name() + ".quiesceCycles")
445 .desc("Total number of cycles that CPU has spent quiesced or waiting "
446 "for an interrupt")
447 .prereq(quiesceCycles);
448
449 // Number of Instructions simulated
450 // --------------------------------
451 // Should probably be in Base CPU but need templated
452 // MaxThreads so put in here instead
453 committedInsts
454 .init(numThreads)
455 .name(name() + ".committedInsts")
456 .desc("Number of Instructions Simulated")
457 .flags(Stats::total);
458
459 committedOps
460 .init(numThreads)
461 .name(name() + ".committedOps")
462 .desc("Number of Ops (including micro ops) Simulated")
463 .flags(Stats::total);
464
465 cpi
466 .name(name() + ".cpi")
467 .desc("CPI: Cycles Per Instruction")
468 .precision(6);
469 cpi = numCycles / committedInsts;
470
471 totalCpi
472 .name(name() + ".cpi_total")
473 .desc("CPI: Total CPI of All Threads")
474 .precision(6);
475 totalCpi = numCycles / sum(committedInsts);
476
477 ipc
478 .name(name() + ".ipc")
479 .desc("IPC: Instructions Per Cycle")
480 .precision(6);
481 ipc = committedInsts / numCycles;
482
483 totalIpc
484 .name(name() + ".ipc_total")
485 .desc("IPC: Total IPC of All Threads")
486 .precision(6);
487 totalIpc = sum(committedInsts) / numCycles;
488
489 this->fetch.regStats();
490 this->decode.regStats();
491 this->rename.regStats();
492 this->iew.regStats();
493 this->commit.regStats();
494 this->rob.regStats();
495
496 intRegfileReads
497 .name(name() + ".int_regfile_reads")
498 .desc("number of integer regfile reads")
499 .prereq(intRegfileReads);
500
501 intRegfileWrites
502 .name(name() + ".int_regfile_writes")
503 .desc("number of integer regfile writes")
504 .prereq(intRegfileWrites);
505
506 fpRegfileReads
507 .name(name() + ".fp_regfile_reads")
508 .desc("number of floating regfile reads")
509 .prereq(fpRegfileReads);
510
511 fpRegfileWrites
512 .name(name() + ".fp_regfile_writes")
513 .desc("number of floating regfile writes")
514 .prereq(fpRegfileWrites);
515
516 ccRegfileReads
517 .name(name() + ".cc_regfile_reads")
518 .desc("number of cc regfile reads")
519 .prereq(ccRegfileReads);
520
521 ccRegfileWrites
522 .name(name() + ".cc_regfile_writes")
523 .desc("number of cc regfile writes")
524 .prereq(ccRegfileWrites);
525
526 miscRegfileReads
527 .name(name() + ".misc_regfile_reads")
528 .desc("number of misc regfile reads")
529 .prereq(miscRegfileReads);
530
531 miscRegfileWrites
532 .name(name() + ".misc_regfile_writes")
533 .desc("number of misc regfile writes")
534 .prereq(miscRegfileWrites);
535}
536
537template <class Impl>
538void
539FullO3CPU<Impl>::tick()
540{
541 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
542 assert(!switchedOut());
543 assert(drainState() != DrainState::Drained);
544
545 ++numCycles;
546 ppCycles->notify(1);
547
548// activity = false;
549
550 //Tick each of the stages
551 fetch.tick();
552
553 decode.tick();
554
555 rename.tick();
556
557 iew.tick();
558
559 commit.tick();
560
561 // Now advance the time buffers
562 timeBuffer.advance();
563
564 fetchQueue.advance();
565 decodeQueue.advance();
566 renameQueue.advance();
567 iewQueue.advance();
568
569 activityRec.advance();
570
571 if (removeInstsThisCycle) {
572 cleanUpRemovedInsts();
573 }
574
575 if (!tickEvent.scheduled()) {
576 if (_status == SwitchedOut) {
577 DPRINTF(O3CPU, "Switched out!\n");
578 // increment stat
579 lastRunningCycle = curCycle();
580 } else if (!activityRec.active() || _status == Idle) {
581 DPRINTF(O3CPU, "Idle!\n");
582 lastRunningCycle = curCycle();
583 timesIdled++;
584 } else {
585 schedule(tickEvent, clockEdge(Cycles(1)));
586 DPRINTF(O3CPU, "Scheduling next tick!\n");
587 }
588 }
589
590 if (!FullSystem)
591 updateThreadPriority();
592
593 tryDrain();
594}
595
596template <class Impl>
597void
598FullO3CPU<Impl>::init()
599{
600 BaseCPU::init();
601
602 for (ThreadID tid = 0; tid < numThreads; ++tid) {
603 // Set noSquashFromTC so that the CPU doesn't squash when initially
604 // setting up registers.
605 thread[tid]->noSquashFromTC = true;
606 // Initialise the ThreadContext's memory proxies
607 thread[tid]->initMemProxies(thread[tid]->getTC());
608 }
609
610 if (FullSystem && !params()->switched_out) {
611 for (ThreadID tid = 0; tid < numThreads; tid++) {
612 ThreadContext *src_tc = threadContexts[tid];
613 TheISA::initCPU(src_tc, src_tc->contextId());
614 }
615 }
616
617 // Clear noSquashFromTC.
618 for (int tid = 0; tid < numThreads; ++tid)
619 thread[tid]->noSquashFromTC = false;
620
621 commit.setThreads(thread);
622}
623
624template <class Impl>
625void
626FullO3CPU<Impl>::startup()
627{
628 BaseCPU::startup();
629 for (int tid = 0; tid < numThreads; ++tid)
630 isa[tid]->startup(threadContexts[tid]);
631
632 fetch.startupStage();
633 decode.startupStage();
634 iew.startupStage();
635 rename.startupStage();
636 commit.startupStage();
637}
638
639template <class Impl>
640void
641FullO3CPU<Impl>::activateThread(ThreadID tid)
642{
643 list<ThreadID>::iterator isActive =
644 std::find(activeThreads.begin(), activeThreads.end(), tid);
645
646 DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid);
647 assert(!switchedOut());
648
649 if (isActive == activeThreads.end()) {
650 DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n",
651 tid);
652
653 activeThreads.push_back(tid);
654 }
655}
656
657template <class Impl>
658void
659FullO3CPU<Impl>::deactivateThread(ThreadID tid)
660{
661 //Remove From Active List, if Active
662 list<ThreadID>::iterator thread_it =
663 std::find(activeThreads.begin(), activeThreads.end(), tid);
664
665 DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid);
666 assert(!switchedOut());
667
668 if (thread_it != activeThreads.end()) {
669 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
670 tid);
671 activeThreads.erase(thread_it);
672 }
673
674 fetch.deactivateThread(tid);
675 commit.deactivateThread(tid);
676}
677
678template <class Impl>
679Counter
680FullO3CPU<Impl>::totalInsts() const
681{
682 Counter total(0);
683
684 ThreadID size = thread.size();
685 for (ThreadID i = 0; i < size; i++)
686 total += thread[i]->numInst;
687
688 return total;
689}
690
691template <class Impl>
692Counter
693FullO3CPU<Impl>::totalOps() const
694{
695 Counter total(0);
696
697 ThreadID size = thread.size();
698 for (ThreadID i = 0; i < size; i++)
699 total += thread[i]->numOp;
700
701 return total;
702}
703
704template <class Impl>
705void
706FullO3CPU<Impl>::activateContext(ThreadID tid)
707{
708 assert(!switchedOut());
709
710 // Needs to set each stage to running as well.
711 activateThread(tid);
712
713 // We don't want to wake the CPU if it is drained. In that case,
714 // we just want to flag the thread as active and schedule the tick
715 // event from drainResume() instead.
716 if (drainState() == DrainState::Drained)
717 return;
718
719 // If we are time 0 or if the last activation time is in the past,
720 // schedule the next tick and wake up the fetch unit
721 if (lastActivatedCycle == 0 || lastActivatedCycle < curTick()) {
722 scheduleTickEvent(Cycles(0));
723
724 // Be sure to signal that there's some activity so the CPU doesn't
725 // deschedule itself.
726 activityRec.activity();
727 fetch.wakeFromQuiesce();
728
729 Cycles cycles(curCycle() - lastRunningCycle);
730 // @todo: This is an oddity that is only here to match the stats
731 if (cycles != 0)
732 --cycles;
733 quiesceCycles += cycles;
734
735 lastActivatedCycle = curTick();
736
737 _status = Running;
738 }
739}
740
741template <class Impl>
742void
743FullO3CPU<Impl>::suspendContext(ThreadID tid)
744{
745 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
746 assert(!switchedOut());
747
748 deactivateThread(tid);
749
750 // If this was the last thread then unschedule the tick event.
751 if (activeThreads.size() == 0) {
752 unscheduleTickEvent();
753 lastRunningCycle = curCycle();
754 _status = Idle;
755 }
756
757 DPRINTF(Quiesce, "Suspending Context\n");
758}
759
760template <class Impl>
761void
762FullO3CPU<Impl>::haltContext(ThreadID tid)
763{
764 //For now, this is the same as deallocate
765 DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
766 assert(!switchedOut());
767
768 deactivateThread(tid);
769 removeThread(tid);
770}
771
772template <class Impl>
773void
774FullO3CPU<Impl>::insertThread(ThreadID tid)
775{
776 DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
777 // Will change now that the PC and thread state is internal to the CPU
778 // and not in the ThreadContext.
779 ThreadContext *src_tc;
780 if (FullSystem)
781 src_tc = system->threadContexts[tid];
782 else
783 src_tc = tcBase(tid);
784
785 //Bind Int Regs to Rename Map
786 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
787 PhysRegIndex phys_reg = freeList.getIntReg();
788
789 renameMap[tid].setEntry(ireg,phys_reg);
790 scoreboard.setReg(phys_reg);
791 }
792
793 //Bind Float Regs to Rename Map
794 int max_reg = TheISA::FP_Reg_Base + TheISA::NumFloatRegs;
795 for (int freg = TheISA::FP_Reg_Base; freg < max_reg; freg++) {
796 PhysRegIndex phys_reg = freeList.getFloatReg();
797
798 renameMap[tid].setEntry(freg,phys_reg);
799 scoreboard.setReg(phys_reg);
800 }
801
802 //Bind condition-code Regs to Rename Map
803 max_reg = TheISA::CC_Reg_Base + TheISA::NumCCRegs;
804 for (int creg = TheISA::CC_Reg_Base;
805 creg < max_reg; creg++) {
806 PhysRegIndex phys_reg = freeList.getCCReg();
807
808 renameMap[tid].setEntry(creg,phys_reg);
809 scoreboard.setReg(phys_reg);
810 }
811
812 //Copy Thread Data Into RegFile
813 //this->copyFromTC(tid);
814
815 //Set PC/NPC/NNPC
816 pcState(src_tc->pcState(), tid);
817
818 src_tc->setStatus(ThreadContext::Active);
819
820 activateContext(tid);
821
822 //Reset ROB/IQ/LSQ Entries
823 commit.rob->resetEntries();
824 iew.resetEntries();
825}
826
827template <class Impl>
828void
829FullO3CPU<Impl>::removeThread(ThreadID tid)
830{
831 DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
832
833 // Copy Thread Data From RegFile
834 // If thread is suspended, it might be re-allocated
835 // this->copyToTC(tid);
836
837
838 // @todo: 2-27-2008: Fix how we free up rename mappings
839 // here to alleviate the case for double-freeing registers
840 // in SMT workloads.
841
842 // Unbind Int Regs from Rename Map
843 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
844 PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
845 scoreboard.unsetReg(phys_reg);
846 freeList.addReg(phys_reg);
847 }
848
849 // Unbind Float Regs from Rename Map
850 int max_reg = TheISA::FP_Reg_Base + TheISA::NumFloatRegs;
851 for (int freg = TheISA::FP_Reg_Base; freg < max_reg; freg++) {
852 PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
853 scoreboard.unsetReg(phys_reg);
854 freeList.addReg(phys_reg);
855 }
856
857 // Unbind condition-code Regs from Rename Map
858 max_reg = TheISA::CC_Reg_Base + TheISA::NumCCRegs;
859 for (int creg = TheISA::CC_Reg_Base; creg < max_reg; creg++) {
860 PhysRegIndex phys_reg = renameMap[tid].lookup(creg);
861 scoreboard.unsetReg(phys_reg);
862 freeList.addReg(phys_reg);
863 }
864
865 // Squash Throughout Pipeline
866 DynInstPtr inst = commit.rob->readHeadInst(tid);
867 InstSeqNum squash_seq_num = inst->seqNum;
868 fetch.squash(0, squash_seq_num, inst, tid);
869 decode.squash(tid);
870 rename.squash(squash_seq_num, tid);
871 iew.squash(tid);
872 iew.ldstQueue.squash(squash_seq_num, tid);
873 commit.rob->squash(squash_seq_num, tid);
874
875
876 assert(iew.instQueue.getCount(tid) == 0);
877 assert(iew.ldstQueue.getCount(tid) == 0);
878
879 // Reset ROB/IQ/LSQ Entries
880
881 // Commented out for now. This should be possible to do by
882 // telling all the pipeline stages to drain first, and then
883 // checking until the drain completes. Once the pipeline is
884 // drained, call resetEntries(). - 10-09-06 ktlim
885/*
886 if (activeThreads.size() >= 1) {
887 commit.rob->resetEntries();
888 iew.resetEntries();
889 }
890*/
891}
892
893template <class Impl>
894Fault
895FullO3CPU<Impl>::hwrei(ThreadID tid)
896{
897#if THE_ISA == ALPHA_ISA
898 // Need to clear the lock flag upon returning from an interrupt.
899 this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
900
901 this->thread[tid]->kernelStats->hwrei();
902
903 // FIXME: XXX check for interrupts? XXX
904#endif
905 return NoFault;
906}
907
908template <class Impl>
909bool
910FullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid)
911{
912#if THE_ISA == ALPHA_ISA
913 if (this->thread[tid]->kernelStats)
914 this->thread[tid]->kernelStats->callpal(palFunc,
915 this->threadContexts[tid]);
916
917 switch (palFunc) {
918 case PAL::halt:
919 halt();
920 if (--System::numSystemsRunning == 0)
921 exitSimLoop("all cpus halted");
922 break;
923
924 case PAL::bpt:
925 case PAL::bugchk:
926 if (this->system->breakpoint())
927 return false;
928 break;
929 }
930#endif
931 return true;
932}
933
934template <class Impl>
935Fault
936FullO3CPU<Impl>::getInterrupts()
937{
938 // Check if there are any outstanding interrupts
939 return this->interrupts[0]->getInterrupt(this->threadContexts[0]);
940}
941
942template <class Impl>
943void
944FullO3CPU<Impl>::processInterrupts(const Fault &interrupt)
945{
946 // Check for interrupts here. For now can copy the code that
947 // exists within isa_fullsys_traits.hh. Also assume that thread 0
948 // is the one that handles the interrupts.
949 // @todo: Possibly consolidate the interrupt checking code.
950 // @todo: Allow other threads to handle interrupts.
951
952 assert(interrupt != NoFault);
953 this->interrupts[0]->updateIntrInfo(this->threadContexts[0]);
954
955 DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
956 this->trap(interrupt, 0, nullptr);
957}
958
959template <class Impl>
960void
961FullO3CPU<Impl>::trap(const Fault &fault, ThreadID tid,
962 const StaticInstPtr &inst)
963{
964 // Pass the thread's TC into the invoke method.
965 fault->invoke(this->threadContexts[tid], inst);
966}
967
968template <class Impl>
969void
970FullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid)
971{
972 DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid);
973
974 DPRINTF(Activity,"Activity: syscall() called.\n");
975
976 // Temporarily increase this by one to account for the syscall
977 // instruction.
978 ++(this->thread[tid]->funcExeInst);
979
980 // Execute the actual syscall.
981 this->thread[tid]->syscall(callnum);
982
983 // Decrease funcExeInst by one as the normal commit will handle
984 // incrementing it.
985 --(this->thread[tid]->funcExeInst);
986}
987
988template <class Impl>
989void
990FullO3CPU<Impl>::serializeThread(CheckpointOut &cp, ThreadID tid) const
991{
992 thread[tid]->serialize(cp);
993}
994
995template <class Impl>
996void
997FullO3CPU<Impl>::unserializeThread(CheckpointIn &cp, ThreadID tid)
998{
999 thread[tid]->unserialize(cp);
1000}
1001
1002template <class Impl>
1003DrainState
1004FullO3CPU<Impl>::drain()
1005{
1006 // If the CPU isn't doing anything, then return immediately.
1007 if (switchedOut())
1008 return DrainState::Drained;
1009
1010 DPRINTF(Drain, "Draining...\n");
1011
1012 // We only need to signal a drain to the commit stage as this
1013 // initiates squashing controls the draining. Once the commit
1014 // stage commits an instruction where it is safe to stop, it'll
1015 // squash the rest of the instructions in the pipeline and force
1016 // the fetch stage to stall. The pipeline will be drained once all
1017 // in-flight instructions have retired.
1018 commit.drain();
1019
1020 // Wake the CPU and record activity so everything can drain out if
1021 // the CPU was not able to immediately drain.
1022 if (!isDrained()) {
1023 wakeCPU();
1024 activityRec.activity();
1025
1026 DPRINTF(Drain, "CPU not drained\n");
1027
1028 return DrainState::Draining;
1029 } else {
1030 DPRINTF(Drain, "CPU is already drained\n");
1031 if (tickEvent.scheduled())
1032 deschedule(tickEvent);
1033
1034 // Flush out any old data from the time buffers. In
1035 // particular, there might be some data in flight from the
1036 // fetch stage that isn't visible in any of the CPU buffers we
1037 // test in isDrained().
1038 for (int i = 0; i < timeBuffer.getSize(); ++i) {
1039 timeBuffer.advance();
1040 fetchQueue.advance();
1041 decodeQueue.advance();
1042 renameQueue.advance();
1043 iewQueue.advance();
1044 }
1045
1046 drainSanityCheck();
1047 return DrainState::Drained;
1048 }
1049}
1050
1051template <class Impl>
1052bool
1053FullO3CPU<Impl>::tryDrain()
1054{
1055 if (drainState() != DrainState::Draining || !isDrained())
1056 return false;
1057
1058 if (tickEvent.scheduled())
1059 deschedule(tickEvent);
1060
1061 DPRINTF(Drain, "CPU done draining, processing drain event\n");
1062 signalDrainDone();
1063
1064 return true;
1065}
1066
1067template <class Impl>
1068void
1069FullO3CPU<Impl>::drainSanityCheck() const
1070{
1071 assert(isDrained());
1072 fetch.drainSanityCheck();
1073 decode.drainSanityCheck();
1074 rename.drainSanityCheck();
1075 iew.drainSanityCheck();
1076 commit.drainSanityCheck();
1077}
1078
1079template <class Impl>
1080bool
1081FullO3CPU<Impl>::isDrained() const
1082{
1083 bool drained(true);
1084
1085 if (!instList.empty() || !removeList.empty()) {
1086 DPRINTF(Drain, "Main CPU structures not drained.\n");
1087 drained = false;
1088 }
1089
1090 if (!fetch.isDrained()) {
1091 DPRINTF(Drain, "Fetch not drained.\n");
1092 drained = false;
1093 }
1094
1095 if (!decode.isDrained()) {
1096 DPRINTF(Drain, "Decode not drained.\n");
1097 drained = false;
1098 }
1099
1100 if (!rename.isDrained()) {
1101 DPRINTF(Drain, "Rename not drained.\n");
1102 drained = false;
1103 }
1104
1105 if (!iew.isDrained()) {
1106 DPRINTF(Drain, "IEW not drained.\n");
1107 drained = false;
1108 }
1109
1110 if (!commit.isDrained()) {
1111 DPRINTF(Drain, "Commit not drained.\n");
1112 drained = false;
1113 }
1114
1115 return drained;
1116}
1117
1118template <class Impl>
1119void
1120FullO3CPU<Impl>::commitDrained(ThreadID tid)
1121{
1122 fetch.drainStall(tid);
1123}
1124
1125template <class Impl>
1126void
1127FullO3CPU<Impl>::drainResume()
1128{
1129 if (switchedOut())
1130 return;
1131
1132 DPRINTF(Drain, "Resuming...\n");
1133 verifyMemoryMode();
1134
1135 fetch.drainResume();
1136 commit.drainResume();
1137
1138 _status = Idle;
1139 for (ThreadID i = 0; i < thread.size(); i++) {
1140 if (thread[i]->status() == ThreadContext::Active) {
1141 DPRINTF(Drain, "Activating thread: %i\n", i);
1142 activateThread(i);
1143 _status = Running;
1144 }
1145 }
1146
1147 assert(!tickEvent.scheduled());
1148 if (_status == Running)
1149 schedule(tickEvent, nextCycle());
1150}
1151
1152template <class Impl>
1153void
1154FullO3CPU<Impl>::switchOut()
1155{
1156 DPRINTF(O3CPU, "Switching out\n");
1157 BaseCPU::switchOut();
1158
1159 activityRec.reset();
1160
1161 _status = SwitchedOut;
1162
1163 if (checker)
1164 checker->switchOut();
1165}
1166
1167template <class Impl>
1168void
1169FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
1170{
1171 BaseCPU::takeOverFrom(oldCPU);
1172
1173 fetch.takeOverFrom();
1174 decode.takeOverFrom();
1175 rename.takeOverFrom();
1176 iew.takeOverFrom();
1177 commit.takeOverFrom();
1178
1179 assert(!tickEvent.scheduled());
1180
1181 FullO3CPU<Impl> *oldO3CPU = dynamic_cast<FullO3CPU<Impl>*>(oldCPU);
1182 if (oldO3CPU)
1183 globalSeqNum = oldO3CPU->globalSeqNum;
1184
1185 lastRunningCycle = curCycle();
1186 _status = Idle;
1187}
1188
1189template <class Impl>
1190void
1191FullO3CPU<Impl>::verifyMemoryMode() const
1192{
1193 if (!system->isTimingMode()) {
1194 fatal("The O3 CPU requires the memory system to be in "
1195 "'timing' mode.\n");
1196 }
1197}
1198
1199template <class Impl>
1200TheISA::MiscReg
1201FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
1202{
1203 return this->isa[tid]->readMiscRegNoEffect(misc_reg);
1204}
1205
1206template <class Impl>
1207TheISA::MiscReg
1208FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
1209{
1210 miscRegfileReads++;
1211 return this->isa[tid]->readMiscReg(misc_reg, tcBase(tid));
1212}
1213
1214template <class Impl>
1215void
1216FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
1217 const TheISA::MiscReg &val, ThreadID tid)
1218{
1219 this->isa[tid]->setMiscRegNoEffect(misc_reg, val);
1220}
1221
1222template <class Impl>
1223void
1224FullO3CPU<Impl>::setMiscReg(int misc_reg,
1225 const TheISA::MiscReg &val, ThreadID tid)
1226{
1227 miscRegfileWrites++;
1228 this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid));
1229}
1230
1231template <class Impl>
1232uint64_t
1233FullO3CPU<Impl>::readIntReg(int reg_idx)
1234{
1235 intRegfileReads++;
1236 return regFile.readIntReg(reg_idx);
1237}
1238
1239template <class Impl>
1240FloatReg
1241FullO3CPU<Impl>::readFloatReg(int reg_idx)
1242{
1243 fpRegfileReads++;
1244 return regFile.readFloatReg(reg_idx);
1245}
1246
1247template <class Impl>
1248FloatRegBits
1249FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
1250{
1251 fpRegfileReads++;
1252 return regFile.readFloatRegBits(reg_idx);
1253}
1254
1255template <class Impl>
1256CCReg
1257FullO3CPU<Impl>::readCCReg(int reg_idx)
1258{
1259 ccRegfileReads++;
1260 return regFile.readCCReg(reg_idx);
1261}
1262
1263template <class Impl>
1264void
1265FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
1266{
1267 intRegfileWrites++;
1268 regFile.setIntReg(reg_idx, val);
1269}
1270
1271template <class Impl>
1272void
1273FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
1274{
1275 fpRegfileWrites++;
1276 regFile.setFloatReg(reg_idx, val);
1277}
1278
1279template <class Impl>
1280void
1281FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
1282{
1283 fpRegfileWrites++;
1284 regFile.setFloatRegBits(reg_idx, val);
1285}
1286
1287template <class Impl>
1288void
1289FullO3CPU<Impl>::setCCReg(int reg_idx, CCReg val)
1290{
1291 ccRegfileWrites++;
1292 regFile.setCCReg(reg_idx, val);
1293}
1294
1295template <class Impl>
1296uint64_t
1297FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1298{
1299 intRegfileReads++;
1300 PhysRegIndex phys_reg = commitRenameMap[tid].lookupInt(reg_idx);
1301
1302 return regFile.readIntReg(phys_reg);
1303}
1304
1305template <class Impl>
1306float
1307FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
1308{
1309 fpRegfileReads++;
1310 PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1311
1312 return regFile.readFloatReg(phys_reg);
1313}
1314
1315template <class Impl>
1316uint64_t
1317FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid)
1318{
1319 fpRegfileReads++;
1320 PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1321
1322 return regFile.readFloatRegBits(phys_reg);
1323}
1324
1325template <class Impl>
1326CCReg
1327FullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid)
1328{
1329 ccRegfileReads++;
1330 PhysRegIndex phys_reg = commitRenameMap[tid].lookupCC(reg_idx);
1331
1332 return regFile.readCCReg(phys_reg);
1333}
1334
1335template <class Impl>
1336void
1337FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
1338{
1339 intRegfileWrites++;
1340 PhysRegIndex phys_reg = commitRenameMap[tid].lookupInt(reg_idx);
1341
1342 regFile.setIntReg(phys_reg, val);
1343}
1344
1345template <class Impl>
1346void
1347FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid)
1348{
1349 fpRegfileWrites++;
1350 PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1351
1352 regFile.setFloatReg(phys_reg, val);
1353}
1354
1355template <class Impl>
1356void
1357FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid)
1358{
1359 fpRegfileWrites++;
1360 PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1361
1362 regFile.setFloatRegBits(phys_reg, val);
1363}
1364
1365template <class Impl>
1366void
1367FullO3CPU<Impl>::setArchCCReg(int reg_idx, CCReg val, ThreadID tid)
1368{
1369 ccRegfileWrites++;
1370 PhysRegIndex phys_reg = commitRenameMap[tid].lookupCC(reg_idx);
1371
1372 regFile.setCCReg(phys_reg, val);
1373}
1374
1375template <class Impl>
1376TheISA::PCState
1377FullO3CPU<Impl>::pcState(ThreadID tid)
1378{
1379 return commit.pcState(tid);
1380}
1381
1382template <class Impl>
1383void
1384FullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid)
1385{
1386 commit.pcState(val, tid);
1387}
1388
1389template <class Impl>
1390Addr
1391FullO3CPU<Impl>::instAddr(ThreadID tid)
1392{
1393 return commit.instAddr(tid);
1394}
1395
1396template <class Impl>
1397Addr
1398FullO3CPU<Impl>::nextInstAddr(ThreadID tid)
1399{
1400 return commit.nextInstAddr(tid);
1401}
1402
1403template <class Impl>
1404MicroPC
1405FullO3CPU<Impl>::microPC(ThreadID tid)
1406{
1407 return commit.microPC(tid);
1408}
1409
1410template <class Impl>
1411void
1412FullO3CPU<Impl>::squashFromTC(ThreadID tid)
1413{
1414 this->thread[tid]->noSquashFromTC = true;
1415 this->commit.generateTCEvent(tid);
1416}
1417
1418template <class Impl>
1419typename FullO3CPU<Impl>::ListIt
1420FullO3CPU<Impl>::addInst(DynInstPtr &inst)
1421{
1422 instList.push_back(inst);
1423
1424 return --(instList.end());
1425}
1426
1427template <class Impl>
1428void
1429FullO3CPU<Impl>::instDone(ThreadID tid, DynInstPtr &inst)
1430{
1431 // Keep an instruction count.
1432 if (!inst->isMicroop() || inst->isLastMicroop()) {
1433 thread[tid]->numInst++;
1434 thread[tid]->numInsts++;
1435 committedInsts[tid]++;
1436 system->totalNumInsts++;
1437
1438 // Check for instruction-count-based events.
1439 comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1440 system->instEventQueue.serviceEvents(system->totalNumInsts);
1441 }
1442 thread[tid]->numOp++;
1443 thread[tid]->numOps++;
1444 committedOps[tid]++;
1445
1446 probeInstCommit(inst->staticInst);
1447}
1448
1449template <class Impl>
1450void
1451FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
1452{
1453 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s "
1454 "[sn:%lli]\n",
1455 inst->threadNumber, inst->pcState(), inst->seqNum);
1456
1457 removeInstsThisCycle = true;
1458
1459 // Remove the front instruction.
1460 removeList.push(inst->getInstListIt());
1461}
1462
1463template <class Impl>
1464void
1465FullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid)
1466{
1467 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1468 " list.\n", tid);
1469
1470 ListIt end_it;
1471
1472 bool rob_empty = false;
1473
1474 if (instList.empty()) {
1475 return;
1476 } else if (rob.isEmpty(tid)) {
1477 DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1478 end_it = instList.begin();
1479 rob_empty = true;
1480 } else {
1481 end_it = (rob.readTailInst(tid))->getInstListIt();
1482 DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1483 }
1484
1485 removeInstsThisCycle = true;
1486
1487 ListIt inst_it = instList.end();
1488
1489 inst_it--;
1490
1491 // Walk through the instruction list, removing any instructions
1492 // that were inserted after the given instruction iterator, end_it.
1493 while (inst_it != end_it) {
1494 assert(!instList.empty());
1495
1496 squashInstIt(inst_it, tid);
1497
1498 inst_it--;
1499 }
1500
1501 // If the ROB was empty, then we actually need to remove the first
1502 // instruction as well.
1503 if (rob_empty) {
1504 squashInstIt(inst_it, tid);
1505 }
1506}
1507
1508template <class Impl>
1509void
1510FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1511{
1512 assert(!instList.empty());
1513
1514 removeInstsThisCycle = true;
1515
1516 ListIt inst_iter = instList.end();
1517
1518 inst_iter--;
1519
1520 DPRINTF(O3CPU, "Deleting instructions from instruction "
1521 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1522 tid, seq_num, (*inst_iter)->seqNum);
1523
1524 while ((*inst_iter)->seqNum > seq_num) {
1525
1526 bool break_loop = (inst_iter == instList.begin());
1527
1528 squashInstIt(inst_iter, tid);
1529
1530 inst_iter--;
1531
1532 if (break_loop)
1533 break;
1534 }
1535}
1536
1537template <class Impl>
1538inline void
1539FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid)
1540{
1541 if ((*instIt)->threadNumber == tid) {
1542 DPRINTF(O3CPU, "Squashing instruction, "
1543 "[tid:%i] [sn:%lli] PC %s\n",
1544 (*instIt)->threadNumber,
1545 (*instIt)->seqNum,
1546 (*instIt)->pcState());
1547
1548 // Mark it as squashed.
1549 (*instIt)->setSquashed();
1550
1551 // @todo: Formulate a consistent method for deleting
1552 // instructions from the instruction list
1553 // Remove the instruction from the list.
1554 removeList.push(instIt);
1555 }
1556}
1557
1558template <class Impl>
1559void
1560FullO3CPU<Impl>::cleanUpRemovedInsts()
1561{
1562 while (!removeList.empty()) {
1563 DPRINTF(O3CPU, "Removing instruction, "
1564 "[tid:%i] [sn:%lli] PC %s\n",
1565 (*removeList.front())->threadNumber,
1566 (*removeList.front())->seqNum,
1567 (*removeList.front())->pcState());
1568
1569 instList.erase(removeList.front());
1570
1571 removeList.pop();
1572 }
1573
1574 removeInstsThisCycle = false;
1575}
1576/*
1577template <class Impl>
1578void
1579FullO3CPU<Impl>::removeAllInsts()
1580{
1581 instList.clear();
1582}
1583*/
1584template <class Impl>
1585void
1586FullO3CPU<Impl>::dumpInsts()
1587{
1588 int num = 0;
1589
1590 ListIt inst_list_it = instList.begin();
1591
1592 cprintf("Dumping Instruction List\n");
1593
1594 while (inst_list_it != instList.end()) {
1595 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1596 "Squashed:%i\n\n",
1597 num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber,
1598 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1599 (*inst_list_it)->isSquashed());
1600 inst_list_it++;
1601 ++num;
1602 }
1603}
1604/*
1605template <class Impl>
1606void
1607FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
1608{
1609 iew.wakeDependents(inst);
1610}
1611*/
1612template <class Impl>
1613void
1614FullO3CPU<Impl>::wakeCPU()
1615{
1616 if (activityRec.active() || tickEvent.scheduled()) {
1617 DPRINTF(Activity, "CPU already running.\n");
1618 return;
1619 }
1620
1621 DPRINTF(Activity, "Waking up CPU\n");
1622
1623 Cycles cycles(curCycle() - lastRunningCycle);
1624 // @todo: This is an oddity that is only here to match the stats
1625 if (cycles > 1) {
1626 --cycles;
1627 idleCycles += cycles;
1628 numCycles += cycles;
1629 ppCycles->notify(cycles);
1630 }
1631
1632 schedule(tickEvent, clockEdge());
1633}
1634
1635template <class Impl>
1636void
1637FullO3CPU<Impl>::wakeup(ThreadID tid)
1638{
1639 if (this->thread[tid]->status() != ThreadContext::Suspended)
1640 return;
1641
1642 this->wakeCPU();
1643
1644 DPRINTF(Quiesce, "Suspended Processor woken\n");
1645 this->threadContexts[tid]->activate();
1646}
1647
1648template <class Impl>
1649ThreadID
1650FullO3CPU<Impl>::getFreeTid()
1651{
1652 for (ThreadID tid = 0; tid < numThreads; tid++) {
1653 if (!tids[tid]) {
1654 tids[tid] = true;
1655 return tid;
1656 }
1657 }
1658
1659 return InvalidThreadID;
1660}
1661
1662template <class Impl>
1663void
1664FullO3CPU<Impl>::updateThreadPriority()
1665{
1666 if (activeThreads.size() > 1) {
1667 //DEFAULT TO ROUND ROBIN SCHEME
1668 //e.g. Move highest priority to end of thread list
1669 list<ThreadID>::iterator list_begin = activeThreads.begin();
1670
1671 unsigned high_thread = *list_begin;
1672
1673 activeThreads.erase(list_begin);
1674
1675 activeThreads.push_back(high_thread);
1676 }
1677}
1678
1679// Forward declaration of FullO3CPU.
1680template class FullO3CPU<O3CPUImpl>;
|