cpu.cc (8232:b28d06a175be) | cpu.cc (8460:3893d9d2c6c2) |
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1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * Copyright (c) 2011 Regents of the University of California 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 32 unchanged lines hidden (view full) --- 41#include "cpu/simple_thread.hh" 42#include "cpu/thread_context.hh" 43#include "debug/Activity.hh" 44#include "debug/O3CPU.hh" 45#include "debug/Quiesce.hh" 46#include "enums/MemoryMode.hh" 47#include "sim/core.hh" 48#include "sim/stat_control.hh" | 1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * Copyright (c) 2011 Regents of the University of California 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 32 unchanged lines hidden (view full) --- 41#include "cpu/simple_thread.hh" 42#include "cpu/thread_context.hh" 43#include "debug/Activity.hh" 44#include "debug/O3CPU.hh" 45#include "debug/Quiesce.hh" 46#include "enums/MemoryMode.hh" 47#include "sim/core.hh" 48#include "sim/stat_control.hh" |
49#include "sim/system.hh" |
|
49 50#if FULL_SYSTEM 51#include "cpu/quiesce_event.hh" | 50 51#if FULL_SYSTEM 52#include "cpu/quiesce_event.hh" |
52#include "sim/system.hh" | |
53#else 54#include "sim/process.hh" 55#endif 56 57#if USE_CHECKER 58#include "cpu/checker/cpu.hh" 59#endif 60 --- 138 unchanged lines hidden (view full) --- 199 decodeQueue(params->backComSize, params->forwardComSize), 200 renameQueue(params->backComSize, params->forwardComSize), 201 iewQueue(params->backComSize, params->forwardComSize), 202 activityRec(name(), NumStages, 203 params->backComSize + params->forwardComSize, 204 params->activity), 205 206 globalSeqNum(1), | 53#else 54#include "sim/process.hh" 55#endif 56 57#if USE_CHECKER 58#include "cpu/checker/cpu.hh" 59#endif 60 --- 138 unchanged lines hidden (view full) --- 199 decodeQueue(params->backComSize, params->forwardComSize), 200 renameQueue(params->backComSize, params->forwardComSize), 201 iewQueue(params->backComSize, params->forwardComSize), 202 activityRec(name(), NumStages, 203 params->backComSize + params->forwardComSize, 204 params->activity), 205 206 globalSeqNum(1), |
207#if FULL_SYSTEM | |
208 system(params->system), | 207 system(params->system), |
209#endif // FULL_SYSTEM | |
210 drainCount(0), 211 deferRegistration(params->defer_registration) 212{ 213 if (!deferRegistration) { 214 _status = Running; 215 } else { 216 _status = Idle; 217 } --- 882 unchanged lines hidden (view full) --- 1100 iew.resume(); 1101 commit.resume(); 1102 1103 changeState(SimObject::Running); 1104 1105 if (_status == SwitchedOut || _status == Idle) 1106 return; 1107 | 208 drainCount(0), 209 deferRegistration(params->defer_registration) 210{ 211 if (!deferRegistration) { 212 _status = Running; 213 } else { 214 _status = Idle; 215 } --- 882 unchanged lines hidden (view full) --- 1098 iew.resume(); 1099 commit.resume(); 1100 1101 changeState(SimObject::Running); 1102 1103 if (_status == SwitchedOut || _status == Idle) 1104 return; 1105 |
1108#if FULL_SYSTEM | |
1109 assert(system->getMemoryMode() == Enums::timing); | 1106 assert(system->getMemoryMode() == Enums::timing); |
1110#endif | |
1111 1112 if (!tickEvent.scheduled()) 1113 schedule(tickEvent, nextCycle()); 1114 _status = Running; 1115} 1116 1117template <class Impl> 1118void --- 562 unchanged lines hidden --- | 1107 1108 if (!tickEvent.scheduled()) 1109 schedule(tickEvent, nextCycle()); 1110 _status = Running; 1111} 1112 1113template <class Impl> 1114void --- 562 unchanged lines hidden --- |