cpu.cc (10934:5af8f40d8f2c) | cpu.cc (10935:acd48ddd725f) |
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1/* 2 * Copyright (c) 2011-2012, 2014 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 156 unchanged lines hidden (view full) --- 165 fetch(this, params), 166 decode(this, params), 167 rename(this, params), 168 iew(this, params), 169 commit(this, params), 170 171 regFile(params->numPhysIntRegs, 172 params->numPhysFloatRegs, | 1/* 2 * Copyright (c) 2011-2012, 2014 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 156 unchanged lines hidden (view full) --- 165 fetch(this, params), 166 decode(this, params), 167 rename(this, params), 168 iew(this, params), 169 commit(this, params), 170 171 regFile(params->numPhysIntRegs, 172 params->numPhysFloatRegs, |
173 params->numPhysCCRegs, 174 params->numPhysVectorRegs), | 173 params->numPhysCCRegs), |
175 176 freeList(name() + ".freelist", ®File), 177 178 rob(this, params), 179 180 scoreboard(name() + ".scoreboard", 181 regFile.totalNumPhysRegs(), TheISA::NumMiscRegs, 182 TheISA::ZeroReg, TheISA::ZeroReg), --- 82 unchanged lines hidden (view full) --- 265 "or edit your workload size."); 266 } 267 } 268 269 //Make Sure That this a Valid Architeture 270 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 271 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 272 assert(params->numPhysCCRegs >= numThreads * TheISA::NumCCRegs); | 174 175 freeList(name() + ".freelist", ®File), 176 177 rob(this, params), 178 179 scoreboard(name() + ".scoreboard", 180 regFile.totalNumPhysRegs(), TheISA::NumMiscRegs, 181 TheISA::ZeroReg, TheISA::ZeroReg), --- 82 unchanged lines hidden (view full) --- 264 "or edit your workload size."); 265 } 266 } 267 268 //Make Sure That this a Valid Architeture 269 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 270 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 271 assert(params->numPhysCCRegs >= numThreads * TheISA::NumCCRegs); |
273 assert(params->numPhysVectorRegs >= numThreads * TheISA::NumVectorRegs); | |
274 275 rename.setScoreboard(&scoreboard); 276 iew.setScoreboard(&scoreboard); 277 278 // Setup the rename map for whichever stages need it. 279 for (ThreadID tid = 0; tid < numThreads; tid++) { 280 isa[tid] = params->isa[tid]; 281 --- 28 unchanged lines hidden (view full) --- 310 commitRenameMap[tid].setFloatEntry(ridx, phys_reg); 311 } 312 313 for (RegIndex ridx = 0; ridx < TheISA::NumCCRegs; ++ridx) { 314 PhysRegIndex phys_reg = freeList.getCCReg(); 315 renameMap[tid].setCCEntry(ridx, phys_reg); 316 commitRenameMap[tid].setCCEntry(ridx, phys_reg); 317 } | 272 273 rename.setScoreboard(&scoreboard); 274 iew.setScoreboard(&scoreboard); 275 276 // Setup the rename map for whichever stages need it. 277 for (ThreadID tid = 0; tid < numThreads; tid++) { 278 isa[tid] = params->isa[tid]; 279 --- 28 unchanged lines hidden (view full) --- 308 commitRenameMap[tid].setFloatEntry(ridx, phys_reg); 309 } 310 311 for (RegIndex ridx = 0; ridx < TheISA::NumCCRegs; ++ridx) { 312 PhysRegIndex phys_reg = freeList.getCCReg(); 313 renameMap[tid].setCCEntry(ridx, phys_reg); 314 commitRenameMap[tid].setCCEntry(ridx, phys_reg); 315 } |
318 319 for (RegIndex ridx = 0; ridx < TheISA::NumVectorRegs; ++ridx) { 320 PhysRegIndex phys_reg = freeList.getVectorReg(); 321 renameMap[tid].setVectorEntry(ridx, phys_reg); 322 commitRenameMap[tid].setVectorEntry(ridx, phys_reg); 323 } | |
324 } 325 326 rename.setRenameMap(renameMap); 327 commit.setRenameMap(commitRenameMap); 328 rename.setFreeList(&freeList); 329 330 // Setup the ROB for whichever stages need it. 331 commit.setROB(&rob); --- 192 unchanged lines hidden (view full) --- 524 .desc("number of cc regfile reads") 525 .prereq(ccRegfileReads); 526 527 ccRegfileWrites 528 .name(name() + ".cc_regfile_writes") 529 .desc("number of cc regfile writes") 530 .prereq(ccRegfileWrites); 531 | 316 } 317 318 rename.setRenameMap(renameMap); 319 commit.setRenameMap(commitRenameMap); 320 rename.setFreeList(&freeList); 321 322 // Setup the ROB for whichever stages need it. 323 commit.setROB(&rob); --- 192 unchanged lines hidden (view full) --- 516 .desc("number of cc regfile reads") 517 .prereq(ccRegfileReads); 518 519 ccRegfileWrites 520 .name(name() + ".cc_regfile_writes") 521 .desc("number of cc regfile writes") 522 .prereq(ccRegfileWrites); 523 |
532 vectorRegfileReads 533 .name(name() + ".vector_regfile_reads") 534 .desc("number of vector regfile reads") 535 .prereq(vectorRegfileReads); 536 537 vectorRegfileWrites 538 .name(name() + ".vector_regfile_writes") 539 .desc("number of vector regfile writes") 540 .prereq(vectorRegfileWrites); 541 | |
542 miscRegfileReads 543 .name(name() + ".misc_regfile_reads") 544 .desc("number of misc regfile reads") 545 .prereq(miscRegfileReads); 546 547 miscRegfileWrites 548 .name(name() + ".misc_regfile_writes") 549 .desc("number of misc regfile writes") --- 270 unchanged lines hidden (view full) --- 820 for (int creg = TheISA::NumIntRegs + TheISA::NumFloatRegs; 821 creg < max_reg; creg++) { 822 PhysRegIndex phys_reg = freeList.getCCReg(); 823 824 renameMap[tid].setEntry(creg,phys_reg); 825 scoreboard.setReg(phys_reg); 826 } 827 | 524 miscRegfileReads 525 .name(name() + ".misc_regfile_reads") 526 .desc("number of misc regfile reads") 527 .prereq(miscRegfileReads); 528 529 miscRegfileWrites 530 .name(name() + ".misc_regfile_writes") 531 .desc("number of misc regfile writes") --- 270 unchanged lines hidden (view full) --- 802 for (int creg = TheISA::NumIntRegs + TheISA::NumFloatRegs; 803 creg < max_reg; creg++) { 804 PhysRegIndex phys_reg = freeList.getCCReg(); 805 806 renameMap[tid].setEntry(creg,phys_reg); 807 scoreboard.setReg(phys_reg); 808 } 809 |
828 //Bind vector Regs to Rename Map 829 max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs + TheISA::NumCCRegs + 830 TheISA::NumVectorRegs; 831 for (int vreg = TheISA::NumIntRegs + TheISA::NumFloatRegs + 832 TheISA::NumCCRegs; 833 vreg < max_reg; vreg++) { 834 PhysRegIndex phys_reg = freeList.getVectorReg(); 835 836 renameMap[tid].setEntry(vreg, phys_reg); 837 scoreboard.setReg(phys_reg); 838 } 839 | |
840 //Copy Thread Data Into RegFile 841 //this->copyFromTC(tid); 842 843 //Set PC/NPC/NNPC 844 pcState(src_tc->pcState(), tid); 845 846 src_tc->setStatus(ThreadContext::Active); 847 --- 37 unchanged lines hidden (view full) --- 885 // Unbind condition-code Regs from Rename Map 886 max_reg = TheISA::CC_Reg_Base + TheISA::NumCCRegs; 887 for (int creg = TheISA::CC_Reg_Base; creg < max_reg; creg++) { 888 PhysRegIndex phys_reg = renameMap[tid].lookup(creg); 889 scoreboard.unsetReg(phys_reg); 890 freeList.addReg(phys_reg); 891 } 892 | 810 //Copy Thread Data Into RegFile 811 //this->copyFromTC(tid); 812 813 //Set PC/NPC/NNPC 814 pcState(src_tc->pcState(), tid); 815 816 src_tc->setStatus(ThreadContext::Active); 817 --- 37 unchanged lines hidden (view full) --- 855 // Unbind condition-code Regs from Rename Map 856 max_reg = TheISA::CC_Reg_Base + TheISA::NumCCRegs; 857 for (int creg = TheISA::CC_Reg_Base; creg < max_reg; creg++) { 858 PhysRegIndex phys_reg = renameMap[tid].lookup(creg); 859 scoreboard.unsetReg(phys_reg); 860 freeList.addReg(phys_reg); 861 } 862 |
893 // Unbind condition-code Regs from Rename Map 894 max_reg = TheISA::Vector_Reg_Base + TheISA::NumVectorRegs; 895 for (int vreg = TheISA::Vector_Reg_Base; vreg < max_reg; vreg++) { 896 PhysRegIndex phys_reg = renameMap[tid].lookup(vreg); 897 scoreboard.unsetReg(phys_reg); 898 freeList.addReg(phys_reg); 899 } 900 | |
901 // Squash Throughout Pipeline 902 DynInstPtr inst = commit.rob->readHeadInst(tid); 903 InstSeqNum squash_seq_num = inst->seqNum; 904 fetch.squash(0, squash_seq_num, inst, tid); 905 decode.squash(tid); 906 rename.squash(squash_seq_num, tid); 907 iew.squash(tid); 908 iew.ldstQueue.squash(squash_seq_num, tid); --- 383 unchanged lines hidden (view full) --- 1292CCReg 1293FullO3CPU<Impl>::readCCReg(int reg_idx) 1294{ 1295 ccRegfileReads++; 1296 return regFile.readCCReg(reg_idx); 1297} 1298 1299template <class Impl> | 863 // Squash Throughout Pipeline 864 DynInstPtr inst = commit.rob->readHeadInst(tid); 865 InstSeqNum squash_seq_num = inst->seqNum; 866 fetch.squash(0, squash_seq_num, inst, tid); 867 decode.squash(tid); 868 rename.squash(squash_seq_num, tid); 869 iew.squash(tid); 870 iew.ldstQueue.squash(squash_seq_num, tid); --- 383 unchanged lines hidden (view full) --- 1254CCReg 1255FullO3CPU<Impl>::readCCReg(int reg_idx) 1256{ 1257 ccRegfileReads++; 1258 return regFile.readCCReg(reg_idx); 1259} 1260 1261template <class Impl> |
1300const VectorReg & 1301FullO3CPU<Impl>::readVectorReg(int reg_idx) 1302{ 1303 vectorRegfileReads++; 1304 return regFile.readVectorReg(reg_idx); 1305} 1306 1307template <class Impl> | |
1308void 1309FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 1310{ 1311 intRegfileWrites++; 1312 regFile.setIntReg(reg_idx, val); 1313} 1314 1315template <class Impl> --- 16 unchanged lines hidden (view full) --- 1332void 1333FullO3CPU<Impl>::setCCReg(int reg_idx, CCReg val) 1334{ 1335 ccRegfileWrites++; 1336 regFile.setCCReg(reg_idx, val); 1337} 1338 1339template <class Impl> | 1262void 1263FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 1264{ 1265 intRegfileWrites++; 1266 regFile.setIntReg(reg_idx, val); 1267} 1268 1269template <class Impl> --- 16 unchanged lines hidden (view full) --- 1286void 1287FullO3CPU<Impl>::setCCReg(int reg_idx, CCReg val) 1288{ 1289 ccRegfileWrites++; 1290 regFile.setCCReg(reg_idx, val); 1291} 1292 1293template <class Impl> |
1340void 1341FullO3CPU<Impl>::setVectorReg(int reg_idx, const VectorReg &val) 1342{ 1343 vectorRegfileWrites++; 1344 regFile.setVectorReg(reg_idx, val); 1345} 1346 1347template <class Impl> | |
1348uint64_t 1349FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid) 1350{ 1351 intRegfileReads++; 1352 PhysRegIndex phys_reg = commitRenameMap[tid].lookupInt(reg_idx); 1353 1354 return regFile.readIntReg(phys_reg); 1355} --- 24 unchanged lines hidden (view full) --- 1380{ 1381 ccRegfileReads++; 1382 PhysRegIndex phys_reg = commitRenameMap[tid].lookupCC(reg_idx); 1383 1384 return regFile.readCCReg(phys_reg); 1385} 1386 1387template <class Impl> | 1294uint64_t 1295FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid) 1296{ 1297 intRegfileReads++; 1298 PhysRegIndex phys_reg = commitRenameMap[tid].lookupInt(reg_idx); 1299 1300 return regFile.readIntReg(phys_reg); 1301} --- 24 unchanged lines hidden (view full) --- 1326{ 1327 ccRegfileReads++; 1328 PhysRegIndex phys_reg = commitRenameMap[tid].lookupCC(reg_idx); 1329 1330 return regFile.readCCReg(phys_reg); 1331} 1332 1333template <class Impl> |
1388const VectorReg& 1389FullO3CPU<Impl>::readArchVectorReg(int reg_idx, ThreadID tid) 1390{ 1391 vectorRegfileReads++; 1392 PhysRegIndex phys_reg = commitRenameMap[tid].lookupVector(reg_idx); 1393 1394 return regFile.readVectorReg(phys_reg); 1395} 1396 1397template <class Impl> | |
1398void 1399FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid) 1400{ 1401 intRegfileWrites++; 1402 PhysRegIndex phys_reg = commitRenameMap[tid].lookupInt(reg_idx); 1403 1404 regFile.setIntReg(phys_reg, val); 1405} --- 24 unchanged lines hidden (view full) --- 1430{ 1431 ccRegfileWrites++; 1432 PhysRegIndex phys_reg = commitRenameMap[tid].lookupCC(reg_idx); 1433 1434 regFile.setCCReg(phys_reg, val); 1435} 1436 1437template <class Impl> | 1334void 1335FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid) 1336{ 1337 intRegfileWrites++; 1338 PhysRegIndex phys_reg = commitRenameMap[tid].lookupInt(reg_idx); 1339 1340 regFile.setIntReg(phys_reg, val); 1341} --- 24 unchanged lines hidden (view full) --- 1366{ 1367 ccRegfileWrites++; 1368 PhysRegIndex phys_reg = commitRenameMap[tid].lookupCC(reg_idx); 1369 1370 regFile.setCCReg(phys_reg, val); 1371} 1372 1373template <class Impl> |
1438void 1439FullO3CPU<Impl>::setArchVectorReg(int reg_idx, const VectorReg &val, 1440 ThreadID tid) 1441{ 1442 vectorRegfileWrites++; 1443 PhysRegIndex phys_reg = commitRenameMap[tid].lookupVector(reg_idx); 1444 regFile.setVectorReg(phys_reg, val); 1445} 1446 1447template <class Impl> | |
1448TheISA::PCState 1449FullO3CPU<Impl>::pcState(ThreadID tid) 1450{ 1451 return commit.pcState(tid); 1452} 1453 1454template <class Impl> 1455void --- 297 unchanged lines hidden --- | 1374TheISA::PCState 1375FullO3CPU<Impl>::pcState(ThreadID tid) 1376{ 1377 return commit.pcState(tid); 1378} 1379 1380template <class Impl> 1381void --- 297 unchanged lines hidden --- |