1/*
2 * Copyright (c) 2011-2012, 2014 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * Copyright (c) 2011 Regents of the University of California
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Kevin Lim
43 * Korey Sewell
44 * Rick Strong
45 */
46
47#include "cpu/o3/cpu.hh"
48
49#include "arch/kernel_stats.hh"
50#include "config/the_isa.hh"
51#include "cpu/activity.hh"
52#include "cpu/checker/cpu.hh"
53#include "cpu/checker/thread_context.hh"
54#include "cpu/o3/isa_specific.hh"
55#include "cpu/o3/thread_context.hh"
56#include "cpu/quiesce_event.hh"
57#include "cpu/simple_thread.hh"
58#include "cpu/thread_context.hh"
59#include "debug/Activity.hh"
60#include "debug/Drain.hh"
61#include "debug/O3CPU.hh"
62#include "debug/Quiesce.hh"
63#include "enums/MemoryMode.hh"
64#include "sim/core.hh"
65#include "sim/full_system.hh"
66#include "sim/process.hh"
67#include "sim/stat_control.hh"
68#include "sim/system.hh"
69
70#if THE_ISA == ALPHA_ISA
71#include "arch/alpha/osfpal.hh"
72#include "debug/Activity.hh"
73
74#endif
75
76struct BaseCPUParams;
77
78using namespace TheISA;
79using namespace std;
80
81BaseO3CPU::BaseO3CPU(BaseCPUParams *params)
82 : BaseCPU(params)
83{
84}
85
86void
87BaseO3CPU::regStats()
88{
89 BaseCPU::regStats();
90}
91
92template<class Impl>
93bool
94FullO3CPU<Impl>::IcachePort::recvTimingResp(PacketPtr pkt)
95{
96 DPRINTF(O3CPU, "Fetch unit received timing\n");
97 // We shouldn't ever get a cacheable block in Modified state
98 assert(pkt->req->isUncacheable() ||
99 !(pkt->cacheResponding() && !pkt->hasSharers()));
100 fetch->processCacheCompletion(pkt);
101
102 return true;
103}
104
105template<class Impl>
106void
107FullO3CPU<Impl>::IcachePort::recvReqRetry()
108{
109 fetch->recvReqRetry();
110}
111
112template <class Impl>
113bool
114FullO3CPU<Impl>::DcachePort::recvTimingResp(PacketPtr pkt)
115{
116 return lsq->recvTimingResp(pkt);
117}
118
119template <class Impl>
120void
121FullO3CPU<Impl>::DcachePort::recvTimingSnoopReq(PacketPtr pkt)
122{
123 for (ThreadID tid = 0; tid < cpu->numThreads; tid++) {
124 if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) {
125 cpu->wakeup(tid);
126 }
127 }
128 lsq->recvTimingSnoopReq(pkt);
129}
130
131template <class Impl>
132void
133FullO3CPU<Impl>::DcachePort::recvReqRetry()
134{
135 lsq->recvReqRetry();
136}
137
138template <class Impl>
139FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
140 : Event(CPU_Tick_Pri), cpu(c)
141{
142}
143
144template <class Impl>
145void
146FullO3CPU<Impl>::TickEvent::process()
147{
148 cpu->tick();
149}
150
151template <class Impl>
152const char *
153FullO3CPU<Impl>::TickEvent::description() const
154{
155 return "FullO3CPU tick";
156}
157
158template <class Impl>
159FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
160 : BaseO3CPU(params),
161 itb(params->itb),
162 dtb(params->dtb),
163 tickEvent(this),
164#ifndef NDEBUG
165 instcount(0),
166#endif
167 removeInstsThisCycle(false),
168 fetch(this, params),
169 decode(this, params),
170 rename(this, params),
171 iew(this, params),
172 commit(this, params),
173
174 regFile(params->numPhysIntRegs,
175 params->numPhysFloatRegs,
176 params->numPhysCCRegs),
177
178 freeList(name() + ".freelist", ®File),
179
180 rob(this, params),
181
182 scoreboard(name() + ".scoreboard",
183 regFile.totalNumPhysRegs(), TheISA::NumMiscRegs,
184 TheISA::ZeroReg, TheISA::ZeroReg),
185
186 isa(numThreads, NULL),
187
188 icachePort(&fetch, this),
189 dcachePort(&iew.ldstQueue, this),
190
191 timeBuffer(params->backComSize, params->forwardComSize),
192 fetchQueue(params->backComSize, params->forwardComSize),
193 decodeQueue(params->backComSize, params->forwardComSize),
194 renameQueue(params->backComSize, params->forwardComSize),
195 iewQueue(params->backComSize, params->forwardComSize),
196 activityRec(name(), NumStages,
197 params->backComSize + params->forwardComSize,
198 params->activity),
199
200 globalSeqNum(1),
201 system(params->system),
202 lastRunningCycle(curCycle())
203{
204 if (!params->switched_out) {
205 _status = Running;
206 } else {
207 _status = SwitchedOut;
208 }
209
210 if (params->checker) {
211 BaseCPU *temp_checker = params->checker;
212 checker = dynamic_cast<Checker<Impl> *>(temp_checker);
213 checker->setIcachePort(&icachePort);
214 checker->setSystem(params->system);
215 } else {
216 checker = NULL;
217 }
218
219 if (!FullSystem) {
220 thread.resize(numThreads);
221 tids.resize(numThreads);
222 }
223
224 // The stages also need their CPU pointer setup. However this
225 // must be done at the upper level CPU because they have pointers
226 // to the upper level CPU, and not this FullO3CPU.
227
228 // Set up Pointers to the activeThreads list for each stage
229 fetch.setActiveThreads(&activeThreads);
230 decode.setActiveThreads(&activeThreads);
231 rename.setActiveThreads(&activeThreads);
232 iew.setActiveThreads(&activeThreads);
233 commit.setActiveThreads(&activeThreads);
234
235 // Give each of the stages the time buffer they will use.
236 fetch.setTimeBuffer(&timeBuffer);
237 decode.setTimeBuffer(&timeBuffer);
238 rename.setTimeBuffer(&timeBuffer);
239 iew.setTimeBuffer(&timeBuffer);
240 commit.setTimeBuffer(&timeBuffer);
241
242 // Also setup each of the stages' queues.
243 fetch.setFetchQueue(&fetchQueue);
244 decode.setFetchQueue(&fetchQueue);
245 commit.setFetchQueue(&fetchQueue);
246 decode.setDecodeQueue(&decodeQueue);
247 rename.setDecodeQueue(&decodeQueue);
248 rename.setRenameQueue(&renameQueue);
249 iew.setRenameQueue(&renameQueue);
250 iew.setIEWQueue(&iewQueue);
251 commit.setIEWQueue(&iewQueue);
252 commit.setRenameQueue(&renameQueue);
253
254 commit.setIEWStage(&iew);
255 rename.setIEWStage(&iew);
256 rename.setCommitStage(&commit);
257
258 ThreadID active_threads;
259 if (FullSystem) {
260 active_threads = 1;
261 } else {
262 active_threads = params->workload.size();
263
264 if (active_threads > Impl::MaxThreads) {
265 panic("Workload Size too large. Increase the 'MaxThreads' "
266 "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) "
267 "or edit your workload size.");
268 }
269 }
270
271 //Make Sure That this a Valid Architeture
272 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs);
273 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
274 assert(params->numPhysCCRegs >= numThreads * TheISA::NumCCRegs);
275
276 rename.setScoreboard(&scoreboard);
277 iew.setScoreboard(&scoreboard);
278
279 // Setup the rename map for whichever stages need it.
280 for (ThreadID tid = 0; tid < numThreads; tid++) {
281 isa[tid] = params->isa[tid];
282
283 // Only Alpha has an FP zero register, so for other ISAs we
284 // use an invalid FP register index to avoid special treatment
285 // of any valid FP reg.
286 RegIndex invalidFPReg = TheISA::NumFloatRegs + 1;
287 RegIndex fpZeroReg =
288 (THE_ISA == ALPHA_ISA) ? TheISA::ZeroReg : invalidFPReg;
289
290 commitRenameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg,
291 &freeList);
292
293 renameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg,
294 &freeList);
295 }
296
297 // Initialize rename map to assign physical registers to the
298 // architectural registers for active threads only.
299 for (ThreadID tid = 0; tid < active_threads; tid++) {
300 for (RegIndex ridx = 0; ridx < TheISA::NumIntRegs; ++ridx) {
301 // Note that we can't use the rename() method because we don't
302 // want special treatment for the zero register at this point
303 PhysRegIndex phys_reg = freeList.getIntReg();
304 renameMap[tid].setIntEntry(ridx, phys_reg);
305 commitRenameMap[tid].setIntEntry(ridx, phys_reg);
306 }
307
308 for (RegIndex ridx = 0; ridx < TheISA::NumFloatRegs; ++ridx) {
309 PhysRegIndex phys_reg = freeList.getFloatReg();
310 renameMap[tid].setFloatEntry(ridx, phys_reg);
311 commitRenameMap[tid].setFloatEntry(ridx, phys_reg);
312 }
313
314 for (RegIndex ridx = 0; ridx < TheISA::NumCCRegs; ++ridx) {
315 PhysRegIndex phys_reg = freeList.getCCReg();
316 renameMap[tid].setCCEntry(ridx, phys_reg);
317 commitRenameMap[tid].setCCEntry(ridx, phys_reg);
318 }
319 }
320
321 rename.setRenameMap(renameMap);
322 commit.setRenameMap(commitRenameMap);
323 rename.setFreeList(&freeList);
324
325 // Setup the ROB for whichever stages need it.
326 commit.setROB(&rob);
327
328 lastActivatedCycle = 0;
329#if 0
330 // Give renameMap & rename stage access to the freeList;
331 for (ThreadID tid = 0; tid < numThreads; tid++)
332 globalSeqNum[tid] = 1;
333#endif
334
335 DPRINTF(O3CPU, "Creating O3CPU object.\n");
336
337 // Setup any thread state.
338 this->thread.resize(this->numThreads);
339
340 for (ThreadID tid = 0; tid < this->numThreads; ++tid) {
341 if (FullSystem) {
342 // SMT is not supported in FS mode yet.
343 assert(this->numThreads == 1);
344 this->thread[tid] = new Thread(this, 0, NULL);
345 } else {
346 if (tid < params->workload.size()) {
347 DPRINTF(O3CPU, "Workload[%i] process is %#x",
348 tid, this->thread[tid]);
349 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
350 (typename Impl::O3CPU *)(this),
351 tid, params->workload[tid]);
352
353 //usedTids[tid] = true;
354 //threadMap[tid] = tid;
355 } else {
356 //Allocate Empty thread so M5 can use later
357 //when scheduling threads to CPU
358 Process* dummy_proc = NULL;
359
360 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
361 (typename Impl::O3CPU *)(this),
362 tid, dummy_proc);
363 //usedTids[tid] = false;
364 }
365 }
366
367 ThreadContext *tc;
368
369 // Setup the TC that will serve as the interface to the threads/CPU.
370 O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>;
371
372 tc = o3_tc;
373
374 // If we're using a checker, then the TC should be the
375 // CheckerThreadContext.
376 if (params->checker) {
377 tc = new CheckerThreadContext<O3ThreadContext<Impl> >(
378 o3_tc, this->checker);
379 }
380
381 o3_tc->cpu = (typename Impl::O3CPU *)(this);
382 assert(o3_tc->cpu);
383 o3_tc->thread = this->thread[tid];
384
385 // Setup quiesce event.
386 this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
387
388 // Give the thread the TC.
389 this->thread[tid]->tc = tc;
390
391 // Add the TC to the CPU's list of TC's.
392 this->threadContexts.push_back(tc);
393 }
394
395 // FullO3CPU always requires an interrupt controller.
396 if (!params->switched_out && interrupts.empty()) {
397 fatal("FullO3CPU %s has no interrupt controller.\n"
398 "Ensure createInterruptController() is called.\n", name());
399 }
400
401 for (ThreadID tid = 0; tid < this->numThreads; tid++)
402 this->thread[tid]->setFuncExeInst(0);
403}
404
405template <class Impl>
406FullO3CPU<Impl>::~FullO3CPU()
407{
408}
409
410template <class Impl>
411void
412FullO3CPU<Impl>::regProbePoints()
413{
414 BaseCPU::regProbePoints();
415
416 ppInstAccessComplete = new ProbePointArg<PacketPtr>(getProbeManager(), "InstAccessComplete");
417 ppDataAccessComplete = new ProbePointArg<std::pair<DynInstPtr, PacketPtr> >(getProbeManager(), "DataAccessComplete");
418
419 fetch.regProbePoints();
420 rename.regProbePoints();
421 iew.regProbePoints();
422 commit.regProbePoints();
423}
424
425template <class Impl>
426void
427FullO3CPU<Impl>::regStats()
428{
429 BaseO3CPU::regStats();
430
431 // Register any of the O3CPU's stats here.
432 timesIdled
433 .name(name() + ".timesIdled")
434 .desc("Number of times that the entire CPU went into an idle state and"
435 " unscheduled itself")
436 .prereq(timesIdled);
437
438 idleCycles
439 .name(name() + ".idleCycles")
440 .desc("Total number of cycles that the CPU has spent unscheduled due "
441 "to idling")
442 .prereq(idleCycles);
443
444 quiesceCycles
445 .name(name() + ".quiesceCycles")
446 .desc("Total number of cycles that CPU has spent quiesced or waiting "
447 "for an interrupt")
448 .prereq(quiesceCycles);
449
450 // Number of Instructions simulated
451 // --------------------------------
452 // Should probably be in Base CPU but need templated
453 // MaxThreads so put in here instead
454 committedInsts
455 .init(numThreads)
456 .name(name() + ".committedInsts")
457 .desc("Number of Instructions Simulated")
458 .flags(Stats::total);
459
460 committedOps
461 .init(numThreads)
462 .name(name() + ".committedOps")
463 .desc("Number of Ops (including micro ops) Simulated")
464 .flags(Stats::total);
465
466 cpi
467 .name(name() + ".cpi")
468 .desc("CPI: Cycles Per Instruction")
469 .precision(6);
470 cpi = numCycles / committedInsts;
471
472 totalCpi
473 .name(name() + ".cpi_total")
474 .desc("CPI: Total CPI of All Threads")
475 .precision(6);
476 totalCpi = numCycles / sum(committedInsts);
477
478 ipc
479 .name(name() + ".ipc")
480 .desc("IPC: Instructions Per Cycle")
481 .precision(6);
482 ipc = committedInsts / numCycles;
483
484 totalIpc
485 .name(name() + ".ipc_total")
486 .desc("IPC: Total IPC of All Threads")
487 .precision(6);
488 totalIpc = sum(committedInsts) / numCycles;
489
490 this->fetch.regStats();
491 this->decode.regStats();
492 this->rename.regStats();
493 this->iew.regStats();
494 this->commit.regStats();
495 this->rob.regStats();
496
497 intRegfileReads
498 .name(name() + ".int_regfile_reads")
499 .desc("number of integer regfile reads")
500 .prereq(intRegfileReads);
501
502 intRegfileWrites
503 .name(name() + ".int_regfile_writes")
504 .desc("number of integer regfile writes")
505 .prereq(intRegfileWrites);
506
507 fpRegfileReads
508 .name(name() + ".fp_regfile_reads")
509 .desc("number of floating regfile reads")
510 .prereq(fpRegfileReads);
511
512 fpRegfileWrites
513 .name(name() + ".fp_regfile_writes")
514 .desc("number of floating regfile writes")
515 .prereq(fpRegfileWrites);
516
517 ccRegfileReads
518 .name(name() + ".cc_regfile_reads")
519 .desc("number of cc regfile reads")
520 .prereq(ccRegfileReads);
521
522 ccRegfileWrites
523 .name(name() + ".cc_regfile_writes")
524 .desc("number of cc regfile writes")
525 .prereq(ccRegfileWrites);
526
527 miscRegfileReads
528 .name(name() + ".misc_regfile_reads")
529 .desc("number of misc regfile reads")
530 .prereq(miscRegfileReads);
531
532 miscRegfileWrites
533 .name(name() + ".misc_regfile_writes")
534 .desc("number of misc regfile writes")
535 .prereq(miscRegfileWrites);
536}
537
538template <class Impl>
539void
540FullO3CPU<Impl>::tick()
541{
542 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
543 assert(!switchedOut());
544 assert(drainState() != DrainState::Drained);
545
546 ++numCycles;
547 ppCycles->notify(1);
548
549// activity = false;
550
551 //Tick each of the stages
552 fetch.tick();
553
554 decode.tick();
555
556 rename.tick();
557
558 iew.tick();
559
560 commit.tick();
561
562 // Now advance the time buffers
563 timeBuffer.advance();
564
565 fetchQueue.advance();
566 decodeQueue.advance();
567 renameQueue.advance();
568 iewQueue.advance();
569
570 activityRec.advance();
571
572 if (removeInstsThisCycle) {
573 cleanUpRemovedInsts();
574 }
575
576 if (!tickEvent.scheduled()) {
577 if (_status == SwitchedOut) {
578 DPRINTF(O3CPU, "Switched out!\n");
579 // increment stat
580 lastRunningCycle = curCycle();
581 } else if (!activityRec.active() || _status == Idle) {
582 DPRINTF(O3CPU, "Idle!\n");
583 lastRunningCycle = curCycle();
584 timesIdled++;
585 } else {
586 schedule(tickEvent, clockEdge(Cycles(1)));
587 DPRINTF(O3CPU, "Scheduling next tick!\n");
588 }
589 }
590
591 if (!FullSystem)
592 updateThreadPriority();
593
594 tryDrain();
595}
596
597template <class Impl>
598void
599FullO3CPU<Impl>::init()
600{
601 BaseCPU::init();
602
603 for (ThreadID tid = 0; tid < numThreads; ++tid) {
604 // Set noSquashFromTC so that the CPU doesn't squash when initially
605 // setting up registers.
606 thread[tid]->noSquashFromTC = true;
607 // Initialise the ThreadContext's memory proxies
608 thread[tid]->initMemProxies(thread[tid]->getTC());
609 }
610
611 if (FullSystem && !params()->switched_out) {
612 for (ThreadID tid = 0; tid < numThreads; tid++) {
613 ThreadContext *src_tc = threadContexts[tid];
614 TheISA::initCPU(src_tc, src_tc->contextId());
615 }
616 }
617
618 // Clear noSquashFromTC.
619 for (int tid = 0; tid < numThreads; ++tid)
620 thread[tid]->noSquashFromTC = false;
621
622 commit.setThreads(thread);
623}
624
625template <class Impl>
626void
627FullO3CPU<Impl>::startup()
628{
629 BaseCPU::startup();
630 for (int tid = 0; tid < numThreads; ++tid)
631 isa[tid]->startup(threadContexts[tid]);
632
633 fetch.startupStage();
634 decode.startupStage();
635 iew.startupStage();
636 rename.startupStage();
637 commit.startupStage();
638}
639
640template <class Impl>
641void
642FullO3CPU<Impl>::activateThread(ThreadID tid)
643{
644 list<ThreadID>::iterator isActive =
645 std::find(activeThreads.begin(), activeThreads.end(), tid);
646
647 DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid);
648 assert(!switchedOut());
649
650 if (isActive == activeThreads.end()) {
651 DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n",
652 tid);
653
654 activeThreads.push_back(tid);
655 }
656}
657
658template <class Impl>
659void
660FullO3CPU<Impl>::deactivateThread(ThreadID tid)
661{
662 //Remove From Active List, if Active
663 list<ThreadID>::iterator thread_it =
664 std::find(activeThreads.begin(), activeThreads.end(), tid);
665
666 DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid);
667 assert(!switchedOut());
668
669 if (thread_it != activeThreads.end()) {
670 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
671 tid);
672 activeThreads.erase(thread_it);
673 }
674
675 fetch.deactivateThread(tid);
676 commit.deactivateThread(tid);
677}
678
679template <class Impl>
680Counter
681FullO3CPU<Impl>::totalInsts() const
682{
683 Counter total(0);
684
685 ThreadID size = thread.size();
686 for (ThreadID i = 0; i < size; i++)
687 total += thread[i]->numInst;
688
689 return total;
690}
691
692template <class Impl>
693Counter
694FullO3CPU<Impl>::totalOps() const
695{
696 Counter total(0);
697
698 ThreadID size = thread.size();
699 for (ThreadID i = 0; i < size; i++)
700 total += thread[i]->numOp;
701
702 return total;
703}
704
705template <class Impl>
706void
707FullO3CPU<Impl>::activateContext(ThreadID tid)
708{
709 assert(!switchedOut());
710
711 // Needs to set each stage to running as well.
712 activateThread(tid);
713
714 // We don't want to wake the CPU if it is drained. In that case,
715 // we just want to flag the thread as active and schedule the tick
716 // event from drainResume() instead.
717 if (drainState() == DrainState::Drained)
718 return;
719
720 // If we are time 0 or if the last activation time is in the past,
721 // schedule the next tick and wake up the fetch unit
722 if (lastActivatedCycle == 0 || lastActivatedCycle < curTick()) {
723 scheduleTickEvent(Cycles(0));
724
725 // Be sure to signal that there's some activity so the CPU doesn't
726 // deschedule itself.
727 activityRec.activity();
728 fetch.wakeFromQuiesce();
729
730 Cycles cycles(curCycle() - lastRunningCycle);
731 // @todo: This is an oddity that is only here to match the stats
732 if (cycles != 0)
733 --cycles;
734 quiesceCycles += cycles;
735
736 lastActivatedCycle = curTick();
737
738 _status = Running;
739
740 BaseCPU::activateContext(tid);
741 }
742}
743
744template <class Impl>
745void
746FullO3CPU<Impl>::suspendContext(ThreadID tid)
747{
748 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
749 assert(!switchedOut());
750
751 deactivateThread(tid);
752
753 // If this was the last thread then unschedule the tick event.
754 if (activeThreads.size() == 0) {
755 unscheduleTickEvent();
756 lastRunningCycle = curCycle();
757 _status = Idle;
758 }
759
760 DPRINTF(Quiesce, "Suspending Context\n");
761
762 BaseCPU::suspendContext(tid);
763}
764
765template <class Impl>
766void
767FullO3CPU<Impl>::haltContext(ThreadID tid)
768{
769 //For now, this is the same as deallocate
770 DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
771 assert(!switchedOut());
772
773 deactivateThread(tid);
774 removeThread(tid);
775}
776
777template <class Impl>
778void
779FullO3CPU<Impl>::insertThread(ThreadID tid)
780{
781 DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
782 // Will change now that the PC and thread state is internal to the CPU
783 // and not in the ThreadContext.
784 ThreadContext *src_tc;
785 if (FullSystem)
786 src_tc = system->threadContexts[tid];
787 else
788 src_tc = tcBase(tid);
789
790 //Bind Int Regs to Rename Map
791
792 for (RegId reg_id(IntRegClass, 0); reg_id.regIdx < TheISA::NumIntRegs;
793 reg_id.regIdx++) {
794 PhysRegIndex phys_reg = freeList.getIntReg();
795 renameMap[tid].setEntry(reg_id, phys_reg);
796 scoreboard.setReg(phys_reg);
797 }
798
799 //Bind Float Regs to Rename Map
800 for (RegId reg_id(FloatRegClass, 0); reg_id.regIdx < TheISA::NumFloatRegs;
801 reg_id.regIdx++) {
802 PhysRegIndex phys_reg = freeList.getFloatReg();
803 renameMap[tid].setEntry(reg_id, phys_reg);
804 scoreboard.setReg(phys_reg);
805 }
806
807 //Bind condition-code Regs to Rename Map
808 for (RegId reg_id(CCRegClass, 0); reg_id.regIdx < TheISA::NumCCRegs;
809 reg_id.regIdx++) {
810 PhysRegIndex phys_reg = freeList.getCCReg();
811 renameMap[tid].setEntry(reg_id, phys_reg);
812 scoreboard.setReg(phys_reg);
813 }
814
815 //Copy Thread Data Into RegFile
816 //this->copyFromTC(tid);
817
818 //Set PC/NPC/NNPC
819 pcState(src_tc->pcState(), tid);
820
821 src_tc->setStatus(ThreadContext::Active);
822
823 activateContext(tid);
824
825 //Reset ROB/IQ/LSQ Entries
826 commit.rob->resetEntries();
827 iew.resetEntries();
828}
829
830template <class Impl>
831void
832FullO3CPU<Impl>::removeThread(ThreadID tid)
833{
834 DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
835
836 // Copy Thread Data From RegFile
837 // If thread is suspended, it might be re-allocated
838 // this->copyToTC(tid);
839
840
841 // @todo: 2-27-2008: Fix how we free up rename mappings
842 // here to alleviate the case for double-freeing registers
843 // in SMT workloads.
844
845 // Unbind Int Regs from Rename Map
846 for (RegId reg_id(IntRegClass, 0); reg_id.regIdx < TheISA::NumIntRegs;
847 reg_id.regIdx++) {
848 PhysRegIndex phys_reg = renameMap[tid].lookup(reg_id);
849 scoreboard.unsetReg(phys_reg);
850 freeList.addReg(phys_reg);
851 }
852
853 // Unbind Float Regs from Rename Map
854 for (RegId reg_id(FloatRegClass, 0); reg_id.regIdx < TheISA::NumFloatRegs;
855 reg_id.regIdx++) {
856 PhysRegIndex phys_reg = renameMap[tid].lookup(reg_id);
857 scoreboard.unsetReg(phys_reg);
858 freeList.addReg(phys_reg);
859 }
860
861 // Unbind condition-code Regs from Rename Map
862 for (RegId reg_id(CCRegClass, 0); reg_id.regIdx < TheISA::NumCCRegs;
863 reg_id.regIdx++) {
864 PhysRegIndex phys_reg = renameMap[tid].lookup(reg_id);
865 scoreboard.unsetReg(phys_reg);
866 freeList.addReg(phys_reg);
867 }
868
869 // Squash Throughout Pipeline
870 DynInstPtr inst = commit.rob->readHeadInst(tid);
871 InstSeqNum squash_seq_num = inst->seqNum;
872 fetch.squash(0, squash_seq_num, inst, tid);
873 decode.squash(tid);
874 rename.squash(squash_seq_num, tid);
875 iew.squash(tid);
876 iew.ldstQueue.squash(squash_seq_num, tid);
877 commit.rob->squash(squash_seq_num, tid);
878
879
880 assert(iew.instQueue.getCount(tid) == 0);
881 assert(iew.ldstQueue.getCount(tid) == 0);
882
883 // Reset ROB/IQ/LSQ Entries
884
885 // Commented out for now. This should be possible to do by
886 // telling all the pipeline stages to drain first, and then
887 // checking until the drain completes. Once the pipeline is
888 // drained, call resetEntries(). - 10-09-06 ktlim
889/*
890 if (activeThreads.size() >= 1) {
891 commit.rob->resetEntries();
892 iew.resetEntries();
893 }
894*/
895}
896
897template <class Impl>
898Fault
899FullO3CPU<Impl>::hwrei(ThreadID tid)
900{
901#if THE_ISA == ALPHA_ISA
902 // Need to clear the lock flag upon returning from an interrupt.
903 this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
904
905 this->thread[tid]->kernelStats->hwrei();
906
907 // FIXME: XXX check for interrupts? XXX
908#endif
909 return NoFault;
910}
911
912template <class Impl>
913bool
914FullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid)
915{
916#if THE_ISA == ALPHA_ISA
917 if (this->thread[tid]->kernelStats)
918 this->thread[tid]->kernelStats->callpal(palFunc,
919 this->threadContexts[tid]);
920
921 switch (palFunc) {
922 case PAL::halt:
923 halt();
924 if (--System::numSystemsRunning == 0)
925 exitSimLoop("all cpus halted");
926 break;
927
928 case PAL::bpt:
929 case PAL::bugchk:
930 if (this->system->breakpoint())
931 return false;
932 break;
933 }
934#endif
935 return true;
936}
937
938template <class Impl>
939Fault
940FullO3CPU<Impl>::getInterrupts()
941{
942 // Check if there are any outstanding interrupts
943 return this->interrupts[0]->getInterrupt(this->threadContexts[0]);
944}
945
946template <class Impl>
947void
948FullO3CPU<Impl>::processInterrupts(const Fault &interrupt)
949{
950 // Check for interrupts here. For now can copy the code that
951 // exists within isa_fullsys_traits.hh. Also assume that thread 0
952 // is the one that handles the interrupts.
953 // @todo: Possibly consolidate the interrupt checking code.
954 // @todo: Allow other threads to handle interrupts.
955
956 assert(interrupt != NoFault);
957 this->interrupts[0]->updateIntrInfo(this->threadContexts[0]);
958
959 DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
960 this->trap(interrupt, 0, nullptr);
961}
962
963template <class Impl>
964void
965FullO3CPU<Impl>::trap(const Fault &fault, ThreadID tid,
966 const StaticInstPtr &inst)
967{
968 // Pass the thread's TC into the invoke method.
969 fault->invoke(this->threadContexts[tid], inst);
970}
971
972template <class Impl>
973void
974FullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid, Fault *fault)
975{
976 DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid);
977
978 DPRINTF(Activity,"Activity: syscall() called.\n");
979
980 // Temporarily increase this by one to account for the syscall
981 // instruction.
982 ++(this->thread[tid]->funcExeInst);
983
984 // Execute the actual syscall.
985 this->thread[tid]->syscall(callnum, fault);
986
987 // Decrease funcExeInst by one as the normal commit will handle
988 // incrementing it.
989 --(this->thread[tid]->funcExeInst);
990}
991
992template <class Impl>
993void
994FullO3CPU<Impl>::serializeThread(CheckpointOut &cp, ThreadID tid) const
995{
996 thread[tid]->serialize(cp);
997}
998
999template <class Impl>
1000void
1001FullO3CPU<Impl>::unserializeThread(CheckpointIn &cp, ThreadID tid)
1002{
1003 thread[tid]->unserialize(cp);
1004}
1005
1006template <class Impl>
1007DrainState
1008FullO3CPU<Impl>::drain()
1009{
1010 // If the CPU isn't doing anything, then return immediately.
1011 if (switchedOut())
1012 return DrainState::Drained;
1013
1014 DPRINTF(Drain, "Draining...\n");
1015
1016 // We only need to signal a drain to the commit stage as this
1017 // initiates squashing controls the draining. Once the commit
1018 // stage commits an instruction where it is safe to stop, it'll
1019 // squash the rest of the instructions in the pipeline and force
1020 // the fetch stage to stall. The pipeline will be drained once all
1021 // in-flight instructions have retired.
1022 commit.drain();
1023
1024 // Wake the CPU and record activity so everything can drain out if
1025 // the CPU was not able to immediately drain.
1026 if (!isDrained()) {
1027 wakeCPU();
1028 activityRec.activity();
1029
1030 DPRINTF(Drain, "CPU not drained\n");
1031
1032 return DrainState::Draining;
1033 } else {
1034 DPRINTF(Drain, "CPU is already drained\n");
1035 if (tickEvent.scheduled())
1036 deschedule(tickEvent);
1037
1038 // Flush out any old data from the time buffers. In
1039 // particular, there might be some data in flight from the
1040 // fetch stage that isn't visible in any of the CPU buffers we
1041 // test in isDrained().
1042 for (int i = 0; i < timeBuffer.getSize(); ++i) {
1043 timeBuffer.advance();
1044 fetchQueue.advance();
1045 decodeQueue.advance();
1046 renameQueue.advance();
1047 iewQueue.advance();
1048 }
1049
1050 drainSanityCheck();
1051 return DrainState::Drained;
1052 }
1053}
1054
1055template <class Impl>
1056bool
1057FullO3CPU<Impl>::tryDrain()
1058{
1059 if (drainState() != DrainState::Draining || !isDrained())
1060 return false;
1061
1062 if (tickEvent.scheduled())
1063 deschedule(tickEvent);
1064
1065 DPRINTF(Drain, "CPU done draining, processing drain event\n");
1066 signalDrainDone();
1067
1068 return true;
1069}
1070
1071template <class Impl>
1072void
1073FullO3CPU<Impl>::drainSanityCheck() const
1074{
1075 assert(isDrained());
1076 fetch.drainSanityCheck();
1077 decode.drainSanityCheck();
1078 rename.drainSanityCheck();
1079 iew.drainSanityCheck();
1080 commit.drainSanityCheck();
1081}
1082
1083template <class Impl>
1084bool
1085FullO3CPU<Impl>::isDrained() const
1086{
1087 bool drained(true);
1088
1089 if (!instList.empty() || !removeList.empty()) {
1090 DPRINTF(Drain, "Main CPU structures not drained.\n");
1091 drained = false;
1092 }
1093
1094 if (!fetch.isDrained()) {
1095 DPRINTF(Drain, "Fetch not drained.\n");
1096 drained = false;
1097 }
1098
1099 if (!decode.isDrained()) {
1100 DPRINTF(Drain, "Decode not drained.\n");
1101 drained = false;
1102 }
1103
1104 if (!rename.isDrained()) {
1105 DPRINTF(Drain, "Rename not drained.\n");
1106 drained = false;
1107 }
1108
1109 if (!iew.isDrained()) {
1110 DPRINTF(Drain, "IEW not drained.\n");
1111 drained = false;
1112 }
1113
1114 if (!commit.isDrained()) {
1115 DPRINTF(Drain, "Commit not drained.\n");
1116 drained = false;
1117 }
1118
1119 return drained;
1120}
1121
1122template <class Impl>
1123void
1124FullO3CPU<Impl>::commitDrained(ThreadID tid)
1125{
1126 fetch.drainStall(tid);
1127}
1128
1129template <class Impl>
1130void
1131FullO3CPU<Impl>::drainResume()
1132{
1133 if (switchedOut())
1134 return;
1135
1136 DPRINTF(Drain, "Resuming...\n");
1137 verifyMemoryMode();
1138
1139 fetch.drainResume();
1140 commit.drainResume();
1141
1142 _status = Idle;
1143 for (ThreadID i = 0; i < thread.size(); i++) {
1144 if (thread[i]->status() == ThreadContext::Active) {
1145 DPRINTF(Drain, "Activating thread: %i\n", i);
1146 activateThread(i);
1147 _status = Running;
1148 }
1149 }
1150
1151 assert(!tickEvent.scheduled());
1152 if (_status == Running)
1153 schedule(tickEvent, nextCycle());
1154}
1155
1156template <class Impl>
1157void
1158FullO3CPU<Impl>::switchOut()
1159{
1160 DPRINTF(O3CPU, "Switching out\n");
1161 BaseCPU::switchOut();
1162
1163 activityRec.reset();
1164
1165 _status = SwitchedOut;
1166
1167 if (checker)
1168 checker->switchOut();
1169}
1170
1171template <class Impl>
1172void
1173FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
1174{
1175 BaseCPU::takeOverFrom(oldCPU);
1176
1177 fetch.takeOverFrom();
1178 decode.takeOverFrom();
1179 rename.takeOverFrom();
1180 iew.takeOverFrom();
1181 commit.takeOverFrom();
1182
1183 assert(!tickEvent.scheduled());
1184
1185 FullO3CPU<Impl> *oldO3CPU = dynamic_cast<FullO3CPU<Impl>*>(oldCPU);
1186 if (oldO3CPU)
1187 globalSeqNum = oldO3CPU->globalSeqNum;
1188
1189 lastRunningCycle = curCycle();
1190 _status = Idle;
1191}
1192
1193template <class Impl>
1194void
1195FullO3CPU<Impl>::verifyMemoryMode() const
1196{
1197 if (!system->isTimingMode()) {
1198 fatal("The O3 CPU requires the memory system to be in "
1199 "'timing' mode.\n");
1200 }
1201}
1202
1203template <class Impl>
1204TheISA::MiscReg
1205FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
1206{
1207 return this->isa[tid]->readMiscRegNoEffect(misc_reg);
1208}
1209
1210template <class Impl>
1211TheISA::MiscReg
1212FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
1213{
1214 miscRegfileReads++;
1215 return this->isa[tid]->readMiscReg(misc_reg, tcBase(tid));
1216}
1217
1218template <class Impl>
1219void
1220FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
1221 const TheISA::MiscReg &val, ThreadID tid)
1222{
1223 this->isa[tid]->setMiscRegNoEffect(misc_reg, val);
1224}
1225
1226template <class Impl>
1227void
1228FullO3CPU<Impl>::setMiscReg(int misc_reg,
1229 const TheISA::MiscReg &val, ThreadID tid)
1230{
1231 miscRegfileWrites++;
1232 this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid));
1233}
1234
1235template <class Impl>
1236uint64_t
1237FullO3CPU<Impl>::readIntReg(int reg_idx)
1238{
1239 intRegfileReads++;
1240 return regFile.readIntReg(reg_idx);
1241}
1242
1243template <class Impl>
1244FloatReg
1245FullO3CPU<Impl>::readFloatReg(int reg_idx)
1246{
1247 fpRegfileReads++;
1248 return regFile.readFloatReg(reg_idx);
1249}
1250
1251template <class Impl>
1252FloatRegBits
1253FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
1254{
1255 fpRegfileReads++;
1256 return regFile.readFloatRegBits(reg_idx);
1257}
1258
1259template <class Impl>
1260CCReg
1261FullO3CPU<Impl>::readCCReg(int reg_idx)
1262{
1263 ccRegfileReads++;
1264 return regFile.readCCReg(reg_idx);
1265}
1266
1267template <class Impl>
1268void
1269FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
1270{
1271 intRegfileWrites++;
1272 regFile.setIntReg(reg_idx, val);
1273}
1274
1275template <class Impl>
1276void
1277FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
1278{
1279 fpRegfileWrites++;
1280 regFile.setFloatReg(reg_idx, val);
1281}
1282
1283template <class Impl>
1284void
1285FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
1286{
1287 fpRegfileWrites++;
1288 regFile.setFloatRegBits(reg_idx, val);
1289}
1290
1291template <class Impl>
1292void
1293FullO3CPU<Impl>::setCCReg(int reg_idx, CCReg val)
1294{
1295 ccRegfileWrites++;
1296 regFile.setCCReg(reg_idx, val);
1297}
1298
1299template <class Impl>
1300uint64_t
1301FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1302{
1303 intRegfileReads++;
1304 PhysRegIndex phys_reg = commitRenameMap[tid].lookupInt(reg_idx);
1305
1306 return regFile.readIntReg(phys_reg);
1307}
1308
1309template <class Impl>
1310float
1311FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
1312{
1313 fpRegfileReads++;
1314 PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1315
1316 return regFile.readFloatReg(phys_reg);
1317}
1318
1319template <class Impl>
1320uint64_t
1321FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid)
1322{
1323 fpRegfileReads++;
1324 PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1325
1326 return regFile.readFloatRegBits(phys_reg);
1327}
1328
1329template <class Impl>
1330CCReg
1331FullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid)
1332{
1333 ccRegfileReads++;
1334 PhysRegIndex phys_reg = commitRenameMap[tid].lookupCC(reg_idx);
1335
1336 return regFile.readCCReg(phys_reg);
1337}
1338
1339template <class Impl>
1340void
1341FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
1342{
1343 intRegfileWrites++;
1344 PhysRegIndex phys_reg = commitRenameMap[tid].lookupInt(reg_idx);
1345
1346 regFile.setIntReg(phys_reg, val);
1347}
1348
1349template <class Impl>
1350void
1351FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid)
1352{
1353 fpRegfileWrites++;
1354 PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1355
1356 regFile.setFloatReg(phys_reg, val);
1357}
1358
1359template <class Impl>
1360void
1361FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid)
1362{
1363 fpRegfileWrites++;
1364 PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1365
1366 regFile.setFloatRegBits(phys_reg, val);
1367}
1368
1369template <class Impl>
1370void
1371FullO3CPU<Impl>::setArchCCReg(int reg_idx, CCReg val, ThreadID tid)
1372{
1373 ccRegfileWrites++;
1374 PhysRegIndex phys_reg = commitRenameMap[tid].lookupCC(reg_idx);
1375
1376 regFile.setCCReg(phys_reg, val);
1377}
1378
1379template <class Impl>
1380TheISA::PCState
1381FullO3CPU<Impl>::pcState(ThreadID tid)
1382{
1383 return commit.pcState(tid);
1384}
1385
1386template <class Impl>
1387void
1388FullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid)
1389{
1390 commit.pcState(val, tid);
1391}
1392
1393template <class Impl>
1394Addr
1395FullO3CPU<Impl>::instAddr(ThreadID tid)
1396{
1397 return commit.instAddr(tid);
1398}
1399
1400template <class Impl>
1401Addr
1402FullO3CPU<Impl>::nextInstAddr(ThreadID tid)
1403{
1404 return commit.nextInstAddr(tid);
1405}
1406
1407template <class Impl>
1408MicroPC
1409FullO3CPU<Impl>::microPC(ThreadID tid)
1410{
1411 return commit.microPC(tid);
1412}
1413
1414template <class Impl>
1415void
1416FullO3CPU<Impl>::squashFromTC(ThreadID tid)
1417{
1418 this->thread[tid]->noSquashFromTC = true;
1419 this->commit.generateTCEvent(tid);
1420}
1421
1422template <class Impl>
1423typename FullO3CPU<Impl>::ListIt
1424FullO3CPU<Impl>::addInst(DynInstPtr &inst)
1425{
1426 instList.push_back(inst);
1427
1428 return --(instList.end());
1429}
1430
1431template <class Impl>
1432void
1433FullO3CPU<Impl>::instDone(ThreadID tid, DynInstPtr &inst)
1434{
1435 // Keep an instruction count.
1436 if (!inst->isMicroop() || inst->isLastMicroop()) {
1437 thread[tid]->numInst++;
1438 thread[tid]->numInsts++;
1439 committedInsts[tid]++;
1440 system->totalNumInsts++;
1441
1442 // Check for instruction-count-based events.
1443 comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1444 system->instEventQueue.serviceEvents(system->totalNumInsts);
1445 }
1446 thread[tid]->numOp++;
1447 thread[tid]->numOps++;
1448 committedOps[tid]++;
1449
1450 probeInstCommit(inst->staticInst);
1451}
1452
1453template <class Impl>
1454void
1455FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
1456{
1457 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s "
1458 "[sn:%lli]\n",
1459 inst->threadNumber, inst->pcState(), inst->seqNum);
1460
1461 removeInstsThisCycle = true;
1462
1463 // Remove the front instruction.
1464 removeList.push(inst->getInstListIt());
1465}
1466
1467template <class Impl>
1468void
1469FullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid)
1470{
1471 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1472 " list.\n", tid);
1473
1474 ListIt end_it;
1475
1476 bool rob_empty = false;
1477
1478 if (instList.empty()) {
1479 return;
1480 } else if (rob.isEmpty(tid)) {
1481 DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1482 end_it = instList.begin();
1483 rob_empty = true;
1484 } else {
1485 end_it = (rob.readTailInst(tid))->getInstListIt();
1486 DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1487 }
1488
1489 removeInstsThisCycle = true;
1490
1491 ListIt inst_it = instList.end();
1492
1493 inst_it--;
1494
1495 // Walk through the instruction list, removing any instructions
1496 // that were inserted after the given instruction iterator, end_it.
1497 while (inst_it != end_it) {
1498 assert(!instList.empty());
1499
1500 squashInstIt(inst_it, tid);
1501
1502 inst_it--;
1503 }
1504
1505 // If the ROB was empty, then we actually need to remove the first
1506 // instruction as well.
1507 if (rob_empty) {
1508 squashInstIt(inst_it, tid);
1509 }
1510}
1511
1512template <class Impl>
1513void
1514FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1515{
1516 assert(!instList.empty());
1517
1518 removeInstsThisCycle = true;
1519
1520 ListIt inst_iter = instList.end();
1521
1522 inst_iter--;
1523
1524 DPRINTF(O3CPU, "Deleting instructions from instruction "
1525 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1526 tid, seq_num, (*inst_iter)->seqNum);
1527
1528 while ((*inst_iter)->seqNum > seq_num) {
1529
1530 bool break_loop = (inst_iter == instList.begin());
1531
1532 squashInstIt(inst_iter, tid);
1533
1534 inst_iter--;
1535
1536 if (break_loop)
1537 break;
1538 }
1539}
1540
1541template <class Impl>
1542inline void
1543FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid)
1544{
1545 if ((*instIt)->threadNumber == tid) {
1546 DPRINTF(O3CPU, "Squashing instruction, "
1547 "[tid:%i] [sn:%lli] PC %s\n",
1548 (*instIt)->threadNumber,
1549 (*instIt)->seqNum,
1550 (*instIt)->pcState());
1551
1552 // Mark it as squashed.
1553 (*instIt)->setSquashed();
1554
1555 // @todo: Formulate a consistent method for deleting
1556 // instructions from the instruction list
1557 // Remove the instruction from the list.
1558 removeList.push(instIt);
1559 }
1560}
1561
1562template <class Impl>
1563void
1564FullO3CPU<Impl>::cleanUpRemovedInsts()
1565{
1566 while (!removeList.empty()) {
1567 DPRINTF(O3CPU, "Removing instruction, "
1568 "[tid:%i] [sn:%lli] PC %s\n",
1569 (*removeList.front())->threadNumber,
1570 (*removeList.front())->seqNum,
1571 (*removeList.front())->pcState());
1572
1573 instList.erase(removeList.front());
1574
1575 removeList.pop();
1576 }
1577
1578 removeInstsThisCycle = false;
1579}
1580/*
1581template <class Impl>
1582void
1583FullO3CPU<Impl>::removeAllInsts()
1584{
1585 instList.clear();
1586}
1587*/
1588template <class Impl>
1589void
1590FullO3CPU<Impl>::dumpInsts()
1591{
1592 int num = 0;
1593
1594 ListIt inst_list_it = instList.begin();
1595
1596 cprintf("Dumping Instruction List\n");
1597
1598 while (inst_list_it != instList.end()) {
1599 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1600 "Squashed:%i\n\n",
1601 num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber,
1602 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1603 (*inst_list_it)->isSquashed());
1604 inst_list_it++;
1605 ++num;
1606 }
1607}
1608/*
1609template <class Impl>
1610void
1611FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
1612{
1613 iew.wakeDependents(inst);
1614}
1615*/
1616template <class Impl>
1617void
1618FullO3CPU<Impl>::wakeCPU()
1619{
1620 if (activityRec.active() || tickEvent.scheduled()) {
1621 DPRINTF(Activity, "CPU already running.\n");
1622 return;
1623 }
1624
1625 DPRINTF(Activity, "Waking up CPU\n");
1626
1627 Cycles cycles(curCycle() - lastRunningCycle);
1628 // @todo: This is an oddity that is only here to match the stats
1629 if (cycles > 1) {
1630 --cycles;
1631 idleCycles += cycles;
1632 numCycles += cycles;
1633 ppCycles->notify(cycles);
1634 }
1635
1636 schedule(tickEvent, clockEdge());
1637}
1638
1639template <class Impl>
1640void
1641FullO3CPU<Impl>::wakeup(ThreadID tid)
1642{
1643 if (this->thread[tid]->status() != ThreadContext::Suspended)
1644 return;
1645
1646 this->wakeCPU();
1647
1648 DPRINTF(Quiesce, "Suspended Processor woken\n");
1649 this->threadContexts[tid]->activate();
1650}
1651
1652template <class Impl>
1653ThreadID
1654FullO3CPU<Impl>::getFreeTid()
1655{
1656 for (ThreadID tid = 0; tid < numThreads; tid++) {
1657 if (!tids[tid]) {
1658 tids[tid] = true;
1659 return tid;
1660 }
1661 }
1662
1663 return InvalidThreadID;
1664}
1665
1666template <class Impl>
1667void
1668FullO3CPU<Impl>::updateThreadPriority()
1669{
1670 if (activeThreads.size() > 1) {
1671 //DEFAULT TO ROUND ROBIN SCHEME
1672 //e.g. Move highest priority to end of thread list
1673 list<ThreadID>::iterator list_begin = activeThreads.begin();
1674
1675 unsigned high_thread = *list_begin;
1676
1677 activeThreads.erase(list_begin);
1678
1679 activeThreads.push_back(high_thread);
1680 }
1681}
1682
1683// Forward declaration of FullO3CPU.
1684template class FullO3CPU<O3CPUImpl>;
2 * Copyright (c) 2011-2012, 2014 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * Copyright (c) 2011 Regents of the University of California
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Kevin Lim
43 * Korey Sewell
44 * Rick Strong
45 */
46
47#include "cpu/o3/cpu.hh"
48
49#include "arch/kernel_stats.hh"
50#include "config/the_isa.hh"
51#include "cpu/activity.hh"
52#include "cpu/checker/cpu.hh"
53#include "cpu/checker/thread_context.hh"
54#include "cpu/o3/isa_specific.hh"
55#include "cpu/o3/thread_context.hh"
56#include "cpu/quiesce_event.hh"
57#include "cpu/simple_thread.hh"
58#include "cpu/thread_context.hh"
59#include "debug/Activity.hh"
60#include "debug/Drain.hh"
61#include "debug/O3CPU.hh"
62#include "debug/Quiesce.hh"
63#include "enums/MemoryMode.hh"
64#include "sim/core.hh"
65#include "sim/full_system.hh"
66#include "sim/process.hh"
67#include "sim/stat_control.hh"
68#include "sim/system.hh"
69
70#if THE_ISA == ALPHA_ISA
71#include "arch/alpha/osfpal.hh"
72#include "debug/Activity.hh"
73
74#endif
75
76struct BaseCPUParams;
77
78using namespace TheISA;
79using namespace std;
80
81BaseO3CPU::BaseO3CPU(BaseCPUParams *params)
82 : BaseCPU(params)
83{
84}
85
86void
87BaseO3CPU::regStats()
88{
89 BaseCPU::regStats();
90}
91
92template<class Impl>
93bool
94FullO3CPU<Impl>::IcachePort::recvTimingResp(PacketPtr pkt)
95{
96 DPRINTF(O3CPU, "Fetch unit received timing\n");
97 // We shouldn't ever get a cacheable block in Modified state
98 assert(pkt->req->isUncacheable() ||
99 !(pkt->cacheResponding() && !pkt->hasSharers()));
100 fetch->processCacheCompletion(pkt);
101
102 return true;
103}
104
105template<class Impl>
106void
107FullO3CPU<Impl>::IcachePort::recvReqRetry()
108{
109 fetch->recvReqRetry();
110}
111
112template <class Impl>
113bool
114FullO3CPU<Impl>::DcachePort::recvTimingResp(PacketPtr pkt)
115{
116 return lsq->recvTimingResp(pkt);
117}
118
119template <class Impl>
120void
121FullO3CPU<Impl>::DcachePort::recvTimingSnoopReq(PacketPtr pkt)
122{
123 for (ThreadID tid = 0; tid < cpu->numThreads; tid++) {
124 if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) {
125 cpu->wakeup(tid);
126 }
127 }
128 lsq->recvTimingSnoopReq(pkt);
129}
130
131template <class Impl>
132void
133FullO3CPU<Impl>::DcachePort::recvReqRetry()
134{
135 lsq->recvReqRetry();
136}
137
138template <class Impl>
139FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
140 : Event(CPU_Tick_Pri), cpu(c)
141{
142}
143
144template <class Impl>
145void
146FullO3CPU<Impl>::TickEvent::process()
147{
148 cpu->tick();
149}
150
151template <class Impl>
152const char *
153FullO3CPU<Impl>::TickEvent::description() const
154{
155 return "FullO3CPU tick";
156}
157
158template <class Impl>
159FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
160 : BaseO3CPU(params),
161 itb(params->itb),
162 dtb(params->dtb),
163 tickEvent(this),
164#ifndef NDEBUG
165 instcount(0),
166#endif
167 removeInstsThisCycle(false),
168 fetch(this, params),
169 decode(this, params),
170 rename(this, params),
171 iew(this, params),
172 commit(this, params),
173
174 regFile(params->numPhysIntRegs,
175 params->numPhysFloatRegs,
176 params->numPhysCCRegs),
177
178 freeList(name() + ".freelist", ®File),
179
180 rob(this, params),
181
182 scoreboard(name() + ".scoreboard",
183 regFile.totalNumPhysRegs(), TheISA::NumMiscRegs,
184 TheISA::ZeroReg, TheISA::ZeroReg),
185
186 isa(numThreads, NULL),
187
188 icachePort(&fetch, this),
189 dcachePort(&iew.ldstQueue, this),
190
191 timeBuffer(params->backComSize, params->forwardComSize),
192 fetchQueue(params->backComSize, params->forwardComSize),
193 decodeQueue(params->backComSize, params->forwardComSize),
194 renameQueue(params->backComSize, params->forwardComSize),
195 iewQueue(params->backComSize, params->forwardComSize),
196 activityRec(name(), NumStages,
197 params->backComSize + params->forwardComSize,
198 params->activity),
199
200 globalSeqNum(1),
201 system(params->system),
202 lastRunningCycle(curCycle())
203{
204 if (!params->switched_out) {
205 _status = Running;
206 } else {
207 _status = SwitchedOut;
208 }
209
210 if (params->checker) {
211 BaseCPU *temp_checker = params->checker;
212 checker = dynamic_cast<Checker<Impl> *>(temp_checker);
213 checker->setIcachePort(&icachePort);
214 checker->setSystem(params->system);
215 } else {
216 checker = NULL;
217 }
218
219 if (!FullSystem) {
220 thread.resize(numThreads);
221 tids.resize(numThreads);
222 }
223
224 // The stages also need their CPU pointer setup. However this
225 // must be done at the upper level CPU because they have pointers
226 // to the upper level CPU, and not this FullO3CPU.
227
228 // Set up Pointers to the activeThreads list for each stage
229 fetch.setActiveThreads(&activeThreads);
230 decode.setActiveThreads(&activeThreads);
231 rename.setActiveThreads(&activeThreads);
232 iew.setActiveThreads(&activeThreads);
233 commit.setActiveThreads(&activeThreads);
234
235 // Give each of the stages the time buffer they will use.
236 fetch.setTimeBuffer(&timeBuffer);
237 decode.setTimeBuffer(&timeBuffer);
238 rename.setTimeBuffer(&timeBuffer);
239 iew.setTimeBuffer(&timeBuffer);
240 commit.setTimeBuffer(&timeBuffer);
241
242 // Also setup each of the stages' queues.
243 fetch.setFetchQueue(&fetchQueue);
244 decode.setFetchQueue(&fetchQueue);
245 commit.setFetchQueue(&fetchQueue);
246 decode.setDecodeQueue(&decodeQueue);
247 rename.setDecodeQueue(&decodeQueue);
248 rename.setRenameQueue(&renameQueue);
249 iew.setRenameQueue(&renameQueue);
250 iew.setIEWQueue(&iewQueue);
251 commit.setIEWQueue(&iewQueue);
252 commit.setRenameQueue(&renameQueue);
253
254 commit.setIEWStage(&iew);
255 rename.setIEWStage(&iew);
256 rename.setCommitStage(&commit);
257
258 ThreadID active_threads;
259 if (FullSystem) {
260 active_threads = 1;
261 } else {
262 active_threads = params->workload.size();
263
264 if (active_threads > Impl::MaxThreads) {
265 panic("Workload Size too large. Increase the 'MaxThreads' "
266 "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) "
267 "or edit your workload size.");
268 }
269 }
270
271 //Make Sure That this a Valid Architeture
272 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs);
273 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
274 assert(params->numPhysCCRegs >= numThreads * TheISA::NumCCRegs);
275
276 rename.setScoreboard(&scoreboard);
277 iew.setScoreboard(&scoreboard);
278
279 // Setup the rename map for whichever stages need it.
280 for (ThreadID tid = 0; tid < numThreads; tid++) {
281 isa[tid] = params->isa[tid];
282
283 // Only Alpha has an FP zero register, so for other ISAs we
284 // use an invalid FP register index to avoid special treatment
285 // of any valid FP reg.
286 RegIndex invalidFPReg = TheISA::NumFloatRegs + 1;
287 RegIndex fpZeroReg =
288 (THE_ISA == ALPHA_ISA) ? TheISA::ZeroReg : invalidFPReg;
289
290 commitRenameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg,
291 &freeList);
292
293 renameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg,
294 &freeList);
295 }
296
297 // Initialize rename map to assign physical registers to the
298 // architectural registers for active threads only.
299 for (ThreadID tid = 0; tid < active_threads; tid++) {
300 for (RegIndex ridx = 0; ridx < TheISA::NumIntRegs; ++ridx) {
301 // Note that we can't use the rename() method because we don't
302 // want special treatment for the zero register at this point
303 PhysRegIndex phys_reg = freeList.getIntReg();
304 renameMap[tid].setIntEntry(ridx, phys_reg);
305 commitRenameMap[tid].setIntEntry(ridx, phys_reg);
306 }
307
308 for (RegIndex ridx = 0; ridx < TheISA::NumFloatRegs; ++ridx) {
309 PhysRegIndex phys_reg = freeList.getFloatReg();
310 renameMap[tid].setFloatEntry(ridx, phys_reg);
311 commitRenameMap[tid].setFloatEntry(ridx, phys_reg);
312 }
313
314 for (RegIndex ridx = 0; ridx < TheISA::NumCCRegs; ++ridx) {
315 PhysRegIndex phys_reg = freeList.getCCReg();
316 renameMap[tid].setCCEntry(ridx, phys_reg);
317 commitRenameMap[tid].setCCEntry(ridx, phys_reg);
318 }
319 }
320
321 rename.setRenameMap(renameMap);
322 commit.setRenameMap(commitRenameMap);
323 rename.setFreeList(&freeList);
324
325 // Setup the ROB for whichever stages need it.
326 commit.setROB(&rob);
327
328 lastActivatedCycle = 0;
329#if 0
330 // Give renameMap & rename stage access to the freeList;
331 for (ThreadID tid = 0; tid < numThreads; tid++)
332 globalSeqNum[tid] = 1;
333#endif
334
335 DPRINTF(O3CPU, "Creating O3CPU object.\n");
336
337 // Setup any thread state.
338 this->thread.resize(this->numThreads);
339
340 for (ThreadID tid = 0; tid < this->numThreads; ++tid) {
341 if (FullSystem) {
342 // SMT is not supported in FS mode yet.
343 assert(this->numThreads == 1);
344 this->thread[tid] = new Thread(this, 0, NULL);
345 } else {
346 if (tid < params->workload.size()) {
347 DPRINTF(O3CPU, "Workload[%i] process is %#x",
348 tid, this->thread[tid]);
349 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
350 (typename Impl::O3CPU *)(this),
351 tid, params->workload[tid]);
352
353 //usedTids[tid] = true;
354 //threadMap[tid] = tid;
355 } else {
356 //Allocate Empty thread so M5 can use later
357 //when scheduling threads to CPU
358 Process* dummy_proc = NULL;
359
360 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
361 (typename Impl::O3CPU *)(this),
362 tid, dummy_proc);
363 //usedTids[tid] = false;
364 }
365 }
366
367 ThreadContext *tc;
368
369 // Setup the TC that will serve as the interface to the threads/CPU.
370 O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>;
371
372 tc = o3_tc;
373
374 // If we're using a checker, then the TC should be the
375 // CheckerThreadContext.
376 if (params->checker) {
377 tc = new CheckerThreadContext<O3ThreadContext<Impl> >(
378 o3_tc, this->checker);
379 }
380
381 o3_tc->cpu = (typename Impl::O3CPU *)(this);
382 assert(o3_tc->cpu);
383 o3_tc->thread = this->thread[tid];
384
385 // Setup quiesce event.
386 this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
387
388 // Give the thread the TC.
389 this->thread[tid]->tc = tc;
390
391 // Add the TC to the CPU's list of TC's.
392 this->threadContexts.push_back(tc);
393 }
394
395 // FullO3CPU always requires an interrupt controller.
396 if (!params->switched_out && interrupts.empty()) {
397 fatal("FullO3CPU %s has no interrupt controller.\n"
398 "Ensure createInterruptController() is called.\n", name());
399 }
400
401 for (ThreadID tid = 0; tid < this->numThreads; tid++)
402 this->thread[tid]->setFuncExeInst(0);
403}
404
405template <class Impl>
406FullO3CPU<Impl>::~FullO3CPU()
407{
408}
409
410template <class Impl>
411void
412FullO3CPU<Impl>::regProbePoints()
413{
414 BaseCPU::regProbePoints();
415
416 ppInstAccessComplete = new ProbePointArg<PacketPtr>(getProbeManager(), "InstAccessComplete");
417 ppDataAccessComplete = new ProbePointArg<std::pair<DynInstPtr, PacketPtr> >(getProbeManager(), "DataAccessComplete");
418
419 fetch.regProbePoints();
420 rename.regProbePoints();
421 iew.regProbePoints();
422 commit.regProbePoints();
423}
424
425template <class Impl>
426void
427FullO3CPU<Impl>::regStats()
428{
429 BaseO3CPU::regStats();
430
431 // Register any of the O3CPU's stats here.
432 timesIdled
433 .name(name() + ".timesIdled")
434 .desc("Number of times that the entire CPU went into an idle state and"
435 " unscheduled itself")
436 .prereq(timesIdled);
437
438 idleCycles
439 .name(name() + ".idleCycles")
440 .desc("Total number of cycles that the CPU has spent unscheduled due "
441 "to idling")
442 .prereq(idleCycles);
443
444 quiesceCycles
445 .name(name() + ".quiesceCycles")
446 .desc("Total number of cycles that CPU has spent quiesced or waiting "
447 "for an interrupt")
448 .prereq(quiesceCycles);
449
450 // Number of Instructions simulated
451 // --------------------------------
452 // Should probably be in Base CPU but need templated
453 // MaxThreads so put in here instead
454 committedInsts
455 .init(numThreads)
456 .name(name() + ".committedInsts")
457 .desc("Number of Instructions Simulated")
458 .flags(Stats::total);
459
460 committedOps
461 .init(numThreads)
462 .name(name() + ".committedOps")
463 .desc("Number of Ops (including micro ops) Simulated")
464 .flags(Stats::total);
465
466 cpi
467 .name(name() + ".cpi")
468 .desc("CPI: Cycles Per Instruction")
469 .precision(6);
470 cpi = numCycles / committedInsts;
471
472 totalCpi
473 .name(name() + ".cpi_total")
474 .desc("CPI: Total CPI of All Threads")
475 .precision(6);
476 totalCpi = numCycles / sum(committedInsts);
477
478 ipc
479 .name(name() + ".ipc")
480 .desc("IPC: Instructions Per Cycle")
481 .precision(6);
482 ipc = committedInsts / numCycles;
483
484 totalIpc
485 .name(name() + ".ipc_total")
486 .desc("IPC: Total IPC of All Threads")
487 .precision(6);
488 totalIpc = sum(committedInsts) / numCycles;
489
490 this->fetch.regStats();
491 this->decode.regStats();
492 this->rename.regStats();
493 this->iew.regStats();
494 this->commit.regStats();
495 this->rob.regStats();
496
497 intRegfileReads
498 .name(name() + ".int_regfile_reads")
499 .desc("number of integer regfile reads")
500 .prereq(intRegfileReads);
501
502 intRegfileWrites
503 .name(name() + ".int_regfile_writes")
504 .desc("number of integer regfile writes")
505 .prereq(intRegfileWrites);
506
507 fpRegfileReads
508 .name(name() + ".fp_regfile_reads")
509 .desc("number of floating regfile reads")
510 .prereq(fpRegfileReads);
511
512 fpRegfileWrites
513 .name(name() + ".fp_regfile_writes")
514 .desc("number of floating regfile writes")
515 .prereq(fpRegfileWrites);
516
517 ccRegfileReads
518 .name(name() + ".cc_regfile_reads")
519 .desc("number of cc regfile reads")
520 .prereq(ccRegfileReads);
521
522 ccRegfileWrites
523 .name(name() + ".cc_regfile_writes")
524 .desc("number of cc regfile writes")
525 .prereq(ccRegfileWrites);
526
527 miscRegfileReads
528 .name(name() + ".misc_regfile_reads")
529 .desc("number of misc regfile reads")
530 .prereq(miscRegfileReads);
531
532 miscRegfileWrites
533 .name(name() + ".misc_regfile_writes")
534 .desc("number of misc regfile writes")
535 .prereq(miscRegfileWrites);
536}
537
538template <class Impl>
539void
540FullO3CPU<Impl>::tick()
541{
542 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
543 assert(!switchedOut());
544 assert(drainState() != DrainState::Drained);
545
546 ++numCycles;
547 ppCycles->notify(1);
548
549// activity = false;
550
551 //Tick each of the stages
552 fetch.tick();
553
554 decode.tick();
555
556 rename.tick();
557
558 iew.tick();
559
560 commit.tick();
561
562 // Now advance the time buffers
563 timeBuffer.advance();
564
565 fetchQueue.advance();
566 decodeQueue.advance();
567 renameQueue.advance();
568 iewQueue.advance();
569
570 activityRec.advance();
571
572 if (removeInstsThisCycle) {
573 cleanUpRemovedInsts();
574 }
575
576 if (!tickEvent.scheduled()) {
577 if (_status == SwitchedOut) {
578 DPRINTF(O3CPU, "Switched out!\n");
579 // increment stat
580 lastRunningCycle = curCycle();
581 } else if (!activityRec.active() || _status == Idle) {
582 DPRINTF(O3CPU, "Idle!\n");
583 lastRunningCycle = curCycle();
584 timesIdled++;
585 } else {
586 schedule(tickEvent, clockEdge(Cycles(1)));
587 DPRINTF(O3CPU, "Scheduling next tick!\n");
588 }
589 }
590
591 if (!FullSystem)
592 updateThreadPriority();
593
594 tryDrain();
595}
596
597template <class Impl>
598void
599FullO3CPU<Impl>::init()
600{
601 BaseCPU::init();
602
603 for (ThreadID tid = 0; tid < numThreads; ++tid) {
604 // Set noSquashFromTC so that the CPU doesn't squash when initially
605 // setting up registers.
606 thread[tid]->noSquashFromTC = true;
607 // Initialise the ThreadContext's memory proxies
608 thread[tid]->initMemProxies(thread[tid]->getTC());
609 }
610
611 if (FullSystem && !params()->switched_out) {
612 for (ThreadID tid = 0; tid < numThreads; tid++) {
613 ThreadContext *src_tc = threadContexts[tid];
614 TheISA::initCPU(src_tc, src_tc->contextId());
615 }
616 }
617
618 // Clear noSquashFromTC.
619 for (int tid = 0; tid < numThreads; ++tid)
620 thread[tid]->noSquashFromTC = false;
621
622 commit.setThreads(thread);
623}
624
625template <class Impl>
626void
627FullO3CPU<Impl>::startup()
628{
629 BaseCPU::startup();
630 for (int tid = 0; tid < numThreads; ++tid)
631 isa[tid]->startup(threadContexts[tid]);
632
633 fetch.startupStage();
634 decode.startupStage();
635 iew.startupStage();
636 rename.startupStage();
637 commit.startupStage();
638}
639
640template <class Impl>
641void
642FullO3CPU<Impl>::activateThread(ThreadID tid)
643{
644 list<ThreadID>::iterator isActive =
645 std::find(activeThreads.begin(), activeThreads.end(), tid);
646
647 DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid);
648 assert(!switchedOut());
649
650 if (isActive == activeThreads.end()) {
651 DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n",
652 tid);
653
654 activeThreads.push_back(tid);
655 }
656}
657
658template <class Impl>
659void
660FullO3CPU<Impl>::deactivateThread(ThreadID tid)
661{
662 //Remove From Active List, if Active
663 list<ThreadID>::iterator thread_it =
664 std::find(activeThreads.begin(), activeThreads.end(), tid);
665
666 DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid);
667 assert(!switchedOut());
668
669 if (thread_it != activeThreads.end()) {
670 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
671 tid);
672 activeThreads.erase(thread_it);
673 }
674
675 fetch.deactivateThread(tid);
676 commit.deactivateThread(tid);
677}
678
679template <class Impl>
680Counter
681FullO3CPU<Impl>::totalInsts() const
682{
683 Counter total(0);
684
685 ThreadID size = thread.size();
686 for (ThreadID i = 0; i < size; i++)
687 total += thread[i]->numInst;
688
689 return total;
690}
691
692template <class Impl>
693Counter
694FullO3CPU<Impl>::totalOps() const
695{
696 Counter total(0);
697
698 ThreadID size = thread.size();
699 for (ThreadID i = 0; i < size; i++)
700 total += thread[i]->numOp;
701
702 return total;
703}
704
705template <class Impl>
706void
707FullO3CPU<Impl>::activateContext(ThreadID tid)
708{
709 assert(!switchedOut());
710
711 // Needs to set each stage to running as well.
712 activateThread(tid);
713
714 // We don't want to wake the CPU if it is drained. In that case,
715 // we just want to flag the thread as active and schedule the tick
716 // event from drainResume() instead.
717 if (drainState() == DrainState::Drained)
718 return;
719
720 // If we are time 0 or if the last activation time is in the past,
721 // schedule the next tick and wake up the fetch unit
722 if (lastActivatedCycle == 0 || lastActivatedCycle < curTick()) {
723 scheduleTickEvent(Cycles(0));
724
725 // Be sure to signal that there's some activity so the CPU doesn't
726 // deschedule itself.
727 activityRec.activity();
728 fetch.wakeFromQuiesce();
729
730 Cycles cycles(curCycle() - lastRunningCycle);
731 // @todo: This is an oddity that is only here to match the stats
732 if (cycles != 0)
733 --cycles;
734 quiesceCycles += cycles;
735
736 lastActivatedCycle = curTick();
737
738 _status = Running;
739
740 BaseCPU::activateContext(tid);
741 }
742}
743
744template <class Impl>
745void
746FullO3CPU<Impl>::suspendContext(ThreadID tid)
747{
748 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
749 assert(!switchedOut());
750
751 deactivateThread(tid);
752
753 // If this was the last thread then unschedule the tick event.
754 if (activeThreads.size() == 0) {
755 unscheduleTickEvent();
756 lastRunningCycle = curCycle();
757 _status = Idle;
758 }
759
760 DPRINTF(Quiesce, "Suspending Context\n");
761
762 BaseCPU::suspendContext(tid);
763}
764
765template <class Impl>
766void
767FullO3CPU<Impl>::haltContext(ThreadID tid)
768{
769 //For now, this is the same as deallocate
770 DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
771 assert(!switchedOut());
772
773 deactivateThread(tid);
774 removeThread(tid);
775}
776
777template <class Impl>
778void
779FullO3CPU<Impl>::insertThread(ThreadID tid)
780{
781 DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
782 // Will change now that the PC and thread state is internal to the CPU
783 // and not in the ThreadContext.
784 ThreadContext *src_tc;
785 if (FullSystem)
786 src_tc = system->threadContexts[tid];
787 else
788 src_tc = tcBase(tid);
789
790 //Bind Int Regs to Rename Map
791
792 for (RegId reg_id(IntRegClass, 0); reg_id.regIdx < TheISA::NumIntRegs;
793 reg_id.regIdx++) {
794 PhysRegIndex phys_reg = freeList.getIntReg();
795 renameMap[tid].setEntry(reg_id, phys_reg);
796 scoreboard.setReg(phys_reg);
797 }
798
799 //Bind Float Regs to Rename Map
800 for (RegId reg_id(FloatRegClass, 0); reg_id.regIdx < TheISA::NumFloatRegs;
801 reg_id.regIdx++) {
802 PhysRegIndex phys_reg = freeList.getFloatReg();
803 renameMap[tid].setEntry(reg_id, phys_reg);
804 scoreboard.setReg(phys_reg);
805 }
806
807 //Bind condition-code Regs to Rename Map
808 for (RegId reg_id(CCRegClass, 0); reg_id.regIdx < TheISA::NumCCRegs;
809 reg_id.regIdx++) {
810 PhysRegIndex phys_reg = freeList.getCCReg();
811 renameMap[tid].setEntry(reg_id, phys_reg);
812 scoreboard.setReg(phys_reg);
813 }
814
815 //Copy Thread Data Into RegFile
816 //this->copyFromTC(tid);
817
818 //Set PC/NPC/NNPC
819 pcState(src_tc->pcState(), tid);
820
821 src_tc->setStatus(ThreadContext::Active);
822
823 activateContext(tid);
824
825 //Reset ROB/IQ/LSQ Entries
826 commit.rob->resetEntries();
827 iew.resetEntries();
828}
829
830template <class Impl>
831void
832FullO3CPU<Impl>::removeThread(ThreadID tid)
833{
834 DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
835
836 // Copy Thread Data From RegFile
837 // If thread is suspended, it might be re-allocated
838 // this->copyToTC(tid);
839
840
841 // @todo: 2-27-2008: Fix how we free up rename mappings
842 // here to alleviate the case for double-freeing registers
843 // in SMT workloads.
844
845 // Unbind Int Regs from Rename Map
846 for (RegId reg_id(IntRegClass, 0); reg_id.regIdx < TheISA::NumIntRegs;
847 reg_id.regIdx++) {
848 PhysRegIndex phys_reg = renameMap[tid].lookup(reg_id);
849 scoreboard.unsetReg(phys_reg);
850 freeList.addReg(phys_reg);
851 }
852
853 // Unbind Float Regs from Rename Map
854 for (RegId reg_id(FloatRegClass, 0); reg_id.regIdx < TheISA::NumFloatRegs;
855 reg_id.regIdx++) {
856 PhysRegIndex phys_reg = renameMap[tid].lookup(reg_id);
857 scoreboard.unsetReg(phys_reg);
858 freeList.addReg(phys_reg);
859 }
860
861 // Unbind condition-code Regs from Rename Map
862 for (RegId reg_id(CCRegClass, 0); reg_id.regIdx < TheISA::NumCCRegs;
863 reg_id.regIdx++) {
864 PhysRegIndex phys_reg = renameMap[tid].lookup(reg_id);
865 scoreboard.unsetReg(phys_reg);
866 freeList.addReg(phys_reg);
867 }
868
869 // Squash Throughout Pipeline
870 DynInstPtr inst = commit.rob->readHeadInst(tid);
871 InstSeqNum squash_seq_num = inst->seqNum;
872 fetch.squash(0, squash_seq_num, inst, tid);
873 decode.squash(tid);
874 rename.squash(squash_seq_num, tid);
875 iew.squash(tid);
876 iew.ldstQueue.squash(squash_seq_num, tid);
877 commit.rob->squash(squash_seq_num, tid);
878
879
880 assert(iew.instQueue.getCount(tid) == 0);
881 assert(iew.ldstQueue.getCount(tid) == 0);
882
883 // Reset ROB/IQ/LSQ Entries
884
885 // Commented out for now. This should be possible to do by
886 // telling all the pipeline stages to drain first, and then
887 // checking until the drain completes. Once the pipeline is
888 // drained, call resetEntries(). - 10-09-06 ktlim
889/*
890 if (activeThreads.size() >= 1) {
891 commit.rob->resetEntries();
892 iew.resetEntries();
893 }
894*/
895}
896
897template <class Impl>
898Fault
899FullO3CPU<Impl>::hwrei(ThreadID tid)
900{
901#if THE_ISA == ALPHA_ISA
902 // Need to clear the lock flag upon returning from an interrupt.
903 this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
904
905 this->thread[tid]->kernelStats->hwrei();
906
907 // FIXME: XXX check for interrupts? XXX
908#endif
909 return NoFault;
910}
911
912template <class Impl>
913bool
914FullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid)
915{
916#if THE_ISA == ALPHA_ISA
917 if (this->thread[tid]->kernelStats)
918 this->thread[tid]->kernelStats->callpal(palFunc,
919 this->threadContexts[tid]);
920
921 switch (palFunc) {
922 case PAL::halt:
923 halt();
924 if (--System::numSystemsRunning == 0)
925 exitSimLoop("all cpus halted");
926 break;
927
928 case PAL::bpt:
929 case PAL::bugchk:
930 if (this->system->breakpoint())
931 return false;
932 break;
933 }
934#endif
935 return true;
936}
937
938template <class Impl>
939Fault
940FullO3CPU<Impl>::getInterrupts()
941{
942 // Check if there are any outstanding interrupts
943 return this->interrupts[0]->getInterrupt(this->threadContexts[0]);
944}
945
946template <class Impl>
947void
948FullO3CPU<Impl>::processInterrupts(const Fault &interrupt)
949{
950 // Check for interrupts here. For now can copy the code that
951 // exists within isa_fullsys_traits.hh. Also assume that thread 0
952 // is the one that handles the interrupts.
953 // @todo: Possibly consolidate the interrupt checking code.
954 // @todo: Allow other threads to handle interrupts.
955
956 assert(interrupt != NoFault);
957 this->interrupts[0]->updateIntrInfo(this->threadContexts[0]);
958
959 DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
960 this->trap(interrupt, 0, nullptr);
961}
962
963template <class Impl>
964void
965FullO3CPU<Impl>::trap(const Fault &fault, ThreadID tid,
966 const StaticInstPtr &inst)
967{
968 // Pass the thread's TC into the invoke method.
969 fault->invoke(this->threadContexts[tid], inst);
970}
971
972template <class Impl>
973void
974FullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid, Fault *fault)
975{
976 DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid);
977
978 DPRINTF(Activity,"Activity: syscall() called.\n");
979
980 // Temporarily increase this by one to account for the syscall
981 // instruction.
982 ++(this->thread[tid]->funcExeInst);
983
984 // Execute the actual syscall.
985 this->thread[tid]->syscall(callnum, fault);
986
987 // Decrease funcExeInst by one as the normal commit will handle
988 // incrementing it.
989 --(this->thread[tid]->funcExeInst);
990}
991
992template <class Impl>
993void
994FullO3CPU<Impl>::serializeThread(CheckpointOut &cp, ThreadID tid) const
995{
996 thread[tid]->serialize(cp);
997}
998
999template <class Impl>
1000void
1001FullO3CPU<Impl>::unserializeThread(CheckpointIn &cp, ThreadID tid)
1002{
1003 thread[tid]->unserialize(cp);
1004}
1005
1006template <class Impl>
1007DrainState
1008FullO3CPU<Impl>::drain()
1009{
1010 // If the CPU isn't doing anything, then return immediately.
1011 if (switchedOut())
1012 return DrainState::Drained;
1013
1014 DPRINTF(Drain, "Draining...\n");
1015
1016 // We only need to signal a drain to the commit stage as this
1017 // initiates squashing controls the draining. Once the commit
1018 // stage commits an instruction where it is safe to stop, it'll
1019 // squash the rest of the instructions in the pipeline and force
1020 // the fetch stage to stall. The pipeline will be drained once all
1021 // in-flight instructions have retired.
1022 commit.drain();
1023
1024 // Wake the CPU and record activity so everything can drain out if
1025 // the CPU was not able to immediately drain.
1026 if (!isDrained()) {
1027 wakeCPU();
1028 activityRec.activity();
1029
1030 DPRINTF(Drain, "CPU not drained\n");
1031
1032 return DrainState::Draining;
1033 } else {
1034 DPRINTF(Drain, "CPU is already drained\n");
1035 if (tickEvent.scheduled())
1036 deschedule(tickEvent);
1037
1038 // Flush out any old data from the time buffers. In
1039 // particular, there might be some data in flight from the
1040 // fetch stage that isn't visible in any of the CPU buffers we
1041 // test in isDrained().
1042 for (int i = 0; i < timeBuffer.getSize(); ++i) {
1043 timeBuffer.advance();
1044 fetchQueue.advance();
1045 decodeQueue.advance();
1046 renameQueue.advance();
1047 iewQueue.advance();
1048 }
1049
1050 drainSanityCheck();
1051 return DrainState::Drained;
1052 }
1053}
1054
1055template <class Impl>
1056bool
1057FullO3CPU<Impl>::tryDrain()
1058{
1059 if (drainState() != DrainState::Draining || !isDrained())
1060 return false;
1061
1062 if (tickEvent.scheduled())
1063 deschedule(tickEvent);
1064
1065 DPRINTF(Drain, "CPU done draining, processing drain event\n");
1066 signalDrainDone();
1067
1068 return true;
1069}
1070
1071template <class Impl>
1072void
1073FullO3CPU<Impl>::drainSanityCheck() const
1074{
1075 assert(isDrained());
1076 fetch.drainSanityCheck();
1077 decode.drainSanityCheck();
1078 rename.drainSanityCheck();
1079 iew.drainSanityCheck();
1080 commit.drainSanityCheck();
1081}
1082
1083template <class Impl>
1084bool
1085FullO3CPU<Impl>::isDrained() const
1086{
1087 bool drained(true);
1088
1089 if (!instList.empty() || !removeList.empty()) {
1090 DPRINTF(Drain, "Main CPU structures not drained.\n");
1091 drained = false;
1092 }
1093
1094 if (!fetch.isDrained()) {
1095 DPRINTF(Drain, "Fetch not drained.\n");
1096 drained = false;
1097 }
1098
1099 if (!decode.isDrained()) {
1100 DPRINTF(Drain, "Decode not drained.\n");
1101 drained = false;
1102 }
1103
1104 if (!rename.isDrained()) {
1105 DPRINTF(Drain, "Rename not drained.\n");
1106 drained = false;
1107 }
1108
1109 if (!iew.isDrained()) {
1110 DPRINTF(Drain, "IEW not drained.\n");
1111 drained = false;
1112 }
1113
1114 if (!commit.isDrained()) {
1115 DPRINTF(Drain, "Commit not drained.\n");
1116 drained = false;
1117 }
1118
1119 return drained;
1120}
1121
1122template <class Impl>
1123void
1124FullO3CPU<Impl>::commitDrained(ThreadID tid)
1125{
1126 fetch.drainStall(tid);
1127}
1128
1129template <class Impl>
1130void
1131FullO3CPU<Impl>::drainResume()
1132{
1133 if (switchedOut())
1134 return;
1135
1136 DPRINTF(Drain, "Resuming...\n");
1137 verifyMemoryMode();
1138
1139 fetch.drainResume();
1140 commit.drainResume();
1141
1142 _status = Idle;
1143 for (ThreadID i = 0; i < thread.size(); i++) {
1144 if (thread[i]->status() == ThreadContext::Active) {
1145 DPRINTF(Drain, "Activating thread: %i\n", i);
1146 activateThread(i);
1147 _status = Running;
1148 }
1149 }
1150
1151 assert(!tickEvent.scheduled());
1152 if (_status == Running)
1153 schedule(tickEvent, nextCycle());
1154}
1155
1156template <class Impl>
1157void
1158FullO3CPU<Impl>::switchOut()
1159{
1160 DPRINTF(O3CPU, "Switching out\n");
1161 BaseCPU::switchOut();
1162
1163 activityRec.reset();
1164
1165 _status = SwitchedOut;
1166
1167 if (checker)
1168 checker->switchOut();
1169}
1170
1171template <class Impl>
1172void
1173FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
1174{
1175 BaseCPU::takeOverFrom(oldCPU);
1176
1177 fetch.takeOverFrom();
1178 decode.takeOverFrom();
1179 rename.takeOverFrom();
1180 iew.takeOverFrom();
1181 commit.takeOverFrom();
1182
1183 assert(!tickEvent.scheduled());
1184
1185 FullO3CPU<Impl> *oldO3CPU = dynamic_cast<FullO3CPU<Impl>*>(oldCPU);
1186 if (oldO3CPU)
1187 globalSeqNum = oldO3CPU->globalSeqNum;
1188
1189 lastRunningCycle = curCycle();
1190 _status = Idle;
1191}
1192
1193template <class Impl>
1194void
1195FullO3CPU<Impl>::verifyMemoryMode() const
1196{
1197 if (!system->isTimingMode()) {
1198 fatal("The O3 CPU requires the memory system to be in "
1199 "'timing' mode.\n");
1200 }
1201}
1202
1203template <class Impl>
1204TheISA::MiscReg
1205FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
1206{
1207 return this->isa[tid]->readMiscRegNoEffect(misc_reg);
1208}
1209
1210template <class Impl>
1211TheISA::MiscReg
1212FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
1213{
1214 miscRegfileReads++;
1215 return this->isa[tid]->readMiscReg(misc_reg, tcBase(tid));
1216}
1217
1218template <class Impl>
1219void
1220FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
1221 const TheISA::MiscReg &val, ThreadID tid)
1222{
1223 this->isa[tid]->setMiscRegNoEffect(misc_reg, val);
1224}
1225
1226template <class Impl>
1227void
1228FullO3CPU<Impl>::setMiscReg(int misc_reg,
1229 const TheISA::MiscReg &val, ThreadID tid)
1230{
1231 miscRegfileWrites++;
1232 this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid));
1233}
1234
1235template <class Impl>
1236uint64_t
1237FullO3CPU<Impl>::readIntReg(int reg_idx)
1238{
1239 intRegfileReads++;
1240 return regFile.readIntReg(reg_idx);
1241}
1242
1243template <class Impl>
1244FloatReg
1245FullO3CPU<Impl>::readFloatReg(int reg_idx)
1246{
1247 fpRegfileReads++;
1248 return regFile.readFloatReg(reg_idx);
1249}
1250
1251template <class Impl>
1252FloatRegBits
1253FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
1254{
1255 fpRegfileReads++;
1256 return regFile.readFloatRegBits(reg_idx);
1257}
1258
1259template <class Impl>
1260CCReg
1261FullO3CPU<Impl>::readCCReg(int reg_idx)
1262{
1263 ccRegfileReads++;
1264 return regFile.readCCReg(reg_idx);
1265}
1266
1267template <class Impl>
1268void
1269FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
1270{
1271 intRegfileWrites++;
1272 regFile.setIntReg(reg_idx, val);
1273}
1274
1275template <class Impl>
1276void
1277FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
1278{
1279 fpRegfileWrites++;
1280 regFile.setFloatReg(reg_idx, val);
1281}
1282
1283template <class Impl>
1284void
1285FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
1286{
1287 fpRegfileWrites++;
1288 regFile.setFloatRegBits(reg_idx, val);
1289}
1290
1291template <class Impl>
1292void
1293FullO3CPU<Impl>::setCCReg(int reg_idx, CCReg val)
1294{
1295 ccRegfileWrites++;
1296 regFile.setCCReg(reg_idx, val);
1297}
1298
1299template <class Impl>
1300uint64_t
1301FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1302{
1303 intRegfileReads++;
1304 PhysRegIndex phys_reg = commitRenameMap[tid].lookupInt(reg_idx);
1305
1306 return regFile.readIntReg(phys_reg);
1307}
1308
1309template <class Impl>
1310float
1311FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
1312{
1313 fpRegfileReads++;
1314 PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1315
1316 return regFile.readFloatReg(phys_reg);
1317}
1318
1319template <class Impl>
1320uint64_t
1321FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid)
1322{
1323 fpRegfileReads++;
1324 PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1325
1326 return regFile.readFloatRegBits(phys_reg);
1327}
1328
1329template <class Impl>
1330CCReg
1331FullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid)
1332{
1333 ccRegfileReads++;
1334 PhysRegIndex phys_reg = commitRenameMap[tid].lookupCC(reg_idx);
1335
1336 return regFile.readCCReg(phys_reg);
1337}
1338
1339template <class Impl>
1340void
1341FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
1342{
1343 intRegfileWrites++;
1344 PhysRegIndex phys_reg = commitRenameMap[tid].lookupInt(reg_idx);
1345
1346 regFile.setIntReg(phys_reg, val);
1347}
1348
1349template <class Impl>
1350void
1351FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid)
1352{
1353 fpRegfileWrites++;
1354 PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1355
1356 regFile.setFloatReg(phys_reg, val);
1357}
1358
1359template <class Impl>
1360void
1361FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid)
1362{
1363 fpRegfileWrites++;
1364 PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1365
1366 regFile.setFloatRegBits(phys_reg, val);
1367}
1368
1369template <class Impl>
1370void
1371FullO3CPU<Impl>::setArchCCReg(int reg_idx, CCReg val, ThreadID tid)
1372{
1373 ccRegfileWrites++;
1374 PhysRegIndex phys_reg = commitRenameMap[tid].lookupCC(reg_idx);
1375
1376 regFile.setCCReg(phys_reg, val);
1377}
1378
1379template <class Impl>
1380TheISA::PCState
1381FullO3CPU<Impl>::pcState(ThreadID tid)
1382{
1383 return commit.pcState(tid);
1384}
1385
1386template <class Impl>
1387void
1388FullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid)
1389{
1390 commit.pcState(val, tid);
1391}
1392
1393template <class Impl>
1394Addr
1395FullO3CPU<Impl>::instAddr(ThreadID tid)
1396{
1397 return commit.instAddr(tid);
1398}
1399
1400template <class Impl>
1401Addr
1402FullO3CPU<Impl>::nextInstAddr(ThreadID tid)
1403{
1404 return commit.nextInstAddr(tid);
1405}
1406
1407template <class Impl>
1408MicroPC
1409FullO3CPU<Impl>::microPC(ThreadID tid)
1410{
1411 return commit.microPC(tid);
1412}
1413
1414template <class Impl>
1415void
1416FullO3CPU<Impl>::squashFromTC(ThreadID tid)
1417{
1418 this->thread[tid]->noSquashFromTC = true;
1419 this->commit.generateTCEvent(tid);
1420}
1421
1422template <class Impl>
1423typename FullO3CPU<Impl>::ListIt
1424FullO3CPU<Impl>::addInst(DynInstPtr &inst)
1425{
1426 instList.push_back(inst);
1427
1428 return --(instList.end());
1429}
1430
1431template <class Impl>
1432void
1433FullO3CPU<Impl>::instDone(ThreadID tid, DynInstPtr &inst)
1434{
1435 // Keep an instruction count.
1436 if (!inst->isMicroop() || inst->isLastMicroop()) {
1437 thread[tid]->numInst++;
1438 thread[tid]->numInsts++;
1439 committedInsts[tid]++;
1440 system->totalNumInsts++;
1441
1442 // Check for instruction-count-based events.
1443 comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1444 system->instEventQueue.serviceEvents(system->totalNumInsts);
1445 }
1446 thread[tid]->numOp++;
1447 thread[tid]->numOps++;
1448 committedOps[tid]++;
1449
1450 probeInstCommit(inst->staticInst);
1451}
1452
1453template <class Impl>
1454void
1455FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
1456{
1457 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s "
1458 "[sn:%lli]\n",
1459 inst->threadNumber, inst->pcState(), inst->seqNum);
1460
1461 removeInstsThisCycle = true;
1462
1463 // Remove the front instruction.
1464 removeList.push(inst->getInstListIt());
1465}
1466
1467template <class Impl>
1468void
1469FullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid)
1470{
1471 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1472 " list.\n", tid);
1473
1474 ListIt end_it;
1475
1476 bool rob_empty = false;
1477
1478 if (instList.empty()) {
1479 return;
1480 } else if (rob.isEmpty(tid)) {
1481 DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1482 end_it = instList.begin();
1483 rob_empty = true;
1484 } else {
1485 end_it = (rob.readTailInst(tid))->getInstListIt();
1486 DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1487 }
1488
1489 removeInstsThisCycle = true;
1490
1491 ListIt inst_it = instList.end();
1492
1493 inst_it--;
1494
1495 // Walk through the instruction list, removing any instructions
1496 // that were inserted after the given instruction iterator, end_it.
1497 while (inst_it != end_it) {
1498 assert(!instList.empty());
1499
1500 squashInstIt(inst_it, tid);
1501
1502 inst_it--;
1503 }
1504
1505 // If the ROB was empty, then we actually need to remove the first
1506 // instruction as well.
1507 if (rob_empty) {
1508 squashInstIt(inst_it, tid);
1509 }
1510}
1511
1512template <class Impl>
1513void
1514FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1515{
1516 assert(!instList.empty());
1517
1518 removeInstsThisCycle = true;
1519
1520 ListIt inst_iter = instList.end();
1521
1522 inst_iter--;
1523
1524 DPRINTF(O3CPU, "Deleting instructions from instruction "
1525 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1526 tid, seq_num, (*inst_iter)->seqNum);
1527
1528 while ((*inst_iter)->seqNum > seq_num) {
1529
1530 bool break_loop = (inst_iter == instList.begin());
1531
1532 squashInstIt(inst_iter, tid);
1533
1534 inst_iter--;
1535
1536 if (break_loop)
1537 break;
1538 }
1539}
1540
1541template <class Impl>
1542inline void
1543FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid)
1544{
1545 if ((*instIt)->threadNumber == tid) {
1546 DPRINTF(O3CPU, "Squashing instruction, "
1547 "[tid:%i] [sn:%lli] PC %s\n",
1548 (*instIt)->threadNumber,
1549 (*instIt)->seqNum,
1550 (*instIt)->pcState());
1551
1552 // Mark it as squashed.
1553 (*instIt)->setSquashed();
1554
1555 // @todo: Formulate a consistent method for deleting
1556 // instructions from the instruction list
1557 // Remove the instruction from the list.
1558 removeList.push(instIt);
1559 }
1560}
1561
1562template <class Impl>
1563void
1564FullO3CPU<Impl>::cleanUpRemovedInsts()
1565{
1566 while (!removeList.empty()) {
1567 DPRINTF(O3CPU, "Removing instruction, "
1568 "[tid:%i] [sn:%lli] PC %s\n",
1569 (*removeList.front())->threadNumber,
1570 (*removeList.front())->seqNum,
1571 (*removeList.front())->pcState());
1572
1573 instList.erase(removeList.front());
1574
1575 removeList.pop();
1576 }
1577
1578 removeInstsThisCycle = false;
1579}
1580/*
1581template <class Impl>
1582void
1583FullO3CPU<Impl>::removeAllInsts()
1584{
1585 instList.clear();
1586}
1587*/
1588template <class Impl>
1589void
1590FullO3CPU<Impl>::dumpInsts()
1591{
1592 int num = 0;
1593
1594 ListIt inst_list_it = instList.begin();
1595
1596 cprintf("Dumping Instruction List\n");
1597
1598 while (inst_list_it != instList.end()) {
1599 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1600 "Squashed:%i\n\n",
1601 num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber,
1602 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1603 (*inst_list_it)->isSquashed());
1604 inst_list_it++;
1605 ++num;
1606 }
1607}
1608/*
1609template <class Impl>
1610void
1611FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
1612{
1613 iew.wakeDependents(inst);
1614}
1615*/
1616template <class Impl>
1617void
1618FullO3CPU<Impl>::wakeCPU()
1619{
1620 if (activityRec.active() || tickEvent.scheduled()) {
1621 DPRINTF(Activity, "CPU already running.\n");
1622 return;
1623 }
1624
1625 DPRINTF(Activity, "Waking up CPU\n");
1626
1627 Cycles cycles(curCycle() - lastRunningCycle);
1628 // @todo: This is an oddity that is only here to match the stats
1629 if (cycles > 1) {
1630 --cycles;
1631 idleCycles += cycles;
1632 numCycles += cycles;
1633 ppCycles->notify(cycles);
1634 }
1635
1636 schedule(tickEvent, clockEdge());
1637}
1638
1639template <class Impl>
1640void
1641FullO3CPU<Impl>::wakeup(ThreadID tid)
1642{
1643 if (this->thread[tid]->status() != ThreadContext::Suspended)
1644 return;
1645
1646 this->wakeCPU();
1647
1648 DPRINTF(Quiesce, "Suspended Processor woken\n");
1649 this->threadContexts[tid]->activate();
1650}
1651
1652template <class Impl>
1653ThreadID
1654FullO3CPU<Impl>::getFreeTid()
1655{
1656 for (ThreadID tid = 0; tid < numThreads; tid++) {
1657 if (!tids[tid]) {
1658 tids[tid] = true;
1659 return tid;
1660 }
1661 }
1662
1663 return InvalidThreadID;
1664}
1665
1666template <class Impl>
1667void
1668FullO3CPU<Impl>::updateThreadPriority()
1669{
1670 if (activeThreads.size() > 1) {
1671 //DEFAULT TO ROUND ROBIN SCHEME
1672 //e.g. Move highest priority to end of thread list
1673 list<ThreadID>::iterator list_begin = activeThreads.begin();
1674
1675 unsigned high_thread = *list_begin;
1676
1677 activeThreads.erase(list_begin);
1678
1679 activeThreads.push_back(high_thread);
1680 }
1681}
1682
1683// Forward declaration of FullO3CPU.
1684template class FullO3CPU<O3CPUImpl>;