1/*
2 * Copyright (c) 2011-2012, 2014 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * Copyright (c) 2011 Regents of the University of California
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Kevin Lim
43 * Korey Sewell
44 * Rick Strong
45 */
46
47#include "arch/kernel_stats.hh"
48#include "config/the_isa.hh"
49#include "cpu/checker/cpu.hh"
50#include "cpu/checker/thread_context.hh"
51#include "cpu/o3/cpu.hh"
52#include "cpu/o3/isa_specific.hh"
53#include "cpu/o3/thread_context.hh"
54#include "cpu/activity.hh"
55#include "cpu/quiesce_event.hh"
56#include "cpu/simple_thread.hh"
57#include "cpu/thread_context.hh"
58#include "debug/Activity.hh"
59#include "debug/Drain.hh"
60#include "debug/O3CPU.hh"
61#include "debug/Quiesce.hh"
62#include "enums/MemoryMode.hh"
63#include "sim/core.hh"
64#include "sim/full_system.hh"
65#include "sim/process.hh"
66#include "sim/stat_control.hh"
67#include "sim/system.hh"
68
69#if THE_ISA == ALPHA_ISA
70#include "arch/alpha/osfpal.hh"
71#include "debug/Activity.hh"
72#endif
73
74struct BaseCPUParams;
75
76using namespace TheISA;
77using namespace std;
78
79BaseO3CPU::BaseO3CPU(BaseCPUParams *params)
80 : BaseCPU(params)
81{
82}
83
84void
85BaseO3CPU::regStats()
86{
87 BaseCPU::regStats();
88}
89
90template<class Impl>
91bool
92FullO3CPU<Impl>::IcachePort::recvTimingResp(PacketPtr pkt)
93{
94 DPRINTF(O3CPU, "Fetch unit received timing\n");
95 // We shouldn't ever get a cacheable block in ownership state
96 assert(pkt->req->isUncacheable() ||
97 !(pkt->memInhibitAsserted() && !pkt->sharedAsserted()));
98 fetch->processCacheCompletion(pkt);
99
100 return true;
101}
102
103template<class Impl>
104void
105FullO3CPU<Impl>::IcachePort::recvReqRetry()
106{
107 fetch->recvReqRetry();
108}
109
110template <class Impl>
111bool
112FullO3CPU<Impl>::DcachePort::recvTimingResp(PacketPtr pkt)
113{
114 return lsq->recvTimingResp(pkt);
115}
116
117template <class Impl>
118void
119FullO3CPU<Impl>::DcachePort::recvTimingSnoopReq(PacketPtr pkt)
120{
121 // X86 ISA: Snooping an invalidation for monitor/mwait
122 if(cpu->getCpuAddrMonitor()->doMonitor(pkt)) {
123 cpu->wakeup();
124 }
125 lsq->recvTimingSnoopReq(pkt);
126}
127
128template <class Impl>
129void
130FullO3CPU<Impl>::DcachePort::recvReqRetry()
131{
132 lsq->recvReqRetry();
133}
134
135template <class Impl>
136FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
137 : Event(CPU_Tick_Pri), cpu(c)
138{
139}
140
141template <class Impl>
142void
143FullO3CPU<Impl>::TickEvent::process()
144{
145 cpu->tick();
146}
147
148template <class Impl>
149const char *
150FullO3CPU<Impl>::TickEvent::description() const
151{
152 return "FullO3CPU tick";
153}
154
155template <class Impl>
156FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
157 : BaseO3CPU(params),
158 itb(params->itb),
159 dtb(params->dtb),
160 tickEvent(this),
161#ifndef NDEBUG
162 instcount(0),
163#endif
164 removeInstsThisCycle(false),
165 fetch(this, params),
166 decode(this, params),
167 rename(this, params),
168 iew(this, params),
169 commit(this, params),
170
171 regFile(params->numPhysIntRegs,
172 params->numPhysFloatRegs,
173 params->numPhysCCRegs,
174 params->numPhysVectorRegs),
175
176 freeList(name() + ".freelist", &regFile),
177
178 rob(this, params),
179
180 scoreboard(name() + ".scoreboard",
181 regFile.totalNumPhysRegs(), TheISA::NumMiscRegs,
182 TheISA::ZeroReg, TheISA::ZeroReg),
183
184 isa(numThreads, NULL),
185
186 icachePort(&fetch, this),
187 dcachePort(&iew.ldstQueue, this),
188
189 timeBuffer(params->backComSize, params->forwardComSize),
190 fetchQueue(params->backComSize, params->forwardComSize),
191 decodeQueue(params->backComSize, params->forwardComSize),
192 renameQueue(params->backComSize, params->forwardComSize),
193 iewQueue(params->backComSize, params->forwardComSize),
194 activityRec(name(), NumStages,
195 params->backComSize + params->forwardComSize,
196 params->activity),
197
198 globalSeqNum(1),
199 system(params->system),
200 lastRunningCycle(curCycle())
201{
202 if (!params->switched_out) {
203 _status = Running;
204 } else {
205 _status = SwitchedOut;
206 }
207
208 if (params->checker) {
209 BaseCPU *temp_checker = params->checker;
210 checker = dynamic_cast<Checker<Impl> *>(temp_checker);
211 checker->setIcachePort(&icachePort);
212 checker->setSystem(params->system);
213 } else {
214 checker = NULL;
215 }
216
217 if (!FullSystem) {
218 thread.resize(numThreads);
219 tids.resize(numThreads);
220 }
221
222 // The stages also need their CPU pointer setup. However this
223 // must be done at the upper level CPU because they have pointers
224 // to the upper level CPU, and not this FullO3CPU.
225
226 // Set up Pointers to the activeThreads list for each stage
227 fetch.setActiveThreads(&activeThreads);
228 decode.setActiveThreads(&activeThreads);
229 rename.setActiveThreads(&activeThreads);
230 iew.setActiveThreads(&activeThreads);
231 commit.setActiveThreads(&activeThreads);
232
233 // Give each of the stages the time buffer they will use.
234 fetch.setTimeBuffer(&timeBuffer);
235 decode.setTimeBuffer(&timeBuffer);
236 rename.setTimeBuffer(&timeBuffer);
237 iew.setTimeBuffer(&timeBuffer);
238 commit.setTimeBuffer(&timeBuffer);
239
240 // Also setup each of the stages' queues.
241 fetch.setFetchQueue(&fetchQueue);
242 decode.setFetchQueue(&fetchQueue);
243 commit.setFetchQueue(&fetchQueue);
244 decode.setDecodeQueue(&decodeQueue);
245 rename.setDecodeQueue(&decodeQueue);
246 rename.setRenameQueue(&renameQueue);
247 iew.setRenameQueue(&renameQueue);
248 iew.setIEWQueue(&iewQueue);
249 commit.setIEWQueue(&iewQueue);
250 commit.setRenameQueue(&renameQueue);
251
252 commit.setIEWStage(&iew);
253 rename.setIEWStage(&iew);
254 rename.setCommitStage(&commit);
255
256 ThreadID active_threads;
257 if (FullSystem) {
258 active_threads = 1;
259 } else {
260 active_threads = params->workload.size();
261
262 if (active_threads > Impl::MaxThreads) {
263 panic("Workload Size too large. Increase the 'MaxThreads' "
264 "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) "
265 "or edit your workload size.");
266 }
267 }
268
269 //Make Sure That this a Valid Architeture
270 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs);
271 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
272 assert(params->numPhysCCRegs >= numThreads * TheISA::NumCCRegs);
273 assert(params->numPhysVectorRegs >= numThreads * TheISA::NumVectorRegs);
274
275 rename.setScoreboard(&scoreboard);
276 iew.setScoreboard(&scoreboard);
277
278 // Setup the rename map for whichever stages need it.
279 for (ThreadID tid = 0; tid < numThreads; tid++) {
280 isa[tid] = params->isa[tid];
281
282 // Only Alpha has an FP zero register, so for other ISAs we
283 // use an invalid FP register index to avoid special treatment
284 // of any valid FP reg.
285 RegIndex invalidFPReg = TheISA::NumFloatRegs + 1;
286 RegIndex fpZeroReg =
287 (THE_ISA == ALPHA_ISA) ? TheISA::ZeroReg : invalidFPReg;
288
289 commitRenameMap[tid].init(&regFile, TheISA::ZeroReg, fpZeroReg,
290 &freeList);
291
292 renameMap[tid].init(&regFile, TheISA::ZeroReg, fpZeroReg,
293 &freeList);
294 }
295
296 // Initialize rename map to assign physical registers to the
297 // architectural registers for active threads only.
298 for (ThreadID tid = 0; tid < active_threads; tid++) {
299 for (RegIndex ridx = 0; ridx < TheISA::NumIntRegs; ++ridx) {
300 // Note that we can't use the rename() method because we don't
301 // want special treatment for the zero register at this point
302 PhysRegIndex phys_reg = freeList.getIntReg();
303 renameMap[tid].setIntEntry(ridx, phys_reg);
304 commitRenameMap[tid].setIntEntry(ridx, phys_reg);
305 }
306
307 for (RegIndex ridx = 0; ridx < TheISA::NumFloatRegs; ++ridx) {
308 PhysRegIndex phys_reg = freeList.getFloatReg();
309 renameMap[tid].setFloatEntry(ridx, phys_reg);
310 commitRenameMap[tid].setFloatEntry(ridx, phys_reg);
311 }
312
313 for (RegIndex ridx = 0; ridx < TheISA::NumCCRegs; ++ridx) {
314 PhysRegIndex phys_reg = freeList.getCCReg();
315 renameMap[tid].setCCEntry(ridx, phys_reg);
316 commitRenameMap[tid].setCCEntry(ridx, phys_reg);
317 }
318
319 for (RegIndex ridx = 0; ridx < TheISA::NumVectorRegs; ++ridx) {
320 PhysRegIndex phys_reg = freeList.getVectorReg();
321 renameMap[tid].setVectorEntry(ridx, phys_reg);
322 commitRenameMap[tid].setVectorEntry(ridx, phys_reg);
323 }
324 }
325
326 rename.setRenameMap(renameMap);
327 commit.setRenameMap(commitRenameMap);
328 rename.setFreeList(&freeList);
329
330 // Setup the ROB for whichever stages need it.
331 commit.setROB(&rob);
332
333 lastActivatedCycle = 0;
334#if 0
335 // Give renameMap & rename stage access to the freeList;
336 for (ThreadID tid = 0; tid < numThreads; tid++)
337 globalSeqNum[tid] = 1;
338#endif
339
340 DPRINTF(O3CPU, "Creating O3CPU object.\n");
341
342 // Setup any thread state.
343 this->thread.resize(this->numThreads);
344
345 for (ThreadID tid = 0; tid < this->numThreads; ++tid) {
346 if (FullSystem) {
347 // SMT is not supported in FS mode yet.
348 assert(this->numThreads == 1);
349 this->thread[tid] = new Thread(this, 0, NULL);
350 } else {
351 if (tid < params->workload.size()) {
352 DPRINTF(O3CPU, "Workload[%i] process is %#x",
353 tid, this->thread[tid]);
354 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
355 (typename Impl::O3CPU *)(this),
356 tid, params->workload[tid]);
357
358 //usedTids[tid] = true;
359 //threadMap[tid] = tid;
360 } else {
361 //Allocate Empty thread so M5 can use later
362 //when scheduling threads to CPU
363 Process* dummy_proc = NULL;
364
365 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
366 (typename Impl::O3CPU *)(this),
367 tid, dummy_proc);
368 //usedTids[tid] = false;
369 }
370 }
371
372 ThreadContext *tc;
373
374 // Setup the TC that will serve as the interface to the threads/CPU.
375 O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>;
376
377 tc = o3_tc;
378
379 // If we're using a checker, then the TC should be the
380 // CheckerThreadContext.
381 if (params->checker) {
382 tc = new CheckerThreadContext<O3ThreadContext<Impl> >(
383 o3_tc, this->checker);
384 }
385
386 o3_tc->cpu = (typename Impl::O3CPU *)(this);
387 assert(o3_tc->cpu);
388 o3_tc->thread = this->thread[tid];
389
390 if (FullSystem) {
391 // Setup quiesce event.
392 this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
393 }
394 // Give the thread the TC.
395 this->thread[tid]->tc = tc;
396
397 // Add the TC to the CPU's list of TC's.
398 this->threadContexts.push_back(tc);
399 }
400
401 // FullO3CPU always requires an interrupt controller.
402 if (!params->switched_out && !interrupts) {
403 fatal("FullO3CPU %s has no interrupt controller.\n"
404 "Ensure createInterruptController() is called.\n", name());
405 }
406
407 for (ThreadID tid = 0; tid < this->numThreads; tid++)
408 this->thread[tid]->setFuncExeInst(0);
409}
410
411template <class Impl>
412FullO3CPU<Impl>::~FullO3CPU()
413{
414}
415
416template <class Impl>
417void
418FullO3CPU<Impl>::regProbePoints()
419{
420 BaseCPU::regProbePoints();
421
422 ppInstAccessComplete = new ProbePointArg<PacketPtr>(getProbeManager(), "InstAccessComplete");
423 ppDataAccessComplete = new ProbePointArg<std::pair<DynInstPtr, PacketPtr> >(getProbeManager(), "DataAccessComplete");
424
425 fetch.regProbePoints();
426 iew.regProbePoints();
427 commit.regProbePoints();
428}
429
430template <class Impl>
431void
432FullO3CPU<Impl>::regStats()
433{
434 BaseO3CPU::regStats();
435
436 // Register any of the O3CPU's stats here.
437 timesIdled
438 .name(name() + ".timesIdled")
439 .desc("Number of times that the entire CPU went into an idle state and"
440 " unscheduled itself")
441 .prereq(timesIdled);
442
443 idleCycles
444 .name(name() + ".idleCycles")
445 .desc("Total number of cycles that the CPU has spent unscheduled due "
446 "to idling")
447 .prereq(idleCycles);
448
449 quiesceCycles
450 .name(name() + ".quiesceCycles")
451 .desc("Total number of cycles that CPU has spent quiesced or waiting "
452 "for an interrupt")
453 .prereq(quiesceCycles);
454
455 // Number of Instructions simulated
456 // --------------------------------
457 // Should probably be in Base CPU but need templated
458 // MaxThreads so put in here instead
459 committedInsts
460 .init(numThreads)
461 .name(name() + ".committedInsts")
462 .desc("Number of Instructions Simulated")
463 .flags(Stats::total);
464
465 committedOps
466 .init(numThreads)
467 .name(name() + ".committedOps")
468 .desc("Number of Ops (including micro ops) Simulated")
469 .flags(Stats::total);
470
471 cpi
472 .name(name() + ".cpi")
473 .desc("CPI: Cycles Per Instruction")
474 .precision(6);
475 cpi = numCycles / committedInsts;
476
477 totalCpi
478 .name(name() + ".cpi_total")
479 .desc("CPI: Total CPI of All Threads")
480 .precision(6);
481 totalCpi = numCycles / sum(committedInsts);
482
483 ipc
484 .name(name() + ".ipc")
485 .desc("IPC: Instructions Per Cycle")
486 .precision(6);
487 ipc = committedInsts / numCycles;
488
489 totalIpc
490 .name(name() + ".ipc_total")
491 .desc("IPC: Total IPC of All Threads")
492 .precision(6);
493 totalIpc = sum(committedInsts) / numCycles;
494
495 this->fetch.regStats();
496 this->decode.regStats();
497 this->rename.regStats();
498 this->iew.regStats();
499 this->commit.regStats();
500 this->rob.regStats();
501
502 intRegfileReads
503 .name(name() + ".int_regfile_reads")
504 .desc("number of integer regfile reads")
505 .prereq(intRegfileReads);
506
507 intRegfileWrites
508 .name(name() + ".int_regfile_writes")
509 .desc("number of integer regfile writes")
510 .prereq(intRegfileWrites);
511
512 fpRegfileReads
513 .name(name() + ".fp_regfile_reads")
514 .desc("number of floating regfile reads")
515 .prereq(fpRegfileReads);
516
517 fpRegfileWrites
518 .name(name() + ".fp_regfile_writes")
519 .desc("number of floating regfile writes")
520 .prereq(fpRegfileWrites);
521
522 ccRegfileReads
523 .name(name() + ".cc_regfile_reads")
524 .desc("number of cc regfile reads")
525 .prereq(ccRegfileReads);
526
527 ccRegfileWrites
528 .name(name() + ".cc_regfile_writes")
529 .desc("number of cc regfile writes")
530 .prereq(ccRegfileWrites);
531
532 vectorRegfileReads
533 .name(name() + ".vector_regfile_reads")
534 .desc("number of vector regfile reads")
535 .prereq(vectorRegfileReads);
536
537 vectorRegfileWrites
538 .name(name() + ".vector_regfile_writes")
539 .desc("number of vector regfile writes")
540 .prereq(vectorRegfileWrites);
541
542 miscRegfileReads
543 .name(name() + ".misc_regfile_reads")
544 .desc("number of misc regfile reads")
545 .prereq(miscRegfileReads);
546
547 miscRegfileWrites
548 .name(name() + ".misc_regfile_writes")
549 .desc("number of misc regfile writes")
550 .prereq(miscRegfileWrites);
551}
552
553template <class Impl>
554void
555FullO3CPU<Impl>::tick()
556{
557 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
558 assert(!switchedOut());
559 assert(drainState() != DrainState::Drained);
560
561 ++numCycles;
562 ppCycles->notify(1);
563
564// activity = false;
565
566 //Tick each of the stages
567 fetch.tick();
568
569 decode.tick();
570
571 rename.tick();
572
573 iew.tick();
574
575 commit.tick();
576
577 // Now advance the time buffers
578 timeBuffer.advance();
579
580 fetchQueue.advance();
581 decodeQueue.advance();
582 renameQueue.advance();
583 iewQueue.advance();
584
585 activityRec.advance();
586
587 if (removeInstsThisCycle) {
588 cleanUpRemovedInsts();
589 }
590
591 if (!tickEvent.scheduled()) {
592 if (_status == SwitchedOut) {
593 DPRINTF(O3CPU, "Switched out!\n");
594 // increment stat
595 lastRunningCycle = curCycle();
596 } else if (!activityRec.active() || _status == Idle) {
597 DPRINTF(O3CPU, "Idle!\n");
598 lastRunningCycle = curCycle();
599 timesIdled++;
600 } else {
601 schedule(tickEvent, clockEdge(Cycles(1)));
602 DPRINTF(O3CPU, "Scheduling next tick!\n");
603 }
604 }
605
606 if (!FullSystem)
607 updateThreadPriority();
608
609 tryDrain();
610}
611
612template <class Impl>
613void
614FullO3CPU<Impl>::init()
615{
616 BaseCPU::init();
617
618 for (ThreadID tid = 0; tid < numThreads; ++tid) {
619 // Set noSquashFromTC so that the CPU doesn't squash when initially
620 // setting up registers.
621 thread[tid]->noSquashFromTC = true;
622 // Initialise the ThreadContext's memory proxies
623 thread[tid]->initMemProxies(thread[tid]->getTC());
624 }
625
626 if (FullSystem && !params()->switched_out) {
627 for (ThreadID tid = 0; tid < numThreads; tid++) {
628 ThreadContext *src_tc = threadContexts[tid];
629 TheISA::initCPU(src_tc, src_tc->contextId());
630 }
631 }
632
633 // Clear noSquashFromTC.
634 for (int tid = 0; tid < numThreads; ++tid)
635 thread[tid]->noSquashFromTC = false;
636
637 commit.setThreads(thread);
638}
639
640template <class Impl>
641void
642FullO3CPU<Impl>::startup()
643{
644 BaseCPU::startup();
645 for (int tid = 0; tid < numThreads; ++tid)
646 isa[tid]->startup(threadContexts[tid]);
647
648 fetch.startupStage();
649 decode.startupStage();
650 iew.startupStage();
651 rename.startupStage();
652 commit.startupStage();
653}
654
655template <class Impl>
656void
657FullO3CPU<Impl>::activateThread(ThreadID tid)
658{
659 list<ThreadID>::iterator isActive =
660 std::find(activeThreads.begin(), activeThreads.end(), tid);
661
662 DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid);
663 assert(!switchedOut());
664
665 if (isActive == activeThreads.end()) {
666 DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n",
667 tid);
668
669 activeThreads.push_back(tid);
670 }
671}
672
673template <class Impl>
674void
675FullO3CPU<Impl>::deactivateThread(ThreadID tid)
676{
677 //Remove From Active List, if Active
678 list<ThreadID>::iterator thread_it =
679 std::find(activeThreads.begin(), activeThreads.end(), tid);
680
681 DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid);
682 assert(!switchedOut());
683
684 if (thread_it != activeThreads.end()) {
685 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
686 tid);
687 activeThreads.erase(thread_it);
688 }
689
690 fetch.deactivateThread(tid);
691 commit.deactivateThread(tid);
692}
693
694template <class Impl>
695Counter
696FullO3CPU<Impl>::totalInsts() const
697{
698 Counter total(0);
699
700 ThreadID size = thread.size();
701 for (ThreadID i = 0; i < size; i++)
702 total += thread[i]->numInst;
703
704 return total;
705}
706
707template <class Impl>
708Counter
709FullO3CPU<Impl>::totalOps() const
710{
711 Counter total(0);
712
713 ThreadID size = thread.size();
714 for (ThreadID i = 0; i < size; i++)
715 total += thread[i]->numOp;
716
717 return total;
718}
719
720template <class Impl>
721void
722FullO3CPU<Impl>::activateContext(ThreadID tid)
723{
724 assert(!switchedOut());
725
726 // Needs to set each stage to running as well.
727 activateThread(tid);
728
729 // We don't want to wake the CPU if it is drained. In that case,
730 // we just want to flag the thread as active and schedule the tick
731 // event from drainResume() instead.
732 if (drainState() == DrainState::Drained)
733 return;
734
735 // If we are time 0 or if the last activation time is in the past,
736 // schedule the next tick and wake up the fetch unit
737 if (lastActivatedCycle == 0 || lastActivatedCycle < curTick()) {
738 scheduleTickEvent(Cycles(0));
739
740 // Be sure to signal that there's some activity so the CPU doesn't
741 // deschedule itself.
742 activityRec.activity();
743 fetch.wakeFromQuiesce();
744
745 Cycles cycles(curCycle() - lastRunningCycle);
746 // @todo: This is an oddity that is only here to match the stats
747 if (cycles != 0)
748 --cycles;
749 quiesceCycles += cycles;
750
751 lastActivatedCycle = curTick();
752
753 _status = Running;
754 }
755}
756
757template <class Impl>
758void
759FullO3CPU<Impl>::suspendContext(ThreadID tid)
760{
761 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
762 assert(!switchedOut());
763
764 deactivateThread(tid);
765
766 // If this was the last thread then unschedule the tick event.
767 if (activeThreads.size() == 0) {
768 unscheduleTickEvent();
769 lastRunningCycle = curCycle();
770 _status = Idle;
771 }
772
773 DPRINTF(Quiesce, "Suspending Context\n");
774}
775
776template <class Impl>
777void
778FullO3CPU<Impl>::haltContext(ThreadID tid)
779{
780 //For now, this is the same as deallocate
781 DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
782 assert(!switchedOut());
783
784 deactivateThread(tid);
785 removeThread(tid);
786}
787
788template <class Impl>
789void
790FullO3CPU<Impl>::insertThread(ThreadID tid)
791{
792 DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
793 // Will change now that the PC and thread state is internal to the CPU
794 // and not in the ThreadContext.
795 ThreadContext *src_tc;
796 if (FullSystem)
797 src_tc = system->threadContexts[tid];
798 else
799 src_tc = tcBase(tid);
800
801 //Bind Int Regs to Rename Map
802 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
803 PhysRegIndex phys_reg = freeList.getIntReg();
804
805 renameMap[tid].setEntry(ireg,phys_reg);
806 scoreboard.setReg(phys_reg);
807 }
808
809 //Bind Float Regs to Rename Map
810 int max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs;
811 for (int freg = TheISA::NumIntRegs; freg < max_reg; freg++) {
812 PhysRegIndex phys_reg = freeList.getFloatReg();
813
814 renameMap[tid].setEntry(freg,phys_reg);
815 scoreboard.setReg(phys_reg);
816 }
817
818 //Bind condition-code Regs to Rename Map
819 max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs + TheISA::NumCCRegs;
820 for (int creg = TheISA::NumIntRegs + TheISA::NumFloatRegs;
821 creg < max_reg; creg++) {
822 PhysRegIndex phys_reg = freeList.getCCReg();
823
824 renameMap[tid].setEntry(creg,phys_reg);
825 scoreboard.setReg(phys_reg);
826 }
827
828 //Bind vector Regs to Rename Map
829 max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs + TheISA::NumCCRegs +
830 TheISA::NumVectorRegs;
831 for (int vreg = TheISA::NumIntRegs + TheISA::NumFloatRegs +
832 TheISA::NumCCRegs;
833 vreg < max_reg; vreg++) {
834 PhysRegIndex phys_reg = freeList.getVectorReg();
835
836 renameMap[tid].setEntry(vreg, phys_reg);
837 scoreboard.setReg(phys_reg);
838 }
839
840 //Copy Thread Data Into RegFile
841 //this->copyFromTC(tid);
842
843 //Set PC/NPC/NNPC
844 pcState(src_tc->pcState(), tid);
845
846 src_tc->setStatus(ThreadContext::Active);
847
848 activateContext(tid);
849
850 //Reset ROB/IQ/LSQ Entries
851 commit.rob->resetEntries();
852 iew.resetEntries();
853}
854
855template <class Impl>
856void
857FullO3CPU<Impl>::removeThread(ThreadID tid)
858{
859 DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
860
861 // Copy Thread Data From RegFile
862 // If thread is suspended, it might be re-allocated
863 // this->copyToTC(tid);
864
865
866 // @todo: 2-27-2008: Fix how we free up rename mappings
867 // here to alleviate the case for double-freeing registers
868 // in SMT workloads.
869
870 // Unbind Int Regs from Rename Map
871 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
872 PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
873 scoreboard.unsetReg(phys_reg);
874 freeList.addReg(phys_reg);
875 }
876
877 // Unbind Float Regs from Rename Map
878 int max_reg = TheISA::FP_Reg_Base + TheISA::NumFloatRegs;
879 for (int freg = TheISA::FP_Reg_Base; freg < max_reg; freg++) {
880 PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
881 scoreboard.unsetReg(phys_reg);
882 freeList.addReg(phys_reg);
883 }
884
885 // Unbind condition-code Regs from Rename Map
886 max_reg = TheISA::CC_Reg_Base + TheISA::NumCCRegs;
887 for (int creg = TheISA::CC_Reg_Base; creg < max_reg; creg++) {
888 PhysRegIndex phys_reg = renameMap[tid].lookup(creg);
889 scoreboard.unsetReg(phys_reg);
890 freeList.addReg(phys_reg);
891 }
892
893 // Unbind condition-code Regs from Rename Map
894 max_reg = TheISA::Vector_Reg_Base + TheISA::NumVectorRegs;
895 for (int vreg = TheISA::Vector_Reg_Base; vreg < max_reg; vreg++) {
896 PhysRegIndex phys_reg = renameMap[tid].lookup(vreg);
897 scoreboard.unsetReg(phys_reg);
898 freeList.addReg(phys_reg);
899 }
900
901 // Squash Throughout Pipeline
902 DynInstPtr inst = commit.rob->readHeadInst(tid);
903 InstSeqNum squash_seq_num = inst->seqNum;
904 fetch.squash(0, squash_seq_num, inst, tid);
905 decode.squash(tid);
906 rename.squash(squash_seq_num, tid);
907 iew.squash(tid);
908 iew.ldstQueue.squash(squash_seq_num, tid);
909 commit.rob->squash(squash_seq_num, tid);
910
911
912 assert(iew.instQueue.getCount(tid) == 0);
913 assert(iew.ldstQueue.getCount(tid) == 0);
914
915 // Reset ROB/IQ/LSQ Entries
916
917 // Commented out for now. This should be possible to do by
918 // telling all the pipeline stages to drain first, and then
919 // checking until the drain completes. Once the pipeline is
920 // drained, call resetEntries(). - 10-09-06 ktlim
921/*
922 if (activeThreads.size() >= 1) {
923 commit.rob->resetEntries();
924 iew.resetEntries();
925 }
926*/
927}
928
929template <class Impl>
930Fault
931FullO3CPU<Impl>::hwrei(ThreadID tid)
932{
933#if THE_ISA == ALPHA_ISA
934 // Need to clear the lock flag upon returning from an interrupt.
935 this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
936
937 this->thread[tid]->kernelStats->hwrei();
938
939 // FIXME: XXX check for interrupts? XXX
940#endif
941 return NoFault;
942}
943
944template <class Impl>
945bool
946FullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid)
947{
948#if THE_ISA == ALPHA_ISA
949 if (this->thread[tid]->kernelStats)
950 this->thread[tid]->kernelStats->callpal(palFunc,
951 this->threadContexts[tid]);
952
953 switch (palFunc) {
954 case PAL::halt:
955 halt();
956 if (--System::numSystemsRunning == 0)
957 exitSimLoop("all cpus halted");
958 break;
959
960 case PAL::bpt:
961 case PAL::bugchk:
962 if (this->system->breakpoint())
963 return false;
964 break;
965 }
966#endif
967 return true;
968}
969
970template <class Impl>
971Fault
972FullO3CPU<Impl>::getInterrupts()
973{
974 // Check if there are any outstanding interrupts
975 return this->interrupts->getInterrupt(this->threadContexts[0]);
976}
977
978template <class Impl>
979void
980FullO3CPU<Impl>::processInterrupts(const Fault &interrupt)
981{
982 // Check for interrupts here. For now can copy the code that
983 // exists within isa_fullsys_traits.hh. Also assume that thread 0
984 // is the one that handles the interrupts.
985 // @todo: Possibly consolidate the interrupt checking code.
986 // @todo: Allow other threads to handle interrupts.
987
988 assert(interrupt != NoFault);
989 this->interrupts->updateIntrInfo(this->threadContexts[0]);
990
991 DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
992 this->trap(interrupt, 0, nullptr);
993}
994
995template <class Impl>
996void
997FullO3CPU<Impl>::trap(const Fault &fault, ThreadID tid,
998 const StaticInstPtr &inst)
999{
1000 // Pass the thread's TC into the invoke method.
1001 fault->invoke(this->threadContexts[tid], inst);
1002}
1003
1004template <class Impl>
1005void
1006FullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid)
1007{
1008 DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid);
1009
1010 DPRINTF(Activity,"Activity: syscall() called.\n");
1011
1012 // Temporarily increase this by one to account for the syscall
1013 // instruction.
1014 ++(this->thread[tid]->funcExeInst);
1015
1016 // Execute the actual syscall.
1017 this->thread[tid]->syscall(callnum);
1018
1019 // Decrease funcExeInst by one as the normal commit will handle
1020 // incrementing it.
1021 --(this->thread[tid]->funcExeInst);
1022}
1023
1024template <class Impl>
1025void
1026FullO3CPU<Impl>::serializeThread(CheckpointOut &cp, ThreadID tid) const
1027{
1028 thread[tid]->serialize(cp);
1029}
1030
1031template <class Impl>
1032void
1033FullO3CPU<Impl>::unserializeThread(CheckpointIn &cp, ThreadID tid)
1034{
1035 thread[tid]->unserialize(cp);
1036}
1037
1038template <class Impl>
1039DrainState
1040FullO3CPU<Impl>::drain()
1041{
1042 // If the CPU isn't doing anything, then return immediately.
1043 if (switchedOut())
1044 return DrainState::Drained;
1045
1046 DPRINTF(Drain, "Draining...\n");
1047
1048 // We only need to signal a drain to the commit stage as this
1049 // initiates squashing controls the draining. Once the commit
1050 // stage commits an instruction where it is safe to stop, it'll
1051 // squash the rest of the instructions in the pipeline and force
1052 // the fetch stage to stall. The pipeline will be drained once all
1053 // in-flight instructions have retired.
1054 commit.drain();
1055
1056 // Wake the CPU and record activity so everything can drain out if
1057 // the CPU was not able to immediately drain.
1058 if (!isDrained()) {
1059 wakeCPU();
1060 activityRec.activity();
1061
1062 DPRINTF(Drain, "CPU not drained\n");
1063
1064 return DrainState::Draining;
1065 } else {
1066 DPRINTF(Drain, "CPU is already drained\n");
1067 if (tickEvent.scheduled())
1068 deschedule(tickEvent);
1069
1070 // Flush out any old data from the time buffers. In
1071 // particular, there might be some data in flight from the
1072 // fetch stage that isn't visible in any of the CPU buffers we
1073 // test in isDrained().
1074 for (int i = 0; i < timeBuffer.getSize(); ++i) {
1075 timeBuffer.advance();
1076 fetchQueue.advance();
1077 decodeQueue.advance();
1078 renameQueue.advance();
1079 iewQueue.advance();
1080 }
1081
1082 drainSanityCheck();
1083 return DrainState::Drained;
1084 }
1085}
1086
1087template <class Impl>
1088bool
1089FullO3CPU<Impl>::tryDrain()
1090{
1091 if (drainState() != DrainState::Draining || !isDrained())
1092 return false;
1093
1094 if (tickEvent.scheduled())
1095 deschedule(tickEvent);
1096
1097 DPRINTF(Drain, "CPU done draining, processing drain event\n");
1098 signalDrainDone();
1099
1100 return true;
1101}
1102
1103template <class Impl>
1104void
1105FullO3CPU<Impl>::drainSanityCheck() const
1106{
1107 assert(isDrained());
1108 fetch.drainSanityCheck();
1109 decode.drainSanityCheck();
1110 rename.drainSanityCheck();
1111 iew.drainSanityCheck();
1112 commit.drainSanityCheck();
1113}
1114
1115template <class Impl>
1116bool
1117FullO3CPU<Impl>::isDrained() const
1118{
1119 bool drained(true);
1120
1121 if (!instList.empty() || !removeList.empty()) {
1122 DPRINTF(Drain, "Main CPU structures not drained.\n");
1123 drained = false;
1124 }
1125
1126 if (!fetch.isDrained()) {
1127 DPRINTF(Drain, "Fetch not drained.\n");
1128 drained = false;
1129 }
1130
1131 if (!decode.isDrained()) {
1132 DPRINTF(Drain, "Decode not drained.\n");
1133 drained = false;
1134 }
1135
1136 if (!rename.isDrained()) {
1137 DPRINTF(Drain, "Rename not drained.\n");
1138 drained = false;
1139 }
1140
1141 if (!iew.isDrained()) {
1142 DPRINTF(Drain, "IEW not drained.\n");
1143 drained = false;
1144 }
1145
1146 if (!commit.isDrained()) {
1147 DPRINTF(Drain, "Commit not drained.\n");
1148 drained = false;
1149 }
1150
1151 return drained;
1152}
1153
1154template <class Impl>
1155void
1156FullO3CPU<Impl>::commitDrained(ThreadID tid)
1157{
1158 fetch.drainStall(tid);
1159}
1160
1161template <class Impl>
1162void
1163FullO3CPU<Impl>::drainResume()
1164{
1165 if (switchedOut())
1166 return;
1167
1168 DPRINTF(Drain, "Resuming...\n");
1169 verifyMemoryMode();
1170
1171 fetch.drainResume();
1172 commit.drainResume();
1173
1174 _status = Idle;
1175 for (ThreadID i = 0; i < thread.size(); i++) {
1176 if (thread[i]->status() == ThreadContext::Active) {
1177 DPRINTF(Drain, "Activating thread: %i\n", i);
1178 activateThread(i);
1179 _status = Running;
1180 }
1181 }
1182
1183 assert(!tickEvent.scheduled());
1184 if (_status == Running)
1185 schedule(tickEvent, nextCycle());
1186}
1187
1188template <class Impl>
1189void
1190FullO3CPU<Impl>::switchOut()
1191{
1192 DPRINTF(O3CPU, "Switching out\n");
1193 BaseCPU::switchOut();
1194
1195 activityRec.reset();
1196
1197 _status = SwitchedOut;
1198
1199 if (checker)
1200 checker->switchOut();
1201}
1202
1203template <class Impl>
1204void
1205FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
1206{
1207 BaseCPU::takeOverFrom(oldCPU);
1208
1209 fetch.takeOverFrom();
1210 decode.takeOverFrom();
1211 rename.takeOverFrom();
1212 iew.takeOverFrom();
1213 commit.takeOverFrom();
1214
1215 assert(!tickEvent.scheduled());
1216
1217 FullO3CPU<Impl> *oldO3CPU = dynamic_cast<FullO3CPU<Impl>*>(oldCPU);
1218 if (oldO3CPU)
1219 globalSeqNum = oldO3CPU->globalSeqNum;
1220
1221 lastRunningCycle = curCycle();
1222 _status = Idle;
1223}
1224
1225template <class Impl>
1226void
1227FullO3CPU<Impl>::verifyMemoryMode() const
1228{
1229 if (!system->isTimingMode()) {
1230 fatal("The O3 CPU requires the memory system to be in "
1231 "'timing' mode.\n");
1232 }
1233}
1234
1235template <class Impl>
1236TheISA::MiscReg
1237FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
1238{
1239 return this->isa[tid]->readMiscRegNoEffect(misc_reg);
1240}
1241
1242template <class Impl>
1243TheISA::MiscReg
1244FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
1245{
1246 miscRegfileReads++;
1247 return this->isa[tid]->readMiscReg(misc_reg, tcBase(tid));
1248}
1249
1250template <class Impl>
1251void
1252FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
1253 const TheISA::MiscReg &val, ThreadID tid)
1254{
1255 this->isa[tid]->setMiscRegNoEffect(misc_reg, val);
1256}
1257
1258template <class Impl>
1259void
1260FullO3CPU<Impl>::setMiscReg(int misc_reg,
1261 const TheISA::MiscReg &val, ThreadID tid)
1262{
1263 miscRegfileWrites++;
1264 this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid));
1265}
1266
1267template <class Impl>
1268uint64_t
1269FullO3CPU<Impl>::readIntReg(int reg_idx)
1270{
1271 intRegfileReads++;
1272 return regFile.readIntReg(reg_idx);
1273}
1274
1275template <class Impl>
1276FloatReg
1277FullO3CPU<Impl>::readFloatReg(int reg_idx)
1278{
1279 fpRegfileReads++;
1280 return regFile.readFloatReg(reg_idx);
1281}
1282
1283template <class Impl>
1284FloatRegBits
1285FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
1286{
1287 fpRegfileReads++;
1288 return regFile.readFloatRegBits(reg_idx);
1289}
1290
1291template <class Impl>
1292CCReg
1293FullO3CPU<Impl>::readCCReg(int reg_idx)
1294{
1295 ccRegfileReads++;
1296 return regFile.readCCReg(reg_idx);
1297}
1298
1299template <class Impl>
1300const VectorReg &
1301FullO3CPU<Impl>::readVectorReg(int reg_idx)
1302{
1303 vectorRegfileReads++;
1304 return regFile.readVectorReg(reg_idx);
1305}
1306
1307template <class Impl>
1308void
1309FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
1310{
1311 intRegfileWrites++;
1312 regFile.setIntReg(reg_idx, val);
1313}
1314
1315template <class Impl>
1316void
1317FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
1318{
1319 fpRegfileWrites++;
1320 regFile.setFloatReg(reg_idx, val);
1321}
1322
1323template <class Impl>
1324void
1325FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
1326{
1327 fpRegfileWrites++;
1328 regFile.setFloatRegBits(reg_idx, val);
1329}
1330
1331template <class Impl>
1332void
1333FullO3CPU<Impl>::setCCReg(int reg_idx, CCReg val)
1334{
1335 ccRegfileWrites++;
1336 regFile.setCCReg(reg_idx, val);
1337}
1338
1339template <class Impl>
1340void
1341FullO3CPU<Impl>::setVectorReg(int reg_idx, const VectorReg &val)
1342{
1343 vectorRegfileWrites++;
1344 regFile.setVectorReg(reg_idx, val);
1345}
1346
1347template <class Impl>
1348uint64_t
1349FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1350{
1351 intRegfileReads++;
1352 PhysRegIndex phys_reg = commitRenameMap[tid].lookupInt(reg_idx);
1353
1354 return regFile.readIntReg(phys_reg);
1355}
1356
1357template <class Impl>
1358float
1359FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
1360{
1361 fpRegfileReads++;
1362 PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1363
1364 return regFile.readFloatReg(phys_reg);
1365}
1366
1367template <class Impl>
1368uint64_t
1369FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid)
1370{
1371 fpRegfileReads++;
1372 PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1373
1374 return regFile.readFloatRegBits(phys_reg);
1375}
1376
1377template <class Impl>
1378CCReg
1379FullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid)
1380{
1381 ccRegfileReads++;
1382 PhysRegIndex phys_reg = commitRenameMap[tid].lookupCC(reg_idx);
1383
1384 return regFile.readCCReg(phys_reg);
1385}
1386
1387template <class Impl>
1388const VectorReg&
1389FullO3CPU<Impl>::readArchVectorReg(int reg_idx, ThreadID tid)
1390{
1391 vectorRegfileReads++;
1392 PhysRegIndex phys_reg = commitRenameMap[tid].lookupVector(reg_idx);
1393
1394 return regFile.readVectorReg(phys_reg);
1395}
1396
1397template <class Impl>
1398void
1399FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
1400{
1401 intRegfileWrites++;
1402 PhysRegIndex phys_reg = commitRenameMap[tid].lookupInt(reg_idx);
1403
1404 regFile.setIntReg(phys_reg, val);
1405}
1406
1407template <class Impl>
1408void
1409FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid)
1410{
1411 fpRegfileWrites++;
1412 PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1413
1414 regFile.setFloatReg(phys_reg, val);
1415}
1416
1417template <class Impl>
1418void
1419FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid)
1420{
1421 fpRegfileWrites++;
1422 PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1423
1424 regFile.setFloatRegBits(phys_reg, val);
1425}
1426
1427template <class Impl>
1428void
1429FullO3CPU<Impl>::setArchCCReg(int reg_idx, CCReg val, ThreadID tid)
1430{
1431 ccRegfileWrites++;
1432 PhysRegIndex phys_reg = commitRenameMap[tid].lookupCC(reg_idx);
1433
1434 regFile.setCCReg(phys_reg, val);
1435}
1436
1437template <class Impl>
1438void
1439FullO3CPU<Impl>::setArchVectorReg(int reg_idx, const VectorReg &val,
1440 ThreadID tid)
1441{
1442 vectorRegfileWrites++;
1443 PhysRegIndex phys_reg = commitRenameMap[tid].lookupVector(reg_idx);
1444 regFile.setVectorReg(phys_reg, val);
1445}
1446
1447template <class Impl>
1448TheISA::PCState
1449FullO3CPU<Impl>::pcState(ThreadID tid)
1450{
1451 return commit.pcState(tid);
1452}
1453
1454template <class Impl>
1455void
1456FullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid)
1457{
1458 commit.pcState(val, tid);
1459}
1460
1461template <class Impl>
1462Addr
1463FullO3CPU<Impl>::instAddr(ThreadID tid)
1464{
1465 return commit.instAddr(tid);
1466}
1467
1468template <class Impl>
1469Addr
1470FullO3CPU<Impl>::nextInstAddr(ThreadID tid)
1471{
1472 return commit.nextInstAddr(tid);
1473}
1474
1475template <class Impl>
1476MicroPC
1477FullO3CPU<Impl>::microPC(ThreadID tid)
1478{
1479 return commit.microPC(tid);
1480}
1481
1482template <class Impl>
1483void
1484FullO3CPU<Impl>::squashFromTC(ThreadID tid)
1485{
1486 this->thread[tid]->noSquashFromTC = true;
1487 this->commit.generateTCEvent(tid);
1488}
1489
1490template <class Impl>
1491typename FullO3CPU<Impl>::ListIt
1492FullO3CPU<Impl>::addInst(DynInstPtr &inst)
1493{
1494 instList.push_back(inst);
1495
1496 return --(instList.end());
1497}
1498
1499template <class Impl>
1500void
1501FullO3CPU<Impl>::instDone(ThreadID tid, DynInstPtr &inst)
1502{
1503 // Keep an instruction count.
1504 if (!inst->isMicroop() || inst->isLastMicroop()) {
1505 thread[tid]->numInst++;
1506 thread[tid]->numInsts++;
1507 committedInsts[tid]++;
1508 system->totalNumInsts++;
1509
1510 // Check for instruction-count-based events.
1511 comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1512 system->instEventQueue.serviceEvents(system->totalNumInsts);
1513 }
1514 thread[tid]->numOp++;
1515 thread[tid]->numOps++;
1516 committedOps[tid]++;
1517
1518 probeInstCommit(inst->staticInst);
1519}
1520
1521template <class Impl>
1522void
1523FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
1524{
1525 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s "
1526 "[sn:%lli]\n",
1527 inst->threadNumber, inst->pcState(), inst->seqNum);
1528
1529 removeInstsThisCycle = true;
1530
1531 // Remove the front instruction.
1532 removeList.push(inst->getInstListIt());
1533}
1534
1535template <class Impl>
1536void
1537FullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid)
1538{
1539 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1540 " list.\n", tid);
1541
1542 ListIt end_it;
1543
1544 bool rob_empty = false;
1545
1546 if (instList.empty()) {
1547 return;
1548 } else if (rob.isEmpty(tid)) {
1549 DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1550 end_it = instList.begin();
1551 rob_empty = true;
1552 } else {
1553 end_it = (rob.readTailInst(tid))->getInstListIt();
1554 DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1555 }
1556
1557 removeInstsThisCycle = true;
1558
1559 ListIt inst_it = instList.end();
1560
1561 inst_it--;
1562
1563 // Walk through the instruction list, removing any instructions
1564 // that were inserted after the given instruction iterator, end_it.
1565 while (inst_it != end_it) {
1566 assert(!instList.empty());
1567
1568 squashInstIt(inst_it, tid);
1569
1570 inst_it--;
1571 }
1572
1573 // If the ROB was empty, then we actually need to remove the first
1574 // instruction as well.
1575 if (rob_empty) {
1576 squashInstIt(inst_it, tid);
1577 }
1578}
1579
1580template <class Impl>
1581void
1582FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1583{
1584 assert(!instList.empty());
1585
1586 removeInstsThisCycle = true;
1587
1588 ListIt inst_iter = instList.end();
1589
1590 inst_iter--;
1591
1592 DPRINTF(O3CPU, "Deleting instructions from instruction "
1593 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1594 tid, seq_num, (*inst_iter)->seqNum);
1595
1596 while ((*inst_iter)->seqNum > seq_num) {
1597
1598 bool break_loop = (inst_iter == instList.begin());
1599
1600 squashInstIt(inst_iter, tid);
1601
1602 inst_iter--;
1603
1604 if (break_loop)
1605 break;
1606 }
1607}
1608
1609template <class Impl>
1610inline void
1611FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid)
1612{
1613 if ((*instIt)->threadNumber == tid) {
1614 DPRINTF(O3CPU, "Squashing instruction, "
1615 "[tid:%i] [sn:%lli] PC %s\n",
1616 (*instIt)->threadNumber,
1617 (*instIt)->seqNum,
1618 (*instIt)->pcState());
1619
1620 // Mark it as squashed.
1621 (*instIt)->setSquashed();
1622
1623 // @todo: Formulate a consistent method for deleting
1624 // instructions from the instruction list
1625 // Remove the instruction from the list.
1626 removeList.push(instIt);
1627 }
1628}
1629
1630template <class Impl>
1631void
1632FullO3CPU<Impl>::cleanUpRemovedInsts()
1633{
1634 while (!removeList.empty()) {
1635 DPRINTF(O3CPU, "Removing instruction, "
1636 "[tid:%i] [sn:%lli] PC %s\n",
1637 (*removeList.front())->threadNumber,
1638 (*removeList.front())->seqNum,
1639 (*removeList.front())->pcState());
1640
1641 instList.erase(removeList.front());
1642
1643 removeList.pop();
1644 }
1645
1646 removeInstsThisCycle = false;
1647}
1648/*
1649template <class Impl>
1650void
1651FullO3CPU<Impl>::removeAllInsts()
1652{
1653 instList.clear();
1654}
1655*/
1656template <class Impl>
1657void
1658FullO3CPU<Impl>::dumpInsts()
1659{
1660 int num = 0;
1661
1662 ListIt inst_list_it = instList.begin();
1663
1664 cprintf("Dumping Instruction List\n");
1665
1666 while (inst_list_it != instList.end()) {
1667 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1668 "Squashed:%i\n\n",
1669 num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber,
1670 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1671 (*inst_list_it)->isSquashed());
1672 inst_list_it++;
1673 ++num;
1674 }
1675}
1676/*
1677template <class Impl>
1678void
1679FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
1680{
1681 iew.wakeDependents(inst);
1682}
1683*/
1684template <class Impl>
1685void
1686FullO3CPU<Impl>::wakeCPU()
1687{
1688 if (activityRec.active() || tickEvent.scheduled()) {
1689 DPRINTF(Activity, "CPU already running.\n");
1690 return;
1691 }
1692
1693 DPRINTF(Activity, "Waking up CPU\n");
1694
1695 Cycles cycles(curCycle() - lastRunningCycle);
1696 // @todo: This is an oddity that is only here to match the stats
1697 if (cycles > 1) {
1698 --cycles;
1699 idleCycles += cycles;
1700 numCycles += cycles;
1701 ppCycles->notify(cycles);
1702 }
1703
1704 schedule(tickEvent, clockEdge());
1705}
1706
1707template <class Impl>
1708void
1709FullO3CPU<Impl>::wakeup()
1710{
1711 if (this->thread[0]->status() != ThreadContext::Suspended)
1712 return;
1713
1714 this->wakeCPU();
1715
1716 DPRINTF(Quiesce, "Suspended Processor woken\n");
1717 this->threadContexts[0]->activate();
1718}
1719
1720template <class Impl>
1721ThreadID
1722FullO3CPU<Impl>::getFreeTid()
1723{
1724 for (ThreadID tid = 0; tid < numThreads; tid++) {
1725 if (!tids[tid]) {
1726 tids[tid] = true;
1727 return tid;
1728 }
1729 }
1730
1731 return InvalidThreadID;
1732}
1733
1734template <class Impl>
1735void
1736FullO3CPU<Impl>::updateThreadPriority()
1737{
1738 if (activeThreads.size() > 1) {
1739 //DEFAULT TO ROUND ROBIN SCHEME
1740 //e.g. Move highest priority to end of thread list
1741 list<ThreadID>::iterator list_begin = activeThreads.begin();
1742
1743 unsigned high_thread = *list_begin;
1744
1745 activeThreads.erase(list_begin);
1746
1747 activeThreads.push_back(high_thread);
1748 }
1749}
1750
1751// Forward declaration of FullO3CPU.
1752template class FullO3CPU<O3CPUImpl>;