1/*
2 * Copyright (c) 2011-2012, 2014 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * Copyright (c) 2011 Regents of the University of California
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Kevin Lim
43 * Korey Sewell
44 * Rick Strong
45 */
46
47#include "arch/kernel_stats.hh"
48#include "config/the_isa.hh"
49#include "cpu/checker/cpu.hh"
50#include "cpu/checker/thread_context.hh"
51#include "cpu/o3/cpu.hh"
52#include "cpu/o3/isa_specific.hh"
53#include "cpu/o3/thread_context.hh"
54#include "cpu/activity.hh"
55#include "cpu/quiesce_event.hh"
56#include "cpu/simple_thread.hh"
57#include "cpu/thread_context.hh"
58#include "debug/Activity.hh"
59#include "debug/Drain.hh"
60#include "debug/O3CPU.hh"
61#include "debug/Quiesce.hh"
62#include "enums/MemoryMode.hh"
63#include "sim/core.hh"
64#include "sim/full_system.hh"
65#include "sim/process.hh"
66#include "sim/stat_control.hh"
67#include "sim/system.hh"
68
69#if THE_ISA == ALPHA_ISA
70#include "arch/alpha/osfpal.hh"
71#include "debug/Activity.hh"
72#endif
73
74struct BaseCPUParams;
75
76using namespace TheISA;
77using namespace std;
78
79BaseO3CPU::BaseO3CPU(BaseCPUParams *params)
80 : BaseCPU(params)
81{
82}
83
84void
85BaseO3CPU::regStats()
86{
87 BaseCPU::regStats();
88}
89
90template<class Impl>
91bool
92FullO3CPU<Impl>::IcachePort::recvTimingResp(PacketPtr pkt)
93{
94 DPRINTF(O3CPU, "Fetch unit received timing\n");
95 // We shouldn't ever get a block in ownership state
96 assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted()));
97 fetch->processCacheCompletion(pkt);
98
99 return true;
100}
101
102template<class Impl>
103void
104FullO3CPU<Impl>::IcachePort::recvReqRetry()
105{
106 fetch->recvReqRetry();
107}
108
109template <class Impl>
110bool
111FullO3CPU<Impl>::DcachePort::recvTimingResp(PacketPtr pkt)
112{
113 return lsq->recvTimingResp(pkt);
114}
115
116template <class Impl>
117void
118FullO3CPU<Impl>::DcachePort::recvTimingSnoopReq(PacketPtr pkt)
119{
120 // X86 ISA: Snooping an invalidation for monitor/mwait
121 if(cpu->getCpuAddrMonitor()->doMonitor(pkt)) {
122 cpu->wakeup();
123 }
124 lsq->recvTimingSnoopReq(pkt);
125}
126
127template <class Impl>
128void
129FullO3CPU<Impl>::DcachePort::recvReqRetry()
130{
131 lsq->recvReqRetry();
132}
133
134template <class Impl>
135FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
136 : Event(CPU_Tick_Pri), cpu(c)
137{
138}
139
140template <class Impl>
141void
142FullO3CPU<Impl>::TickEvent::process()
143{
144 cpu->tick();
145}
146
147template <class Impl>
148const char *
149FullO3CPU<Impl>::TickEvent::description() const
150{
151 return "FullO3CPU tick";
152}
153
154template <class Impl>
155FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
156 : BaseO3CPU(params),
157 itb(params->itb),
158 dtb(params->dtb),
159 tickEvent(this),
160#ifndef NDEBUG
161 instcount(0),
162#endif
163 removeInstsThisCycle(false),
164 fetch(this, params),
165 decode(this, params),
166 rename(this, params),
167 iew(this, params),
168 commit(this, params),
169
170 regFile(params->numPhysIntRegs,
171 params->numPhysFloatRegs,
172 params->numPhysCCRegs),
173
174 freeList(name() + ".freelist", ®File),
175
176 rob(this, params),
177
178 scoreboard(name() + ".scoreboard",
179 regFile.totalNumPhysRegs(), TheISA::NumMiscRegs,
180 TheISA::ZeroReg, TheISA::ZeroReg),
181
182 isa(numThreads, NULL),
183
184 icachePort(&fetch, this),
185 dcachePort(&iew.ldstQueue, this),
186
187 timeBuffer(params->backComSize, params->forwardComSize),
188 fetchQueue(params->backComSize, params->forwardComSize),
189 decodeQueue(params->backComSize, params->forwardComSize),
190 renameQueue(params->backComSize, params->forwardComSize),
191 iewQueue(params->backComSize, params->forwardComSize),
192 activityRec(name(), NumStages,
193 params->backComSize + params->forwardComSize,
194 params->activity),
195
196 globalSeqNum(1),
197 system(params->system),
198 drainManager(NULL),
199 lastRunningCycle(curCycle())
200{
201 if (!params->switched_out) {
202 _status = Running;
203 } else {
204 _status = SwitchedOut;
205 }
206
207 if (params->checker) {
208 BaseCPU *temp_checker = params->checker;
209 checker = dynamic_cast<Checker<Impl> *>(temp_checker);
210 checker->setIcachePort(&icachePort);
211 checker->setSystem(params->system);
212 } else {
213 checker = NULL;
214 }
215
216 if (!FullSystem) {
217 thread.resize(numThreads);
218 tids.resize(numThreads);
219 }
220
221 // The stages also need their CPU pointer setup. However this
222 // must be done at the upper level CPU because they have pointers
223 // to the upper level CPU, and not this FullO3CPU.
224
225 // Set up Pointers to the activeThreads list for each stage
226 fetch.setActiveThreads(&activeThreads);
227 decode.setActiveThreads(&activeThreads);
228 rename.setActiveThreads(&activeThreads);
229 iew.setActiveThreads(&activeThreads);
230 commit.setActiveThreads(&activeThreads);
231
232 // Give each of the stages the time buffer they will use.
233 fetch.setTimeBuffer(&timeBuffer);
234 decode.setTimeBuffer(&timeBuffer);
235 rename.setTimeBuffer(&timeBuffer);
236 iew.setTimeBuffer(&timeBuffer);
237 commit.setTimeBuffer(&timeBuffer);
238
239 // Also setup each of the stages' queues.
240 fetch.setFetchQueue(&fetchQueue);
241 decode.setFetchQueue(&fetchQueue);
242 commit.setFetchQueue(&fetchQueue);
243 decode.setDecodeQueue(&decodeQueue);
244 rename.setDecodeQueue(&decodeQueue);
245 rename.setRenameQueue(&renameQueue);
246 iew.setRenameQueue(&renameQueue);
247 iew.setIEWQueue(&iewQueue);
248 commit.setIEWQueue(&iewQueue);
249 commit.setRenameQueue(&renameQueue);
250
251 commit.setIEWStage(&iew);
252 rename.setIEWStage(&iew);
253 rename.setCommitStage(&commit);
254
255 ThreadID active_threads;
256 if (FullSystem) {
257 active_threads = 1;
258 } else {
259 active_threads = params->workload.size();
260
261 if (active_threads > Impl::MaxThreads) {
262 panic("Workload Size too large. Increase the 'MaxThreads' "
263 "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) "
264 "or edit your workload size.");
265 }
266 }
267
268 //Make Sure That this a Valid Architeture
269 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs);
270 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
271 assert(params->numPhysCCRegs >= numThreads * TheISA::NumCCRegs);
272
273 rename.setScoreboard(&scoreboard);
274 iew.setScoreboard(&scoreboard);
275
276 // Setup the rename map for whichever stages need it.
277 for (ThreadID tid = 0; tid < numThreads; tid++) {
278 isa[tid] = params->isa[tid];
279
280 // Only Alpha has an FP zero register, so for other ISAs we
281 // use an invalid FP register index to avoid special treatment
282 // of any valid FP reg.
283 RegIndex invalidFPReg = TheISA::NumFloatRegs + 1;
284 RegIndex fpZeroReg =
285 (THE_ISA == ALPHA_ISA) ? TheISA::ZeroReg : invalidFPReg;
286
287 commitRenameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg,
288 &freeList);
289
290 renameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg,
291 &freeList);
292 }
293
294 // Initialize rename map to assign physical registers to the
295 // architectural registers for active threads only.
296 for (ThreadID tid = 0; tid < active_threads; tid++) {
297 for (RegIndex ridx = 0; ridx < TheISA::NumIntRegs; ++ridx) {
298 // Note that we can't use the rename() method because we don't
299 // want special treatment for the zero register at this point
300 PhysRegIndex phys_reg = freeList.getIntReg();
301 renameMap[tid].setIntEntry(ridx, phys_reg);
302 commitRenameMap[tid].setIntEntry(ridx, phys_reg);
303 }
304
305 for (RegIndex ridx = 0; ridx < TheISA::NumFloatRegs; ++ridx) {
306 PhysRegIndex phys_reg = freeList.getFloatReg();
307 renameMap[tid].setFloatEntry(ridx, phys_reg);
308 commitRenameMap[tid].setFloatEntry(ridx, phys_reg);
309 }
310
311 for (RegIndex ridx = 0; ridx < TheISA::NumCCRegs; ++ridx) {
312 PhysRegIndex phys_reg = freeList.getCCReg();
313 renameMap[tid].setCCEntry(ridx, phys_reg);
314 commitRenameMap[tid].setCCEntry(ridx, phys_reg);
315 }
316 }
317
318 rename.setRenameMap(renameMap);
319 commit.setRenameMap(commitRenameMap);
320 rename.setFreeList(&freeList);
321
322 // Setup the ROB for whichever stages need it.
323 commit.setROB(&rob);
324
325 lastActivatedCycle = 0;
326#if 0
327 // Give renameMap & rename stage access to the freeList;
328 for (ThreadID tid = 0; tid < numThreads; tid++)
329 globalSeqNum[tid] = 1;
330#endif
331
332 DPRINTF(O3CPU, "Creating O3CPU object.\n");
333
334 // Setup any thread state.
335 this->thread.resize(this->numThreads);
336
337 for (ThreadID tid = 0; tid < this->numThreads; ++tid) {
338 if (FullSystem) {
339 // SMT is not supported in FS mode yet.
340 assert(this->numThreads == 1);
341 this->thread[tid] = new Thread(this, 0, NULL);
342 } else {
343 if (tid < params->workload.size()) {
344 DPRINTF(O3CPU, "Workload[%i] process is %#x",
345 tid, this->thread[tid]);
346 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
347 (typename Impl::O3CPU *)(this),
348 tid, params->workload[tid]);
349
350 //usedTids[tid] = true;
351 //threadMap[tid] = tid;
352 } else {
353 //Allocate Empty thread so M5 can use later
354 //when scheduling threads to CPU
355 Process* dummy_proc = NULL;
356
357 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
358 (typename Impl::O3CPU *)(this),
359 tid, dummy_proc);
360 //usedTids[tid] = false;
361 }
362 }
363
364 ThreadContext *tc;
365
366 // Setup the TC that will serve as the interface to the threads/CPU.
367 O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>;
368
369 tc = o3_tc;
370
371 // If we're using a checker, then the TC should be the
372 // CheckerThreadContext.
373 if (params->checker) {
374 tc = new CheckerThreadContext<O3ThreadContext<Impl> >(
375 o3_tc, this->checker);
376 }
377
378 o3_tc->cpu = (typename Impl::O3CPU *)(this);
379 assert(o3_tc->cpu);
380 o3_tc->thread = this->thread[tid];
381
382 if (FullSystem) {
383 // Setup quiesce event.
384 this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
385 }
386 // Give the thread the TC.
387 this->thread[tid]->tc = tc;
388
389 // Add the TC to the CPU's list of TC's.
390 this->threadContexts.push_back(tc);
391 }
392
393 // FullO3CPU always requires an interrupt controller.
394 if (!params->switched_out && !interrupts) {
395 fatal("FullO3CPU %s has no interrupt controller.\n"
396 "Ensure createInterruptController() is called.\n", name());
397 }
398
399 for (ThreadID tid = 0; tid < this->numThreads; tid++)
400 this->thread[tid]->setFuncExeInst(0);
401}
402
403template <class Impl>
404FullO3CPU<Impl>::~FullO3CPU()
405{
406}
407
408template <class Impl>
409void
410FullO3CPU<Impl>::regProbePoints()
411{
412 BaseCPU::regProbePoints();
413
414 ppInstAccessComplete = new ProbePointArg<PacketPtr>(getProbeManager(), "InstAccessComplete");
415 ppDataAccessComplete = new ProbePointArg<std::pair<DynInstPtr, PacketPtr> >(getProbeManager(), "DataAccessComplete");
416
417 fetch.regProbePoints();
418 iew.regProbePoints();
419 commit.regProbePoints();
420}
421
422template <class Impl>
423void
424FullO3CPU<Impl>::regStats()
425{
426 BaseO3CPU::regStats();
427
428 // Register any of the O3CPU's stats here.
429 timesIdled
430 .name(name() + ".timesIdled")
431 .desc("Number of times that the entire CPU went into an idle state and"
432 " unscheduled itself")
433 .prereq(timesIdled);
434
435 idleCycles
436 .name(name() + ".idleCycles")
437 .desc("Total number of cycles that the CPU has spent unscheduled due "
438 "to idling")
439 .prereq(idleCycles);
440
441 quiesceCycles
442 .name(name() + ".quiesceCycles")
443 .desc("Total number of cycles that CPU has spent quiesced or waiting "
444 "for an interrupt")
445 .prereq(quiesceCycles);
446
447 // Number of Instructions simulated
448 // --------------------------------
449 // Should probably be in Base CPU but need templated
450 // MaxThreads so put in here instead
451 committedInsts
452 .init(numThreads)
453 .name(name() + ".committedInsts")
454 .desc("Number of Instructions Simulated")
455 .flags(Stats::total);
456
457 committedOps
458 .init(numThreads)
459 .name(name() + ".committedOps")
460 .desc("Number of Ops (including micro ops) Simulated")
461 .flags(Stats::total);
462
463 cpi
464 .name(name() + ".cpi")
465 .desc("CPI: Cycles Per Instruction")
466 .precision(6);
467 cpi = numCycles / committedInsts;
468
469 totalCpi
470 .name(name() + ".cpi_total")
471 .desc("CPI: Total CPI of All Threads")
472 .precision(6);
473 totalCpi = numCycles / sum(committedInsts);
474
475 ipc
476 .name(name() + ".ipc")
477 .desc("IPC: Instructions Per Cycle")
478 .precision(6);
479 ipc = committedInsts / numCycles;
480
481 totalIpc
482 .name(name() + ".ipc_total")
483 .desc("IPC: Total IPC of All Threads")
484 .precision(6);
485 totalIpc = sum(committedInsts) / numCycles;
486
487 this->fetch.regStats();
488 this->decode.regStats();
489 this->rename.regStats();
490 this->iew.regStats();
491 this->commit.regStats();
492 this->rob.regStats();
493
494 intRegfileReads
495 .name(name() + ".int_regfile_reads")
496 .desc("number of integer regfile reads")
497 .prereq(intRegfileReads);
498
499 intRegfileWrites
500 .name(name() + ".int_regfile_writes")
501 .desc("number of integer regfile writes")
502 .prereq(intRegfileWrites);
503
504 fpRegfileReads
505 .name(name() + ".fp_regfile_reads")
506 .desc("number of floating regfile reads")
507 .prereq(fpRegfileReads);
508
509 fpRegfileWrites
510 .name(name() + ".fp_regfile_writes")
511 .desc("number of floating regfile writes")
512 .prereq(fpRegfileWrites);
513
514 ccRegfileReads
515 .name(name() + ".cc_regfile_reads")
516 .desc("number of cc regfile reads")
517 .prereq(ccRegfileReads);
518
519 ccRegfileWrites
520 .name(name() + ".cc_regfile_writes")
521 .desc("number of cc regfile writes")
522 .prereq(ccRegfileWrites);
523
524 miscRegfileReads
525 .name(name() + ".misc_regfile_reads")
526 .desc("number of misc regfile reads")
527 .prereq(miscRegfileReads);
528
529 miscRegfileWrites
530 .name(name() + ".misc_regfile_writes")
531 .desc("number of misc regfile writes")
532 .prereq(miscRegfileWrites);
533}
534
535template <class Impl>
536void
537FullO3CPU<Impl>::tick()
538{
539 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
540 assert(!switchedOut());
541 assert(getDrainState() != Drainable::Drained);
542
543 ++numCycles;
544 ppCycles->notify(1);
545
546// activity = false;
547
548 //Tick each of the stages
549 fetch.tick();
550
551 decode.tick();
552
553 rename.tick();
554
555 iew.tick();
556
557 commit.tick();
558
559 // Now advance the time buffers
560 timeBuffer.advance();
561
562 fetchQueue.advance();
563 decodeQueue.advance();
564 renameQueue.advance();
565 iewQueue.advance();
566
567 activityRec.advance();
568
569 if (removeInstsThisCycle) {
570 cleanUpRemovedInsts();
571 }
572
573 if (!tickEvent.scheduled()) {
574 if (_status == SwitchedOut) {
575 DPRINTF(O3CPU, "Switched out!\n");
576 // increment stat
577 lastRunningCycle = curCycle();
578 } else if (!activityRec.active() || _status == Idle) {
579 DPRINTF(O3CPU, "Idle!\n");
580 lastRunningCycle = curCycle();
581 timesIdled++;
582 } else {
583 schedule(tickEvent, clockEdge(Cycles(1)));
584 DPRINTF(O3CPU, "Scheduling next tick!\n");
585 }
586 }
587
588 if (!FullSystem)
589 updateThreadPriority();
590
591 tryDrain();
592}
593
594template <class Impl>
595void
596FullO3CPU<Impl>::init()
597{
598 BaseCPU::init();
599
600 for (ThreadID tid = 0; tid < numThreads; ++tid) {
601 // Set noSquashFromTC so that the CPU doesn't squash when initially
602 // setting up registers.
603 thread[tid]->noSquashFromTC = true;
604 // Initialise the ThreadContext's memory proxies
605 thread[tid]->initMemProxies(thread[tid]->getTC());
606 }
607
608 if (FullSystem && !params()->switched_out) {
609 for (ThreadID tid = 0; tid < numThreads; tid++) {
610 ThreadContext *src_tc = threadContexts[tid];
611 TheISA::initCPU(src_tc, src_tc->contextId());
612 }
613 }
614
615 // Clear noSquashFromTC.
616 for (int tid = 0; tid < numThreads; ++tid)
617 thread[tid]->noSquashFromTC = false;
618
619 commit.setThreads(thread);
620}
621
622template <class Impl>
623void
624FullO3CPU<Impl>::startup()
625{
626 BaseCPU::startup();
627 for (int tid = 0; tid < numThreads; ++tid)
628 isa[tid]->startup(threadContexts[tid]);
629
630 fetch.startupStage();
631 decode.startupStage();
632 iew.startupStage();
633 rename.startupStage();
634 commit.startupStage();
635}
636
637template <class Impl>
638void
639FullO3CPU<Impl>::activateThread(ThreadID tid)
640{
641 list<ThreadID>::iterator isActive =
642 std::find(activeThreads.begin(), activeThreads.end(), tid);
643
644 DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid);
645 assert(!switchedOut());
646
647 if (isActive == activeThreads.end()) {
648 DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n",
649 tid);
650
651 activeThreads.push_back(tid);
652 }
653}
654
655template <class Impl>
656void
657FullO3CPU<Impl>::deactivateThread(ThreadID tid)
658{
659 //Remove From Active List, if Active
660 list<ThreadID>::iterator thread_it =
661 std::find(activeThreads.begin(), activeThreads.end(), tid);
662
663 DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid);
664 assert(!switchedOut());
665
666 if (thread_it != activeThreads.end()) {
667 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
668 tid);
669 activeThreads.erase(thread_it);
670 }
671
672 fetch.deactivateThread(tid);
673 commit.deactivateThread(tid);
674}
675
676template <class Impl>
677Counter
678FullO3CPU<Impl>::totalInsts() const
679{
680 Counter total(0);
681
682 ThreadID size = thread.size();
683 for (ThreadID i = 0; i < size; i++)
684 total += thread[i]->numInst;
685
686 return total;
687}
688
689template <class Impl>
690Counter
691FullO3CPU<Impl>::totalOps() const
692{
693 Counter total(0);
694
695 ThreadID size = thread.size();
696 for (ThreadID i = 0; i < size; i++)
697 total += thread[i]->numOp;
698
699 return total;
700}
701
702template <class Impl>
703void
704FullO3CPU<Impl>::activateContext(ThreadID tid)
705{
706 assert(!switchedOut());
707
708 // Needs to set each stage to running as well.
709 activateThread(tid);
710
711 // We don't want to wake the CPU if it is drained. In that case,
712 // we just want to flag the thread as active and schedule the tick
713 // event from drainResume() instead.
714 if (getDrainState() == Drainable::Drained)
715 return;
716
717 // If we are time 0 or if the last activation time is in the past,
718 // schedule the next tick and wake up the fetch unit
719 if (lastActivatedCycle == 0 || lastActivatedCycle < curTick()) {
720 scheduleTickEvent(Cycles(0));
721
722 // Be sure to signal that there's some activity so the CPU doesn't
723 // deschedule itself.
724 activityRec.activity();
725 fetch.wakeFromQuiesce();
726
727 Cycles cycles(curCycle() - lastRunningCycle);
728 // @todo: This is an oddity that is only here to match the stats
729 if (cycles != 0)
730 --cycles;
731 quiesceCycles += cycles;
732
733 lastActivatedCycle = curTick();
734
735 _status = Running;
736 }
737}
738
739template <class Impl>
740void
741FullO3CPU<Impl>::suspendContext(ThreadID tid)
742{
743 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
744 assert(!switchedOut());
745
746 deactivateThread(tid);
747
748 // If this was the last thread then unschedule the tick event.
749 if (activeThreads.size() == 0) {
750 unscheduleTickEvent();
751 lastRunningCycle = curCycle();
752 _status = Idle;
753 }
754
755 DPRINTF(Quiesce, "Suspending Context\n");
756}
757
758template <class Impl>
759void
760FullO3CPU<Impl>::haltContext(ThreadID tid)
761{
762 //For now, this is the same as deallocate
763 DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
764 assert(!switchedOut());
765
766 deactivateThread(tid);
767 removeThread(tid);
768}
769
770template <class Impl>
771void
772FullO3CPU<Impl>::insertThread(ThreadID tid)
773{
774 DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
775 // Will change now that the PC and thread state is internal to the CPU
776 // and not in the ThreadContext.
777 ThreadContext *src_tc;
778 if (FullSystem)
779 src_tc = system->threadContexts[tid];
780 else
781 src_tc = tcBase(tid);
782
783 //Bind Int Regs to Rename Map
784 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
785 PhysRegIndex phys_reg = freeList.getIntReg();
786
787 renameMap[tid].setEntry(ireg,phys_reg);
788 scoreboard.setReg(phys_reg);
789 }
790
791 //Bind Float Regs to Rename Map
792 int max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs;
793 for (int freg = TheISA::NumIntRegs; freg < max_reg; freg++) {
794 PhysRegIndex phys_reg = freeList.getFloatReg();
795
796 renameMap[tid].setEntry(freg,phys_reg);
797 scoreboard.setReg(phys_reg);
798 }
799
800 //Bind condition-code Regs to Rename Map
801 max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs + TheISA::NumCCRegs;
802 for (int creg = TheISA::NumIntRegs + TheISA::NumFloatRegs;
803 creg < max_reg; creg++) {
804 PhysRegIndex phys_reg = freeList.getCCReg();
805
806 renameMap[tid].setEntry(creg,phys_reg);
807 scoreboard.setReg(phys_reg);
808 }
809
810 //Copy Thread Data Into RegFile
811 //this->copyFromTC(tid);
812
813 //Set PC/NPC/NNPC
814 pcState(src_tc->pcState(), tid);
815
816 src_tc->setStatus(ThreadContext::Active);
817
818 activateContext(tid);
819
820 //Reset ROB/IQ/LSQ Entries
821 commit.rob->resetEntries();
822 iew.resetEntries();
823}
824
825template <class Impl>
826void
827FullO3CPU<Impl>::removeThread(ThreadID tid)
828{
829 DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
830
831 // Copy Thread Data From RegFile
832 // If thread is suspended, it might be re-allocated
833 // this->copyToTC(tid);
834
835
836 // @todo: 2-27-2008: Fix how we free up rename mappings
837 // here to alleviate the case for double-freeing registers
838 // in SMT workloads.
839
840 // Unbind Int Regs from Rename Map
841 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
842 PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
843 scoreboard.unsetReg(phys_reg);
844 freeList.addReg(phys_reg);
845 }
846
847 // Unbind Float Regs from Rename Map
848 int max_reg = TheISA::FP_Reg_Base + TheISA::NumFloatRegs;
849 for (int freg = TheISA::FP_Reg_Base; freg < max_reg; freg++) {
850 PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
851 scoreboard.unsetReg(phys_reg);
852 freeList.addReg(phys_reg);
853 }
854
855 // Unbind condition-code Regs from Rename Map
856 max_reg = TheISA::CC_Reg_Base + TheISA::NumCCRegs;
857 for (int creg = TheISA::CC_Reg_Base; creg < max_reg; creg++) {
858 PhysRegIndex phys_reg = renameMap[tid].lookup(creg);
859 scoreboard.unsetReg(phys_reg);
860 freeList.addReg(phys_reg);
861 }
862
863 // Squash Throughout Pipeline
864 DynInstPtr inst = commit.rob->readHeadInst(tid);
865 InstSeqNum squash_seq_num = inst->seqNum;
866 fetch.squash(0, squash_seq_num, inst, tid);
867 decode.squash(tid);
868 rename.squash(squash_seq_num, tid);
869 iew.squash(tid);
870 iew.ldstQueue.squash(squash_seq_num, tid);
871 commit.rob->squash(squash_seq_num, tid);
872
873
874 assert(iew.instQueue.getCount(tid) == 0);
875 assert(iew.ldstQueue.getCount(tid) == 0);
876
877 // Reset ROB/IQ/LSQ Entries
878
879 // Commented out for now. This should be possible to do by
880 // telling all the pipeline stages to drain first, and then
881 // checking until the drain completes. Once the pipeline is
882 // drained, call resetEntries(). - 10-09-06 ktlim
883/*
884 if (activeThreads.size() >= 1) {
885 commit.rob->resetEntries();
886 iew.resetEntries();
887 }
888*/
889}
890
891template <class Impl>
892Fault
893FullO3CPU<Impl>::hwrei(ThreadID tid)
894{
895#if THE_ISA == ALPHA_ISA
896 // Need to clear the lock flag upon returning from an interrupt.
897 this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
898
899 this->thread[tid]->kernelStats->hwrei();
900
901 // FIXME: XXX check for interrupts? XXX
902#endif
903 return NoFault;
904}
905
906template <class Impl>
907bool
908FullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid)
909{
910#if THE_ISA == ALPHA_ISA
911 if (this->thread[tid]->kernelStats)
912 this->thread[tid]->kernelStats->callpal(palFunc,
913 this->threadContexts[tid]);
914
915 switch (palFunc) {
916 case PAL::halt:
917 halt();
918 if (--System::numSystemsRunning == 0)
919 exitSimLoop("all cpus halted");
920 break;
921
922 case PAL::bpt:
923 case PAL::bugchk:
924 if (this->system->breakpoint())
925 return false;
926 break;
927 }
928#endif
929 return true;
930}
931
932template <class Impl>
933Fault
934FullO3CPU<Impl>::getInterrupts()
935{
936 // Check if there are any outstanding interrupts
937 return this->interrupts->getInterrupt(this->threadContexts[0]);
938}
939
940template <class Impl>
941void
942FullO3CPU<Impl>::processInterrupts(const Fault &interrupt)
943{
944 // Check for interrupts here. For now can copy the code that
945 // exists within isa_fullsys_traits.hh. Also assume that thread 0
946 // is the one that handles the interrupts.
947 // @todo: Possibly consolidate the interrupt checking code.
948 // @todo: Allow other threads to handle interrupts.
949
950 assert(interrupt != NoFault);
951 this->interrupts->updateIntrInfo(this->threadContexts[0]);
952
953 DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
954 this->trap(interrupt, 0, nullptr);
955}
956
957template <class Impl>
958void
959FullO3CPU<Impl>::trap(const Fault &fault, ThreadID tid,
960 const StaticInstPtr &inst)
961{
962 // Pass the thread's TC into the invoke method.
963 fault->invoke(this->threadContexts[tid], inst);
964}
965
966template <class Impl>
967void
968FullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid)
969{
970 DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid);
971
972 DPRINTF(Activity,"Activity: syscall() called.\n");
973
974 // Temporarily increase this by one to account for the syscall
975 // instruction.
976 ++(this->thread[tid]->funcExeInst);
977
978 // Execute the actual syscall.
979 this->thread[tid]->syscall(callnum);
980
981 // Decrease funcExeInst by one as the normal commit will handle
982 // incrementing it.
983 --(this->thread[tid]->funcExeInst);
984}
985
986template <class Impl>
987void
988FullO3CPU<Impl>::serializeThread(std::ostream &os, ThreadID tid)
989{
990 thread[tid]->serialize(os);
991}
992
993template <class Impl>
994void
995FullO3CPU<Impl>::unserializeThread(Checkpoint *cp, const std::string §ion,
996 ThreadID tid)
997{
998 thread[tid]->unserialize(cp, section);
999}
1000
1001template <class Impl>
1002unsigned int
1003FullO3CPU<Impl>::drain(DrainManager *drain_manager)
1004{
1005 // If the CPU isn't doing anything, then return immediately.
1006 if (switchedOut()) {
1007 setDrainState(Drainable::Drained);
1008 return 0;
1009 }
1010
1011 DPRINTF(Drain, "Draining...\n");
1012 setDrainState(Drainable::Draining);
1013
1014 // We only need to signal a drain to the commit stage as this
1015 // initiates squashing controls the draining. Once the commit
1016 // stage commits an instruction where it is safe to stop, it'll
1017 // squash the rest of the instructions in the pipeline and force
1018 // the fetch stage to stall. The pipeline will be drained once all
1019 // in-flight instructions have retired.
1020 commit.drain();
1021
1022 // Wake the CPU and record activity so everything can drain out if
1023 // the CPU was not able to immediately drain.
1024 if (!isDrained()) {
1025 drainManager = drain_manager;
1026
1027 wakeCPU();
1028 activityRec.activity();
1029
1030 DPRINTF(Drain, "CPU not drained\n");
1031
1032 return 1;
1033 } else {
1034 setDrainState(Drainable::Drained);
1035 DPRINTF(Drain, "CPU is already drained\n");
1036 if (tickEvent.scheduled())
1037 deschedule(tickEvent);
1038
1039 // Flush out any old data from the time buffers. In
1040 // particular, there might be some data in flight from the
1041 // fetch stage that isn't visible in any of the CPU buffers we
1042 // test in isDrained().
1043 for (int i = 0; i < timeBuffer.getSize(); ++i) {
1044 timeBuffer.advance();
1045 fetchQueue.advance();
1046 decodeQueue.advance();
1047 renameQueue.advance();
1048 iewQueue.advance();
1049 }
1050
1051 drainSanityCheck();
1052 return 0;
1053 }
1054}
1055
1056template <class Impl>
1057bool
1058FullO3CPU<Impl>::tryDrain()
1059{
1060 if (!drainManager || !isDrained())
1061 return false;
1062
1063 if (tickEvent.scheduled())
1064 deschedule(tickEvent);
1065
1066 DPRINTF(Drain, "CPU done draining, processing drain event\n");
1067 drainManager->signalDrainDone();
1068 drainManager = NULL;
1069
1070 return true;
1071}
1072
1073template <class Impl>
1074void
1075FullO3CPU<Impl>::drainSanityCheck() const
1076{
1077 assert(isDrained());
1078 fetch.drainSanityCheck();
1079 decode.drainSanityCheck();
1080 rename.drainSanityCheck();
1081 iew.drainSanityCheck();
1082 commit.drainSanityCheck();
1083}
1084
1085template <class Impl>
1086bool
1087FullO3CPU<Impl>::isDrained() const
1088{
1089 bool drained(true);
1090
1091 if (!instList.empty() || !removeList.empty()) {
1092 DPRINTF(Drain, "Main CPU structures not drained.\n");
1093 drained = false;
1094 }
1095
1096 if (!fetch.isDrained()) {
1097 DPRINTF(Drain, "Fetch not drained.\n");
1098 drained = false;
1099 }
1100
1101 if (!decode.isDrained()) {
1102 DPRINTF(Drain, "Decode not drained.\n");
1103 drained = false;
1104 }
1105
1106 if (!rename.isDrained()) {
1107 DPRINTF(Drain, "Rename not drained.\n");
1108 drained = false;
1109 }
1110
1111 if (!iew.isDrained()) {
1112 DPRINTF(Drain, "IEW not drained.\n");
1113 drained = false;
1114 }
1115
1116 if (!commit.isDrained()) {
1117 DPRINTF(Drain, "Commit not drained.\n");
1118 drained = false;
1119 }
1120
1121 return drained;
1122}
1123
1124template <class Impl>
1125void
1126FullO3CPU<Impl>::commitDrained(ThreadID tid)
1127{
1128 fetch.drainStall(tid);
1129}
1130
1131template <class Impl>
1132void
1133FullO3CPU<Impl>::drainResume()
1134{
1135 setDrainState(Drainable::Running);
1136 if (switchedOut())
1137 return;
1138
1139 DPRINTF(Drain, "Resuming...\n");
1140 verifyMemoryMode();
1141
1142 fetch.drainResume();
1143 commit.drainResume();
1144
1145 _status = Idle;
1146 for (ThreadID i = 0; i < thread.size(); i++) {
1147 if (thread[i]->status() == ThreadContext::Active) {
1148 DPRINTF(Drain, "Activating thread: %i\n", i);
1149 activateThread(i);
1150 _status = Running;
1151 }
1152 }
1153
1154 assert(!tickEvent.scheduled());
1155 if (_status == Running)
1156 schedule(tickEvent, nextCycle());
1157}
1158
1159template <class Impl>
1160void
1161FullO3CPU<Impl>::switchOut()
1162{
1163 DPRINTF(O3CPU, "Switching out\n");
1164 BaseCPU::switchOut();
1165
1166 activityRec.reset();
1167
1168 _status = SwitchedOut;
1169
1170 if (checker)
1171 checker->switchOut();
1172}
1173
1174template <class Impl>
1175void
1176FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
1177{
1178 BaseCPU::takeOverFrom(oldCPU);
1179
1180 fetch.takeOverFrom();
1181 decode.takeOverFrom();
1182 rename.takeOverFrom();
1183 iew.takeOverFrom();
1184 commit.takeOverFrom();
1185
1186 assert(!tickEvent.scheduled());
1187
1188 FullO3CPU<Impl> *oldO3CPU = dynamic_cast<FullO3CPU<Impl>*>(oldCPU);
1189 if (oldO3CPU)
1190 globalSeqNum = oldO3CPU->globalSeqNum;
1191
1192 lastRunningCycle = curCycle();
1193 _status = Idle;
1194}
1195
1196template <class Impl>
1197void
1198FullO3CPU<Impl>::verifyMemoryMode() const
1199{
1200 if (!system->isTimingMode()) {
1201 fatal("The O3 CPU requires the memory system to be in "
1202 "'timing' mode.\n");
1203 }
1204}
1205
1206template <class Impl>
1207TheISA::MiscReg
1208FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
1209{
1210 return this->isa[tid]->readMiscRegNoEffect(misc_reg);
1211}
1212
1213template <class Impl>
1214TheISA::MiscReg
1215FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
1216{
1217 miscRegfileReads++;
1218 return this->isa[tid]->readMiscReg(misc_reg, tcBase(tid));
1219}
1220
1221template <class Impl>
1222void
1223FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
1224 const TheISA::MiscReg &val, ThreadID tid)
1225{
1226 this->isa[tid]->setMiscRegNoEffect(misc_reg, val);
1227}
1228
1229template <class Impl>
1230void
1231FullO3CPU<Impl>::setMiscReg(int misc_reg,
1232 const TheISA::MiscReg &val, ThreadID tid)
1233{
1234 miscRegfileWrites++;
1235 this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid));
1236}
1237
1238template <class Impl>
1239uint64_t
1240FullO3CPU<Impl>::readIntReg(int reg_idx)
1241{
1242 intRegfileReads++;
1243 return regFile.readIntReg(reg_idx);
1244}
1245
1246template <class Impl>
1247FloatReg
1248FullO3CPU<Impl>::readFloatReg(int reg_idx)
1249{
1250 fpRegfileReads++;
1251 return regFile.readFloatReg(reg_idx);
1252}
1253
1254template <class Impl>
1255FloatRegBits
1256FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
1257{
1258 fpRegfileReads++;
1259 return regFile.readFloatRegBits(reg_idx);
1260}
1261
1262template <class Impl>
1263CCReg
1264FullO3CPU<Impl>::readCCReg(int reg_idx)
1265{
1266 ccRegfileReads++;
1267 return regFile.readCCReg(reg_idx);
1268}
1269
1270template <class Impl>
1271void
1272FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
1273{
1274 intRegfileWrites++;
1275 regFile.setIntReg(reg_idx, val);
1276}
1277
1278template <class Impl>
1279void
1280FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
1281{
1282 fpRegfileWrites++;
1283 regFile.setFloatReg(reg_idx, val);
1284}
1285
1286template <class Impl>
1287void
1288FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
1289{
1290 fpRegfileWrites++;
1291 regFile.setFloatRegBits(reg_idx, val);
1292}
1293
1294template <class Impl>
1295void
1296FullO3CPU<Impl>::setCCReg(int reg_idx, CCReg val)
1297{
1298 ccRegfileWrites++;
1299 regFile.setCCReg(reg_idx, val);
1300}
1301
1302template <class Impl>
1303uint64_t
1304FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1305{
1306 intRegfileReads++;
1307 PhysRegIndex phys_reg = commitRenameMap[tid].lookupInt(reg_idx);
1308
1309 return regFile.readIntReg(phys_reg);
1310}
1311
1312template <class Impl>
1313float
1314FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
1315{
1316 fpRegfileReads++;
1317 PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1318
1319 return regFile.readFloatReg(phys_reg);
1320}
1321
1322template <class Impl>
1323uint64_t
1324FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid)
1325{
1326 fpRegfileReads++;
1327 PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1328
1329 return regFile.readFloatRegBits(phys_reg);
1330}
1331
1332template <class Impl>
1333CCReg
1334FullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid)
1335{
1336 ccRegfileReads++;
1337 PhysRegIndex phys_reg = commitRenameMap[tid].lookupCC(reg_idx);
1338
1339 return regFile.readCCReg(phys_reg);
1340}
1341
1342template <class Impl>
1343void
1344FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
1345{
1346 intRegfileWrites++;
1347 PhysRegIndex phys_reg = commitRenameMap[tid].lookupInt(reg_idx);
1348
1349 regFile.setIntReg(phys_reg, val);
1350}
1351
1352template <class Impl>
1353void
1354FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid)
1355{
1356 fpRegfileWrites++;
1357 PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1358
1359 regFile.setFloatReg(phys_reg, val);
1360}
1361
1362template <class Impl>
1363void
1364FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid)
1365{
1366 fpRegfileWrites++;
1367 PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1368
1369 regFile.setFloatRegBits(phys_reg, val);
1370}
1371
1372template <class Impl>
1373void
1374FullO3CPU<Impl>::setArchCCReg(int reg_idx, CCReg val, ThreadID tid)
1375{
1376 ccRegfileWrites++;
1377 PhysRegIndex phys_reg = commitRenameMap[tid].lookupCC(reg_idx);
1378
1379 regFile.setCCReg(phys_reg, val);
1380}
1381
1382template <class Impl>
1383TheISA::PCState
1384FullO3CPU<Impl>::pcState(ThreadID tid)
1385{
1386 return commit.pcState(tid);
1387}
1388
1389template <class Impl>
1390void
1391FullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid)
1392{
1393 commit.pcState(val, tid);
1394}
1395
1396template <class Impl>
1397Addr
1398FullO3CPU<Impl>::instAddr(ThreadID tid)
1399{
1400 return commit.instAddr(tid);
1401}
1402
1403template <class Impl>
1404Addr
1405FullO3CPU<Impl>::nextInstAddr(ThreadID tid)
1406{
1407 return commit.nextInstAddr(tid);
1408}
1409
1410template <class Impl>
1411MicroPC
1412FullO3CPU<Impl>::microPC(ThreadID tid)
1413{
1414 return commit.microPC(tid);
1415}
1416
1417template <class Impl>
1418void
1419FullO3CPU<Impl>::squashFromTC(ThreadID tid)
1420{
1421 this->thread[tid]->noSquashFromTC = true;
1422 this->commit.generateTCEvent(tid);
1423}
1424
1425template <class Impl>
1426typename FullO3CPU<Impl>::ListIt
1427FullO3CPU<Impl>::addInst(DynInstPtr &inst)
1428{
1429 instList.push_back(inst);
1430
1431 return --(instList.end());
1432}
1433
1434template <class Impl>
1435void
1436FullO3CPU<Impl>::instDone(ThreadID tid, DynInstPtr &inst)
1437{
1438 // Keep an instruction count.
1439 if (!inst->isMicroop() || inst->isLastMicroop()) {
1440 thread[tid]->numInst++;
1441 thread[tid]->numInsts++;
1442 committedInsts[tid]++;
1443 system->totalNumInsts++;
1444
1445 // Check for instruction-count-based events.
1446 comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1447 system->instEventQueue.serviceEvents(system->totalNumInsts);
1448 }
1449 thread[tid]->numOp++;
1450 thread[tid]->numOps++;
1451 committedOps[tid]++;
1452
1453 probeInstCommit(inst->staticInst);
1454}
1455
1456template <class Impl>
1457void
1458FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
1459{
1460 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s "
1461 "[sn:%lli]\n",
1462 inst->threadNumber, inst->pcState(), inst->seqNum);
1463
1464 removeInstsThisCycle = true;
1465
1466 // Remove the front instruction.
1467 removeList.push(inst->getInstListIt());
1468}
1469
1470template <class Impl>
1471void
1472FullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid)
1473{
1474 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1475 " list.\n", tid);
1476
1477 ListIt end_it;
1478
1479 bool rob_empty = false;
1480
1481 if (instList.empty()) {
1482 return;
1483 } else if (rob.isEmpty(tid)) {
1484 DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1485 end_it = instList.begin();
1486 rob_empty = true;
1487 } else {
1488 end_it = (rob.readTailInst(tid))->getInstListIt();
1489 DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1490 }
1491
1492 removeInstsThisCycle = true;
1493
1494 ListIt inst_it = instList.end();
1495
1496 inst_it--;
1497
1498 // Walk through the instruction list, removing any instructions
1499 // that were inserted after the given instruction iterator, end_it.
1500 while (inst_it != end_it) {
1501 assert(!instList.empty());
1502
1503 squashInstIt(inst_it, tid);
1504
1505 inst_it--;
1506 }
1507
1508 // If the ROB was empty, then we actually need to remove the first
1509 // instruction as well.
1510 if (rob_empty) {
1511 squashInstIt(inst_it, tid);
1512 }
1513}
1514
1515template <class Impl>
1516void
1517FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1518{
1519 assert(!instList.empty());
1520
1521 removeInstsThisCycle = true;
1522
1523 ListIt inst_iter = instList.end();
1524
1525 inst_iter--;
1526
1527 DPRINTF(O3CPU, "Deleting instructions from instruction "
1528 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1529 tid, seq_num, (*inst_iter)->seqNum);
1530
1531 while ((*inst_iter)->seqNum > seq_num) {
1532
1533 bool break_loop = (inst_iter == instList.begin());
1534
1535 squashInstIt(inst_iter, tid);
1536
1537 inst_iter--;
1538
1539 if (break_loop)
1540 break;
1541 }
1542}
1543
1544template <class Impl>
1545inline void
1546FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid)
1547{
1548 if ((*instIt)->threadNumber == tid) {
1549 DPRINTF(O3CPU, "Squashing instruction, "
1550 "[tid:%i] [sn:%lli] PC %s\n",
1551 (*instIt)->threadNumber,
1552 (*instIt)->seqNum,
1553 (*instIt)->pcState());
1554
1555 // Mark it as squashed.
1556 (*instIt)->setSquashed();
1557
1558 // @todo: Formulate a consistent method for deleting
1559 // instructions from the instruction list
1560 // Remove the instruction from the list.
1561 removeList.push(instIt);
1562 }
1563}
1564
1565template <class Impl>
1566void
1567FullO3CPU<Impl>::cleanUpRemovedInsts()
1568{
1569 while (!removeList.empty()) {
1570 DPRINTF(O3CPU, "Removing instruction, "
1571 "[tid:%i] [sn:%lli] PC %s\n",
1572 (*removeList.front())->threadNumber,
1573 (*removeList.front())->seqNum,
1574 (*removeList.front())->pcState());
1575
1576 instList.erase(removeList.front());
1577
1578 removeList.pop();
1579 }
1580
1581 removeInstsThisCycle = false;
1582}
1583/*
1584template <class Impl>
1585void
1586FullO3CPU<Impl>::removeAllInsts()
1587{
1588 instList.clear();
1589}
1590*/
1591template <class Impl>
1592void
1593FullO3CPU<Impl>::dumpInsts()
1594{
1595 int num = 0;
1596
1597 ListIt inst_list_it = instList.begin();
1598
1599 cprintf("Dumping Instruction List\n");
1600
1601 while (inst_list_it != instList.end()) {
1602 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1603 "Squashed:%i\n\n",
1604 num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber,
1605 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1606 (*inst_list_it)->isSquashed());
1607 inst_list_it++;
1608 ++num;
1609 }
1610}
1611/*
1612template <class Impl>
1613void
1614FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
1615{
1616 iew.wakeDependents(inst);
1617}
1618*/
1619template <class Impl>
1620void
1621FullO3CPU<Impl>::wakeCPU()
1622{
1623 if (activityRec.active() || tickEvent.scheduled()) {
1624 DPRINTF(Activity, "CPU already running.\n");
1625 return;
1626 }
1627
1628 DPRINTF(Activity, "Waking up CPU\n");
1629
1630 Cycles cycles(curCycle() - lastRunningCycle);
1631 // @todo: This is an oddity that is only here to match the stats
1632 if (cycles > 1) {
1633 --cycles;
1634 idleCycles += cycles;
1635 numCycles += cycles;
1636 ppCycles->notify(cycles);
1637 }
1638
1639 schedule(tickEvent, clockEdge());
1640}
1641
1642template <class Impl>
1643void
1644FullO3CPU<Impl>::wakeup()
1645{
1646 if (this->thread[0]->status() != ThreadContext::Suspended)
1647 return;
1648
1649 this->wakeCPU();
1650
1651 DPRINTF(Quiesce, "Suspended Processor woken\n");
1652 this->threadContexts[0]->activate();
1653}
1654
1655template <class Impl>
1656ThreadID
1657FullO3CPU<Impl>::getFreeTid()
1658{
1659 for (ThreadID tid = 0; tid < numThreads; tid++) {
1660 if (!tids[tid]) {
1661 tids[tid] = true;
1662 return tid;
1663 }
1664 }
1665
1666 return InvalidThreadID;
1667}
1668
1669template <class Impl>
1670void
1671FullO3CPU<Impl>::updateThreadPriority()
1672{
1673 if (activeThreads.size() > 1) {
1674 //DEFAULT TO ROUND ROBIN SCHEME
1675 //e.g. Move highest priority to end of thread list
1676 list<ThreadID>::iterator list_begin = activeThreads.begin();
1677
1678 unsigned high_thread = *list_begin;
1679
1680 activeThreads.erase(list_begin);
1681
1682 activeThreads.push_back(high_thread);
1683 }
1684}
1685
1686// Forward declaration of FullO3CPU.
1687template class FullO3CPU<O3CPUImpl>;
2 * Copyright (c) 2011-2012, 2014 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * Copyright (c) 2011 Regents of the University of California
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Kevin Lim
43 * Korey Sewell
44 * Rick Strong
45 */
46
47#include "arch/kernel_stats.hh"
48#include "config/the_isa.hh"
49#include "cpu/checker/cpu.hh"
50#include "cpu/checker/thread_context.hh"
51#include "cpu/o3/cpu.hh"
52#include "cpu/o3/isa_specific.hh"
53#include "cpu/o3/thread_context.hh"
54#include "cpu/activity.hh"
55#include "cpu/quiesce_event.hh"
56#include "cpu/simple_thread.hh"
57#include "cpu/thread_context.hh"
58#include "debug/Activity.hh"
59#include "debug/Drain.hh"
60#include "debug/O3CPU.hh"
61#include "debug/Quiesce.hh"
62#include "enums/MemoryMode.hh"
63#include "sim/core.hh"
64#include "sim/full_system.hh"
65#include "sim/process.hh"
66#include "sim/stat_control.hh"
67#include "sim/system.hh"
68
69#if THE_ISA == ALPHA_ISA
70#include "arch/alpha/osfpal.hh"
71#include "debug/Activity.hh"
72#endif
73
74struct BaseCPUParams;
75
76using namespace TheISA;
77using namespace std;
78
79BaseO3CPU::BaseO3CPU(BaseCPUParams *params)
80 : BaseCPU(params)
81{
82}
83
84void
85BaseO3CPU::regStats()
86{
87 BaseCPU::regStats();
88}
89
90template<class Impl>
91bool
92FullO3CPU<Impl>::IcachePort::recvTimingResp(PacketPtr pkt)
93{
94 DPRINTF(O3CPU, "Fetch unit received timing\n");
95 // We shouldn't ever get a block in ownership state
96 assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted()));
97 fetch->processCacheCompletion(pkt);
98
99 return true;
100}
101
102template<class Impl>
103void
104FullO3CPU<Impl>::IcachePort::recvReqRetry()
105{
106 fetch->recvReqRetry();
107}
108
109template <class Impl>
110bool
111FullO3CPU<Impl>::DcachePort::recvTimingResp(PacketPtr pkt)
112{
113 return lsq->recvTimingResp(pkt);
114}
115
116template <class Impl>
117void
118FullO3CPU<Impl>::DcachePort::recvTimingSnoopReq(PacketPtr pkt)
119{
120 // X86 ISA: Snooping an invalidation for monitor/mwait
121 if(cpu->getCpuAddrMonitor()->doMonitor(pkt)) {
122 cpu->wakeup();
123 }
124 lsq->recvTimingSnoopReq(pkt);
125}
126
127template <class Impl>
128void
129FullO3CPU<Impl>::DcachePort::recvReqRetry()
130{
131 lsq->recvReqRetry();
132}
133
134template <class Impl>
135FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
136 : Event(CPU_Tick_Pri), cpu(c)
137{
138}
139
140template <class Impl>
141void
142FullO3CPU<Impl>::TickEvent::process()
143{
144 cpu->tick();
145}
146
147template <class Impl>
148const char *
149FullO3CPU<Impl>::TickEvent::description() const
150{
151 return "FullO3CPU tick";
152}
153
154template <class Impl>
155FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
156 : BaseO3CPU(params),
157 itb(params->itb),
158 dtb(params->dtb),
159 tickEvent(this),
160#ifndef NDEBUG
161 instcount(0),
162#endif
163 removeInstsThisCycle(false),
164 fetch(this, params),
165 decode(this, params),
166 rename(this, params),
167 iew(this, params),
168 commit(this, params),
169
170 regFile(params->numPhysIntRegs,
171 params->numPhysFloatRegs,
172 params->numPhysCCRegs),
173
174 freeList(name() + ".freelist", ®File),
175
176 rob(this, params),
177
178 scoreboard(name() + ".scoreboard",
179 regFile.totalNumPhysRegs(), TheISA::NumMiscRegs,
180 TheISA::ZeroReg, TheISA::ZeroReg),
181
182 isa(numThreads, NULL),
183
184 icachePort(&fetch, this),
185 dcachePort(&iew.ldstQueue, this),
186
187 timeBuffer(params->backComSize, params->forwardComSize),
188 fetchQueue(params->backComSize, params->forwardComSize),
189 decodeQueue(params->backComSize, params->forwardComSize),
190 renameQueue(params->backComSize, params->forwardComSize),
191 iewQueue(params->backComSize, params->forwardComSize),
192 activityRec(name(), NumStages,
193 params->backComSize + params->forwardComSize,
194 params->activity),
195
196 globalSeqNum(1),
197 system(params->system),
198 drainManager(NULL),
199 lastRunningCycle(curCycle())
200{
201 if (!params->switched_out) {
202 _status = Running;
203 } else {
204 _status = SwitchedOut;
205 }
206
207 if (params->checker) {
208 BaseCPU *temp_checker = params->checker;
209 checker = dynamic_cast<Checker<Impl> *>(temp_checker);
210 checker->setIcachePort(&icachePort);
211 checker->setSystem(params->system);
212 } else {
213 checker = NULL;
214 }
215
216 if (!FullSystem) {
217 thread.resize(numThreads);
218 tids.resize(numThreads);
219 }
220
221 // The stages also need their CPU pointer setup. However this
222 // must be done at the upper level CPU because they have pointers
223 // to the upper level CPU, and not this FullO3CPU.
224
225 // Set up Pointers to the activeThreads list for each stage
226 fetch.setActiveThreads(&activeThreads);
227 decode.setActiveThreads(&activeThreads);
228 rename.setActiveThreads(&activeThreads);
229 iew.setActiveThreads(&activeThreads);
230 commit.setActiveThreads(&activeThreads);
231
232 // Give each of the stages the time buffer they will use.
233 fetch.setTimeBuffer(&timeBuffer);
234 decode.setTimeBuffer(&timeBuffer);
235 rename.setTimeBuffer(&timeBuffer);
236 iew.setTimeBuffer(&timeBuffer);
237 commit.setTimeBuffer(&timeBuffer);
238
239 // Also setup each of the stages' queues.
240 fetch.setFetchQueue(&fetchQueue);
241 decode.setFetchQueue(&fetchQueue);
242 commit.setFetchQueue(&fetchQueue);
243 decode.setDecodeQueue(&decodeQueue);
244 rename.setDecodeQueue(&decodeQueue);
245 rename.setRenameQueue(&renameQueue);
246 iew.setRenameQueue(&renameQueue);
247 iew.setIEWQueue(&iewQueue);
248 commit.setIEWQueue(&iewQueue);
249 commit.setRenameQueue(&renameQueue);
250
251 commit.setIEWStage(&iew);
252 rename.setIEWStage(&iew);
253 rename.setCommitStage(&commit);
254
255 ThreadID active_threads;
256 if (FullSystem) {
257 active_threads = 1;
258 } else {
259 active_threads = params->workload.size();
260
261 if (active_threads > Impl::MaxThreads) {
262 panic("Workload Size too large. Increase the 'MaxThreads' "
263 "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) "
264 "or edit your workload size.");
265 }
266 }
267
268 //Make Sure That this a Valid Architeture
269 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs);
270 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
271 assert(params->numPhysCCRegs >= numThreads * TheISA::NumCCRegs);
272
273 rename.setScoreboard(&scoreboard);
274 iew.setScoreboard(&scoreboard);
275
276 // Setup the rename map for whichever stages need it.
277 for (ThreadID tid = 0; tid < numThreads; tid++) {
278 isa[tid] = params->isa[tid];
279
280 // Only Alpha has an FP zero register, so for other ISAs we
281 // use an invalid FP register index to avoid special treatment
282 // of any valid FP reg.
283 RegIndex invalidFPReg = TheISA::NumFloatRegs + 1;
284 RegIndex fpZeroReg =
285 (THE_ISA == ALPHA_ISA) ? TheISA::ZeroReg : invalidFPReg;
286
287 commitRenameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg,
288 &freeList);
289
290 renameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg,
291 &freeList);
292 }
293
294 // Initialize rename map to assign physical registers to the
295 // architectural registers for active threads only.
296 for (ThreadID tid = 0; tid < active_threads; tid++) {
297 for (RegIndex ridx = 0; ridx < TheISA::NumIntRegs; ++ridx) {
298 // Note that we can't use the rename() method because we don't
299 // want special treatment for the zero register at this point
300 PhysRegIndex phys_reg = freeList.getIntReg();
301 renameMap[tid].setIntEntry(ridx, phys_reg);
302 commitRenameMap[tid].setIntEntry(ridx, phys_reg);
303 }
304
305 for (RegIndex ridx = 0; ridx < TheISA::NumFloatRegs; ++ridx) {
306 PhysRegIndex phys_reg = freeList.getFloatReg();
307 renameMap[tid].setFloatEntry(ridx, phys_reg);
308 commitRenameMap[tid].setFloatEntry(ridx, phys_reg);
309 }
310
311 for (RegIndex ridx = 0; ridx < TheISA::NumCCRegs; ++ridx) {
312 PhysRegIndex phys_reg = freeList.getCCReg();
313 renameMap[tid].setCCEntry(ridx, phys_reg);
314 commitRenameMap[tid].setCCEntry(ridx, phys_reg);
315 }
316 }
317
318 rename.setRenameMap(renameMap);
319 commit.setRenameMap(commitRenameMap);
320 rename.setFreeList(&freeList);
321
322 // Setup the ROB for whichever stages need it.
323 commit.setROB(&rob);
324
325 lastActivatedCycle = 0;
326#if 0
327 // Give renameMap & rename stage access to the freeList;
328 for (ThreadID tid = 0; tid < numThreads; tid++)
329 globalSeqNum[tid] = 1;
330#endif
331
332 DPRINTF(O3CPU, "Creating O3CPU object.\n");
333
334 // Setup any thread state.
335 this->thread.resize(this->numThreads);
336
337 for (ThreadID tid = 0; tid < this->numThreads; ++tid) {
338 if (FullSystem) {
339 // SMT is not supported in FS mode yet.
340 assert(this->numThreads == 1);
341 this->thread[tid] = new Thread(this, 0, NULL);
342 } else {
343 if (tid < params->workload.size()) {
344 DPRINTF(O3CPU, "Workload[%i] process is %#x",
345 tid, this->thread[tid]);
346 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
347 (typename Impl::O3CPU *)(this),
348 tid, params->workload[tid]);
349
350 //usedTids[tid] = true;
351 //threadMap[tid] = tid;
352 } else {
353 //Allocate Empty thread so M5 can use later
354 //when scheduling threads to CPU
355 Process* dummy_proc = NULL;
356
357 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
358 (typename Impl::O3CPU *)(this),
359 tid, dummy_proc);
360 //usedTids[tid] = false;
361 }
362 }
363
364 ThreadContext *tc;
365
366 // Setup the TC that will serve as the interface to the threads/CPU.
367 O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>;
368
369 tc = o3_tc;
370
371 // If we're using a checker, then the TC should be the
372 // CheckerThreadContext.
373 if (params->checker) {
374 tc = new CheckerThreadContext<O3ThreadContext<Impl> >(
375 o3_tc, this->checker);
376 }
377
378 o3_tc->cpu = (typename Impl::O3CPU *)(this);
379 assert(o3_tc->cpu);
380 o3_tc->thread = this->thread[tid];
381
382 if (FullSystem) {
383 // Setup quiesce event.
384 this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
385 }
386 // Give the thread the TC.
387 this->thread[tid]->tc = tc;
388
389 // Add the TC to the CPU's list of TC's.
390 this->threadContexts.push_back(tc);
391 }
392
393 // FullO3CPU always requires an interrupt controller.
394 if (!params->switched_out && !interrupts) {
395 fatal("FullO3CPU %s has no interrupt controller.\n"
396 "Ensure createInterruptController() is called.\n", name());
397 }
398
399 for (ThreadID tid = 0; tid < this->numThreads; tid++)
400 this->thread[tid]->setFuncExeInst(0);
401}
402
403template <class Impl>
404FullO3CPU<Impl>::~FullO3CPU()
405{
406}
407
408template <class Impl>
409void
410FullO3CPU<Impl>::regProbePoints()
411{
412 BaseCPU::regProbePoints();
413
414 ppInstAccessComplete = new ProbePointArg<PacketPtr>(getProbeManager(), "InstAccessComplete");
415 ppDataAccessComplete = new ProbePointArg<std::pair<DynInstPtr, PacketPtr> >(getProbeManager(), "DataAccessComplete");
416
417 fetch.regProbePoints();
418 iew.regProbePoints();
419 commit.regProbePoints();
420}
421
422template <class Impl>
423void
424FullO3CPU<Impl>::regStats()
425{
426 BaseO3CPU::regStats();
427
428 // Register any of the O3CPU's stats here.
429 timesIdled
430 .name(name() + ".timesIdled")
431 .desc("Number of times that the entire CPU went into an idle state and"
432 " unscheduled itself")
433 .prereq(timesIdled);
434
435 idleCycles
436 .name(name() + ".idleCycles")
437 .desc("Total number of cycles that the CPU has spent unscheduled due "
438 "to idling")
439 .prereq(idleCycles);
440
441 quiesceCycles
442 .name(name() + ".quiesceCycles")
443 .desc("Total number of cycles that CPU has spent quiesced or waiting "
444 "for an interrupt")
445 .prereq(quiesceCycles);
446
447 // Number of Instructions simulated
448 // --------------------------------
449 // Should probably be in Base CPU but need templated
450 // MaxThreads so put in here instead
451 committedInsts
452 .init(numThreads)
453 .name(name() + ".committedInsts")
454 .desc("Number of Instructions Simulated")
455 .flags(Stats::total);
456
457 committedOps
458 .init(numThreads)
459 .name(name() + ".committedOps")
460 .desc("Number of Ops (including micro ops) Simulated")
461 .flags(Stats::total);
462
463 cpi
464 .name(name() + ".cpi")
465 .desc("CPI: Cycles Per Instruction")
466 .precision(6);
467 cpi = numCycles / committedInsts;
468
469 totalCpi
470 .name(name() + ".cpi_total")
471 .desc("CPI: Total CPI of All Threads")
472 .precision(6);
473 totalCpi = numCycles / sum(committedInsts);
474
475 ipc
476 .name(name() + ".ipc")
477 .desc("IPC: Instructions Per Cycle")
478 .precision(6);
479 ipc = committedInsts / numCycles;
480
481 totalIpc
482 .name(name() + ".ipc_total")
483 .desc("IPC: Total IPC of All Threads")
484 .precision(6);
485 totalIpc = sum(committedInsts) / numCycles;
486
487 this->fetch.regStats();
488 this->decode.regStats();
489 this->rename.regStats();
490 this->iew.regStats();
491 this->commit.regStats();
492 this->rob.regStats();
493
494 intRegfileReads
495 .name(name() + ".int_regfile_reads")
496 .desc("number of integer regfile reads")
497 .prereq(intRegfileReads);
498
499 intRegfileWrites
500 .name(name() + ".int_regfile_writes")
501 .desc("number of integer regfile writes")
502 .prereq(intRegfileWrites);
503
504 fpRegfileReads
505 .name(name() + ".fp_regfile_reads")
506 .desc("number of floating regfile reads")
507 .prereq(fpRegfileReads);
508
509 fpRegfileWrites
510 .name(name() + ".fp_regfile_writes")
511 .desc("number of floating regfile writes")
512 .prereq(fpRegfileWrites);
513
514 ccRegfileReads
515 .name(name() + ".cc_regfile_reads")
516 .desc("number of cc regfile reads")
517 .prereq(ccRegfileReads);
518
519 ccRegfileWrites
520 .name(name() + ".cc_regfile_writes")
521 .desc("number of cc regfile writes")
522 .prereq(ccRegfileWrites);
523
524 miscRegfileReads
525 .name(name() + ".misc_regfile_reads")
526 .desc("number of misc regfile reads")
527 .prereq(miscRegfileReads);
528
529 miscRegfileWrites
530 .name(name() + ".misc_regfile_writes")
531 .desc("number of misc regfile writes")
532 .prereq(miscRegfileWrites);
533}
534
535template <class Impl>
536void
537FullO3CPU<Impl>::tick()
538{
539 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
540 assert(!switchedOut());
541 assert(getDrainState() != Drainable::Drained);
542
543 ++numCycles;
544 ppCycles->notify(1);
545
546// activity = false;
547
548 //Tick each of the stages
549 fetch.tick();
550
551 decode.tick();
552
553 rename.tick();
554
555 iew.tick();
556
557 commit.tick();
558
559 // Now advance the time buffers
560 timeBuffer.advance();
561
562 fetchQueue.advance();
563 decodeQueue.advance();
564 renameQueue.advance();
565 iewQueue.advance();
566
567 activityRec.advance();
568
569 if (removeInstsThisCycle) {
570 cleanUpRemovedInsts();
571 }
572
573 if (!tickEvent.scheduled()) {
574 if (_status == SwitchedOut) {
575 DPRINTF(O3CPU, "Switched out!\n");
576 // increment stat
577 lastRunningCycle = curCycle();
578 } else if (!activityRec.active() || _status == Idle) {
579 DPRINTF(O3CPU, "Idle!\n");
580 lastRunningCycle = curCycle();
581 timesIdled++;
582 } else {
583 schedule(tickEvent, clockEdge(Cycles(1)));
584 DPRINTF(O3CPU, "Scheduling next tick!\n");
585 }
586 }
587
588 if (!FullSystem)
589 updateThreadPriority();
590
591 tryDrain();
592}
593
594template <class Impl>
595void
596FullO3CPU<Impl>::init()
597{
598 BaseCPU::init();
599
600 for (ThreadID tid = 0; tid < numThreads; ++tid) {
601 // Set noSquashFromTC so that the CPU doesn't squash when initially
602 // setting up registers.
603 thread[tid]->noSquashFromTC = true;
604 // Initialise the ThreadContext's memory proxies
605 thread[tid]->initMemProxies(thread[tid]->getTC());
606 }
607
608 if (FullSystem && !params()->switched_out) {
609 for (ThreadID tid = 0; tid < numThreads; tid++) {
610 ThreadContext *src_tc = threadContexts[tid];
611 TheISA::initCPU(src_tc, src_tc->contextId());
612 }
613 }
614
615 // Clear noSquashFromTC.
616 for (int tid = 0; tid < numThreads; ++tid)
617 thread[tid]->noSquashFromTC = false;
618
619 commit.setThreads(thread);
620}
621
622template <class Impl>
623void
624FullO3CPU<Impl>::startup()
625{
626 BaseCPU::startup();
627 for (int tid = 0; tid < numThreads; ++tid)
628 isa[tid]->startup(threadContexts[tid]);
629
630 fetch.startupStage();
631 decode.startupStage();
632 iew.startupStage();
633 rename.startupStage();
634 commit.startupStage();
635}
636
637template <class Impl>
638void
639FullO3CPU<Impl>::activateThread(ThreadID tid)
640{
641 list<ThreadID>::iterator isActive =
642 std::find(activeThreads.begin(), activeThreads.end(), tid);
643
644 DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid);
645 assert(!switchedOut());
646
647 if (isActive == activeThreads.end()) {
648 DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n",
649 tid);
650
651 activeThreads.push_back(tid);
652 }
653}
654
655template <class Impl>
656void
657FullO3CPU<Impl>::deactivateThread(ThreadID tid)
658{
659 //Remove From Active List, if Active
660 list<ThreadID>::iterator thread_it =
661 std::find(activeThreads.begin(), activeThreads.end(), tid);
662
663 DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid);
664 assert(!switchedOut());
665
666 if (thread_it != activeThreads.end()) {
667 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
668 tid);
669 activeThreads.erase(thread_it);
670 }
671
672 fetch.deactivateThread(tid);
673 commit.deactivateThread(tid);
674}
675
676template <class Impl>
677Counter
678FullO3CPU<Impl>::totalInsts() const
679{
680 Counter total(0);
681
682 ThreadID size = thread.size();
683 for (ThreadID i = 0; i < size; i++)
684 total += thread[i]->numInst;
685
686 return total;
687}
688
689template <class Impl>
690Counter
691FullO3CPU<Impl>::totalOps() const
692{
693 Counter total(0);
694
695 ThreadID size = thread.size();
696 for (ThreadID i = 0; i < size; i++)
697 total += thread[i]->numOp;
698
699 return total;
700}
701
702template <class Impl>
703void
704FullO3CPU<Impl>::activateContext(ThreadID tid)
705{
706 assert(!switchedOut());
707
708 // Needs to set each stage to running as well.
709 activateThread(tid);
710
711 // We don't want to wake the CPU if it is drained. In that case,
712 // we just want to flag the thread as active and schedule the tick
713 // event from drainResume() instead.
714 if (getDrainState() == Drainable::Drained)
715 return;
716
717 // If we are time 0 or if the last activation time is in the past,
718 // schedule the next tick and wake up the fetch unit
719 if (lastActivatedCycle == 0 || lastActivatedCycle < curTick()) {
720 scheduleTickEvent(Cycles(0));
721
722 // Be sure to signal that there's some activity so the CPU doesn't
723 // deschedule itself.
724 activityRec.activity();
725 fetch.wakeFromQuiesce();
726
727 Cycles cycles(curCycle() - lastRunningCycle);
728 // @todo: This is an oddity that is only here to match the stats
729 if (cycles != 0)
730 --cycles;
731 quiesceCycles += cycles;
732
733 lastActivatedCycle = curTick();
734
735 _status = Running;
736 }
737}
738
739template <class Impl>
740void
741FullO3CPU<Impl>::suspendContext(ThreadID tid)
742{
743 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
744 assert(!switchedOut());
745
746 deactivateThread(tid);
747
748 // If this was the last thread then unschedule the tick event.
749 if (activeThreads.size() == 0) {
750 unscheduleTickEvent();
751 lastRunningCycle = curCycle();
752 _status = Idle;
753 }
754
755 DPRINTF(Quiesce, "Suspending Context\n");
756}
757
758template <class Impl>
759void
760FullO3CPU<Impl>::haltContext(ThreadID tid)
761{
762 //For now, this is the same as deallocate
763 DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
764 assert(!switchedOut());
765
766 deactivateThread(tid);
767 removeThread(tid);
768}
769
770template <class Impl>
771void
772FullO3CPU<Impl>::insertThread(ThreadID tid)
773{
774 DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
775 // Will change now that the PC and thread state is internal to the CPU
776 // and not in the ThreadContext.
777 ThreadContext *src_tc;
778 if (FullSystem)
779 src_tc = system->threadContexts[tid];
780 else
781 src_tc = tcBase(tid);
782
783 //Bind Int Regs to Rename Map
784 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
785 PhysRegIndex phys_reg = freeList.getIntReg();
786
787 renameMap[tid].setEntry(ireg,phys_reg);
788 scoreboard.setReg(phys_reg);
789 }
790
791 //Bind Float Regs to Rename Map
792 int max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs;
793 for (int freg = TheISA::NumIntRegs; freg < max_reg; freg++) {
794 PhysRegIndex phys_reg = freeList.getFloatReg();
795
796 renameMap[tid].setEntry(freg,phys_reg);
797 scoreboard.setReg(phys_reg);
798 }
799
800 //Bind condition-code Regs to Rename Map
801 max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs + TheISA::NumCCRegs;
802 for (int creg = TheISA::NumIntRegs + TheISA::NumFloatRegs;
803 creg < max_reg; creg++) {
804 PhysRegIndex phys_reg = freeList.getCCReg();
805
806 renameMap[tid].setEntry(creg,phys_reg);
807 scoreboard.setReg(phys_reg);
808 }
809
810 //Copy Thread Data Into RegFile
811 //this->copyFromTC(tid);
812
813 //Set PC/NPC/NNPC
814 pcState(src_tc->pcState(), tid);
815
816 src_tc->setStatus(ThreadContext::Active);
817
818 activateContext(tid);
819
820 //Reset ROB/IQ/LSQ Entries
821 commit.rob->resetEntries();
822 iew.resetEntries();
823}
824
825template <class Impl>
826void
827FullO3CPU<Impl>::removeThread(ThreadID tid)
828{
829 DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
830
831 // Copy Thread Data From RegFile
832 // If thread is suspended, it might be re-allocated
833 // this->copyToTC(tid);
834
835
836 // @todo: 2-27-2008: Fix how we free up rename mappings
837 // here to alleviate the case for double-freeing registers
838 // in SMT workloads.
839
840 // Unbind Int Regs from Rename Map
841 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
842 PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
843 scoreboard.unsetReg(phys_reg);
844 freeList.addReg(phys_reg);
845 }
846
847 // Unbind Float Regs from Rename Map
848 int max_reg = TheISA::FP_Reg_Base + TheISA::NumFloatRegs;
849 for (int freg = TheISA::FP_Reg_Base; freg < max_reg; freg++) {
850 PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
851 scoreboard.unsetReg(phys_reg);
852 freeList.addReg(phys_reg);
853 }
854
855 // Unbind condition-code Regs from Rename Map
856 max_reg = TheISA::CC_Reg_Base + TheISA::NumCCRegs;
857 for (int creg = TheISA::CC_Reg_Base; creg < max_reg; creg++) {
858 PhysRegIndex phys_reg = renameMap[tid].lookup(creg);
859 scoreboard.unsetReg(phys_reg);
860 freeList.addReg(phys_reg);
861 }
862
863 // Squash Throughout Pipeline
864 DynInstPtr inst = commit.rob->readHeadInst(tid);
865 InstSeqNum squash_seq_num = inst->seqNum;
866 fetch.squash(0, squash_seq_num, inst, tid);
867 decode.squash(tid);
868 rename.squash(squash_seq_num, tid);
869 iew.squash(tid);
870 iew.ldstQueue.squash(squash_seq_num, tid);
871 commit.rob->squash(squash_seq_num, tid);
872
873
874 assert(iew.instQueue.getCount(tid) == 0);
875 assert(iew.ldstQueue.getCount(tid) == 0);
876
877 // Reset ROB/IQ/LSQ Entries
878
879 // Commented out for now. This should be possible to do by
880 // telling all the pipeline stages to drain first, and then
881 // checking until the drain completes. Once the pipeline is
882 // drained, call resetEntries(). - 10-09-06 ktlim
883/*
884 if (activeThreads.size() >= 1) {
885 commit.rob->resetEntries();
886 iew.resetEntries();
887 }
888*/
889}
890
891template <class Impl>
892Fault
893FullO3CPU<Impl>::hwrei(ThreadID tid)
894{
895#if THE_ISA == ALPHA_ISA
896 // Need to clear the lock flag upon returning from an interrupt.
897 this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
898
899 this->thread[tid]->kernelStats->hwrei();
900
901 // FIXME: XXX check for interrupts? XXX
902#endif
903 return NoFault;
904}
905
906template <class Impl>
907bool
908FullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid)
909{
910#if THE_ISA == ALPHA_ISA
911 if (this->thread[tid]->kernelStats)
912 this->thread[tid]->kernelStats->callpal(palFunc,
913 this->threadContexts[tid]);
914
915 switch (palFunc) {
916 case PAL::halt:
917 halt();
918 if (--System::numSystemsRunning == 0)
919 exitSimLoop("all cpus halted");
920 break;
921
922 case PAL::bpt:
923 case PAL::bugchk:
924 if (this->system->breakpoint())
925 return false;
926 break;
927 }
928#endif
929 return true;
930}
931
932template <class Impl>
933Fault
934FullO3CPU<Impl>::getInterrupts()
935{
936 // Check if there are any outstanding interrupts
937 return this->interrupts->getInterrupt(this->threadContexts[0]);
938}
939
940template <class Impl>
941void
942FullO3CPU<Impl>::processInterrupts(const Fault &interrupt)
943{
944 // Check for interrupts here. For now can copy the code that
945 // exists within isa_fullsys_traits.hh. Also assume that thread 0
946 // is the one that handles the interrupts.
947 // @todo: Possibly consolidate the interrupt checking code.
948 // @todo: Allow other threads to handle interrupts.
949
950 assert(interrupt != NoFault);
951 this->interrupts->updateIntrInfo(this->threadContexts[0]);
952
953 DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
954 this->trap(interrupt, 0, nullptr);
955}
956
957template <class Impl>
958void
959FullO3CPU<Impl>::trap(const Fault &fault, ThreadID tid,
960 const StaticInstPtr &inst)
961{
962 // Pass the thread's TC into the invoke method.
963 fault->invoke(this->threadContexts[tid], inst);
964}
965
966template <class Impl>
967void
968FullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid)
969{
970 DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid);
971
972 DPRINTF(Activity,"Activity: syscall() called.\n");
973
974 // Temporarily increase this by one to account for the syscall
975 // instruction.
976 ++(this->thread[tid]->funcExeInst);
977
978 // Execute the actual syscall.
979 this->thread[tid]->syscall(callnum);
980
981 // Decrease funcExeInst by one as the normal commit will handle
982 // incrementing it.
983 --(this->thread[tid]->funcExeInst);
984}
985
986template <class Impl>
987void
988FullO3CPU<Impl>::serializeThread(std::ostream &os, ThreadID tid)
989{
990 thread[tid]->serialize(os);
991}
992
993template <class Impl>
994void
995FullO3CPU<Impl>::unserializeThread(Checkpoint *cp, const std::string §ion,
996 ThreadID tid)
997{
998 thread[tid]->unserialize(cp, section);
999}
1000
1001template <class Impl>
1002unsigned int
1003FullO3CPU<Impl>::drain(DrainManager *drain_manager)
1004{
1005 // If the CPU isn't doing anything, then return immediately.
1006 if (switchedOut()) {
1007 setDrainState(Drainable::Drained);
1008 return 0;
1009 }
1010
1011 DPRINTF(Drain, "Draining...\n");
1012 setDrainState(Drainable::Draining);
1013
1014 // We only need to signal a drain to the commit stage as this
1015 // initiates squashing controls the draining. Once the commit
1016 // stage commits an instruction where it is safe to stop, it'll
1017 // squash the rest of the instructions in the pipeline and force
1018 // the fetch stage to stall. The pipeline will be drained once all
1019 // in-flight instructions have retired.
1020 commit.drain();
1021
1022 // Wake the CPU and record activity so everything can drain out if
1023 // the CPU was not able to immediately drain.
1024 if (!isDrained()) {
1025 drainManager = drain_manager;
1026
1027 wakeCPU();
1028 activityRec.activity();
1029
1030 DPRINTF(Drain, "CPU not drained\n");
1031
1032 return 1;
1033 } else {
1034 setDrainState(Drainable::Drained);
1035 DPRINTF(Drain, "CPU is already drained\n");
1036 if (tickEvent.scheduled())
1037 deschedule(tickEvent);
1038
1039 // Flush out any old data from the time buffers. In
1040 // particular, there might be some data in flight from the
1041 // fetch stage that isn't visible in any of the CPU buffers we
1042 // test in isDrained().
1043 for (int i = 0; i < timeBuffer.getSize(); ++i) {
1044 timeBuffer.advance();
1045 fetchQueue.advance();
1046 decodeQueue.advance();
1047 renameQueue.advance();
1048 iewQueue.advance();
1049 }
1050
1051 drainSanityCheck();
1052 return 0;
1053 }
1054}
1055
1056template <class Impl>
1057bool
1058FullO3CPU<Impl>::tryDrain()
1059{
1060 if (!drainManager || !isDrained())
1061 return false;
1062
1063 if (tickEvent.scheduled())
1064 deschedule(tickEvent);
1065
1066 DPRINTF(Drain, "CPU done draining, processing drain event\n");
1067 drainManager->signalDrainDone();
1068 drainManager = NULL;
1069
1070 return true;
1071}
1072
1073template <class Impl>
1074void
1075FullO3CPU<Impl>::drainSanityCheck() const
1076{
1077 assert(isDrained());
1078 fetch.drainSanityCheck();
1079 decode.drainSanityCheck();
1080 rename.drainSanityCheck();
1081 iew.drainSanityCheck();
1082 commit.drainSanityCheck();
1083}
1084
1085template <class Impl>
1086bool
1087FullO3CPU<Impl>::isDrained() const
1088{
1089 bool drained(true);
1090
1091 if (!instList.empty() || !removeList.empty()) {
1092 DPRINTF(Drain, "Main CPU structures not drained.\n");
1093 drained = false;
1094 }
1095
1096 if (!fetch.isDrained()) {
1097 DPRINTF(Drain, "Fetch not drained.\n");
1098 drained = false;
1099 }
1100
1101 if (!decode.isDrained()) {
1102 DPRINTF(Drain, "Decode not drained.\n");
1103 drained = false;
1104 }
1105
1106 if (!rename.isDrained()) {
1107 DPRINTF(Drain, "Rename not drained.\n");
1108 drained = false;
1109 }
1110
1111 if (!iew.isDrained()) {
1112 DPRINTF(Drain, "IEW not drained.\n");
1113 drained = false;
1114 }
1115
1116 if (!commit.isDrained()) {
1117 DPRINTF(Drain, "Commit not drained.\n");
1118 drained = false;
1119 }
1120
1121 return drained;
1122}
1123
1124template <class Impl>
1125void
1126FullO3CPU<Impl>::commitDrained(ThreadID tid)
1127{
1128 fetch.drainStall(tid);
1129}
1130
1131template <class Impl>
1132void
1133FullO3CPU<Impl>::drainResume()
1134{
1135 setDrainState(Drainable::Running);
1136 if (switchedOut())
1137 return;
1138
1139 DPRINTF(Drain, "Resuming...\n");
1140 verifyMemoryMode();
1141
1142 fetch.drainResume();
1143 commit.drainResume();
1144
1145 _status = Idle;
1146 for (ThreadID i = 0; i < thread.size(); i++) {
1147 if (thread[i]->status() == ThreadContext::Active) {
1148 DPRINTF(Drain, "Activating thread: %i\n", i);
1149 activateThread(i);
1150 _status = Running;
1151 }
1152 }
1153
1154 assert(!tickEvent.scheduled());
1155 if (_status == Running)
1156 schedule(tickEvent, nextCycle());
1157}
1158
1159template <class Impl>
1160void
1161FullO3CPU<Impl>::switchOut()
1162{
1163 DPRINTF(O3CPU, "Switching out\n");
1164 BaseCPU::switchOut();
1165
1166 activityRec.reset();
1167
1168 _status = SwitchedOut;
1169
1170 if (checker)
1171 checker->switchOut();
1172}
1173
1174template <class Impl>
1175void
1176FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
1177{
1178 BaseCPU::takeOverFrom(oldCPU);
1179
1180 fetch.takeOverFrom();
1181 decode.takeOverFrom();
1182 rename.takeOverFrom();
1183 iew.takeOverFrom();
1184 commit.takeOverFrom();
1185
1186 assert(!tickEvent.scheduled());
1187
1188 FullO3CPU<Impl> *oldO3CPU = dynamic_cast<FullO3CPU<Impl>*>(oldCPU);
1189 if (oldO3CPU)
1190 globalSeqNum = oldO3CPU->globalSeqNum;
1191
1192 lastRunningCycle = curCycle();
1193 _status = Idle;
1194}
1195
1196template <class Impl>
1197void
1198FullO3CPU<Impl>::verifyMemoryMode() const
1199{
1200 if (!system->isTimingMode()) {
1201 fatal("The O3 CPU requires the memory system to be in "
1202 "'timing' mode.\n");
1203 }
1204}
1205
1206template <class Impl>
1207TheISA::MiscReg
1208FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
1209{
1210 return this->isa[tid]->readMiscRegNoEffect(misc_reg);
1211}
1212
1213template <class Impl>
1214TheISA::MiscReg
1215FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
1216{
1217 miscRegfileReads++;
1218 return this->isa[tid]->readMiscReg(misc_reg, tcBase(tid));
1219}
1220
1221template <class Impl>
1222void
1223FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
1224 const TheISA::MiscReg &val, ThreadID tid)
1225{
1226 this->isa[tid]->setMiscRegNoEffect(misc_reg, val);
1227}
1228
1229template <class Impl>
1230void
1231FullO3CPU<Impl>::setMiscReg(int misc_reg,
1232 const TheISA::MiscReg &val, ThreadID tid)
1233{
1234 miscRegfileWrites++;
1235 this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid));
1236}
1237
1238template <class Impl>
1239uint64_t
1240FullO3CPU<Impl>::readIntReg(int reg_idx)
1241{
1242 intRegfileReads++;
1243 return regFile.readIntReg(reg_idx);
1244}
1245
1246template <class Impl>
1247FloatReg
1248FullO3CPU<Impl>::readFloatReg(int reg_idx)
1249{
1250 fpRegfileReads++;
1251 return regFile.readFloatReg(reg_idx);
1252}
1253
1254template <class Impl>
1255FloatRegBits
1256FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
1257{
1258 fpRegfileReads++;
1259 return regFile.readFloatRegBits(reg_idx);
1260}
1261
1262template <class Impl>
1263CCReg
1264FullO3CPU<Impl>::readCCReg(int reg_idx)
1265{
1266 ccRegfileReads++;
1267 return regFile.readCCReg(reg_idx);
1268}
1269
1270template <class Impl>
1271void
1272FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
1273{
1274 intRegfileWrites++;
1275 regFile.setIntReg(reg_idx, val);
1276}
1277
1278template <class Impl>
1279void
1280FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
1281{
1282 fpRegfileWrites++;
1283 regFile.setFloatReg(reg_idx, val);
1284}
1285
1286template <class Impl>
1287void
1288FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
1289{
1290 fpRegfileWrites++;
1291 regFile.setFloatRegBits(reg_idx, val);
1292}
1293
1294template <class Impl>
1295void
1296FullO3CPU<Impl>::setCCReg(int reg_idx, CCReg val)
1297{
1298 ccRegfileWrites++;
1299 regFile.setCCReg(reg_idx, val);
1300}
1301
1302template <class Impl>
1303uint64_t
1304FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1305{
1306 intRegfileReads++;
1307 PhysRegIndex phys_reg = commitRenameMap[tid].lookupInt(reg_idx);
1308
1309 return regFile.readIntReg(phys_reg);
1310}
1311
1312template <class Impl>
1313float
1314FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
1315{
1316 fpRegfileReads++;
1317 PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1318
1319 return regFile.readFloatReg(phys_reg);
1320}
1321
1322template <class Impl>
1323uint64_t
1324FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid)
1325{
1326 fpRegfileReads++;
1327 PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1328
1329 return regFile.readFloatRegBits(phys_reg);
1330}
1331
1332template <class Impl>
1333CCReg
1334FullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid)
1335{
1336 ccRegfileReads++;
1337 PhysRegIndex phys_reg = commitRenameMap[tid].lookupCC(reg_idx);
1338
1339 return regFile.readCCReg(phys_reg);
1340}
1341
1342template <class Impl>
1343void
1344FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
1345{
1346 intRegfileWrites++;
1347 PhysRegIndex phys_reg = commitRenameMap[tid].lookupInt(reg_idx);
1348
1349 regFile.setIntReg(phys_reg, val);
1350}
1351
1352template <class Impl>
1353void
1354FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid)
1355{
1356 fpRegfileWrites++;
1357 PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1358
1359 regFile.setFloatReg(phys_reg, val);
1360}
1361
1362template <class Impl>
1363void
1364FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid)
1365{
1366 fpRegfileWrites++;
1367 PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx);
1368
1369 regFile.setFloatRegBits(phys_reg, val);
1370}
1371
1372template <class Impl>
1373void
1374FullO3CPU<Impl>::setArchCCReg(int reg_idx, CCReg val, ThreadID tid)
1375{
1376 ccRegfileWrites++;
1377 PhysRegIndex phys_reg = commitRenameMap[tid].lookupCC(reg_idx);
1378
1379 regFile.setCCReg(phys_reg, val);
1380}
1381
1382template <class Impl>
1383TheISA::PCState
1384FullO3CPU<Impl>::pcState(ThreadID tid)
1385{
1386 return commit.pcState(tid);
1387}
1388
1389template <class Impl>
1390void
1391FullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid)
1392{
1393 commit.pcState(val, tid);
1394}
1395
1396template <class Impl>
1397Addr
1398FullO3CPU<Impl>::instAddr(ThreadID tid)
1399{
1400 return commit.instAddr(tid);
1401}
1402
1403template <class Impl>
1404Addr
1405FullO3CPU<Impl>::nextInstAddr(ThreadID tid)
1406{
1407 return commit.nextInstAddr(tid);
1408}
1409
1410template <class Impl>
1411MicroPC
1412FullO3CPU<Impl>::microPC(ThreadID tid)
1413{
1414 return commit.microPC(tid);
1415}
1416
1417template <class Impl>
1418void
1419FullO3CPU<Impl>::squashFromTC(ThreadID tid)
1420{
1421 this->thread[tid]->noSquashFromTC = true;
1422 this->commit.generateTCEvent(tid);
1423}
1424
1425template <class Impl>
1426typename FullO3CPU<Impl>::ListIt
1427FullO3CPU<Impl>::addInst(DynInstPtr &inst)
1428{
1429 instList.push_back(inst);
1430
1431 return --(instList.end());
1432}
1433
1434template <class Impl>
1435void
1436FullO3CPU<Impl>::instDone(ThreadID tid, DynInstPtr &inst)
1437{
1438 // Keep an instruction count.
1439 if (!inst->isMicroop() || inst->isLastMicroop()) {
1440 thread[tid]->numInst++;
1441 thread[tid]->numInsts++;
1442 committedInsts[tid]++;
1443 system->totalNumInsts++;
1444
1445 // Check for instruction-count-based events.
1446 comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1447 system->instEventQueue.serviceEvents(system->totalNumInsts);
1448 }
1449 thread[tid]->numOp++;
1450 thread[tid]->numOps++;
1451 committedOps[tid]++;
1452
1453 probeInstCommit(inst->staticInst);
1454}
1455
1456template <class Impl>
1457void
1458FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
1459{
1460 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s "
1461 "[sn:%lli]\n",
1462 inst->threadNumber, inst->pcState(), inst->seqNum);
1463
1464 removeInstsThisCycle = true;
1465
1466 // Remove the front instruction.
1467 removeList.push(inst->getInstListIt());
1468}
1469
1470template <class Impl>
1471void
1472FullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid)
1473{
1474 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1475 " list.\n", tid);
1476
1477 ListIt end_it;
1478
1479 bool rob_empty = false;
1480
1481 if (instList.empty()) {
1482 return;
1483 } else if (rob.isEmpty(tid)) {
1484 DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1485 end_it = instList.begin();
1486 rob_empty = true;
1487 } else {
1488 end_it = (rob.readTailInst(tid))->getInstListIt();
1489 DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1490 }
1491
1492 removeInstsThisCycle = true;
1493
1494 ListIt inst_it = instList.end();
1495
1496 inst_it--;
1497
1498 // Walk through the instruction list, removing any instructions
1499 // that were inserted after the given instruction iterator, end_it.
1500 while (inst_it != end_it) {
1501 assert(!instList.empty());
1502
1503 squashInstIt(inst_it, tid);
1504
1505 inst_it--;
1506 }
1507
1508 // If the ROB was empty, then we actually need to remove the first
1509 // instruction as well.
1510 if (rob_empty) {
1511 squashInstIt(inst_it, tid);
1512 }
1513}
1514
1515template <class Impl>
1516void
1517FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1518{
1519 assert(!instList.empty());
1520
1521 removeInstsThisCycle = true;
1522
1523 ListIt inst_iter = instList.end();
1524
1525 inst_iter--;
1526
1527 DPRINTF(O3CPU, "Deleting instructions from instruction "
1528 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1529 tid, seq_num, (*inst_iter)->seqNum);
1530
1531 while ((*inst_iter)->seqNum > seq_num) {
1532
1533 bool break_loop = (inst_iter == instList.begin());
1534
1535 squashInstIt(inst_iter, tid);
1536
1537 inst_iter--;
1538
1539 if (break_loop)
1540 break;
1541 }
1542}
1543
1544template <class Impl>
1545inline void
1546FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid)
1547{
1548 if ((*instIt)->threadNumber == tid) {
1549 DPRINTF(O3CPU, "Squashing instruction, "
1550 "[tid:%i] [sn:%lli] PC %s\n",
1551 (*instIt)->threadNumber,
1552 (*instIt)->seqNum,
1553 (*instIt)->pcState());
1554
1555 // Mark it as squashed.
1556 (*instIt)->setSquashed();
1557
1558 // @todo: Formulate a consistent method for deleting
1559 // instructions from the instruction list
1560 // Remove the instruction from the list.
1561 removeList.push(instIt);
1562 }
1563}
1564
1565template <class Impl>
1566void
1567FullO3CPU<Impl>::cleanUpRemovedInsts()
1568{
1569 while (!removeList.empty()) {
1570 DPRINTF(O3CPU, "Removing instruction, "
1571 "[tid:%i] [sn:%lli] PC %s\n",
1572 (*removeList.front())->threadNumber,
1573 (*removeList.front())->seqNum,
1574 (*removeList.front())->pcState());
1575
1576 instList.erase(removeList.front());
1577
1578 removeList.pop();
1579 }
1580
1581 removeInstsThisCycle = false;
1582}
1583/*
1584template <class Impl>
1585void
1586FullO3CPU<Impl>::removeAllInsts()
1587{
1588 instList.clear();
1589}
1590*/
1591template <class Impl>
1592void
1593FullO3CPU<Impl>::dumpInsts()
1594{
1595 int num = 0;
1596
1597 ListIt inst_list_it = instList.begin();
1598
1599 cprintf("Dumping Instruction List\n");
1600
1601 while (inst_list_it != instList.end()) {
1602 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1603 "Squashed:%i\n\n",
1604 num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber,
1605 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1606 (*inst_list_it)->isSquashed());
1607 inst_list_it++;
1608 ++num;
1609 }
1610}
1611/*
1612template <class Impl>
1613void
1614FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
1615{
1616 iew.wakeDependents(inst);
1617}
1618*/
1619template <class Impl>
1620void
1621FullO3CPU<Impl>::wakeCPU()
1622{
1623 if (activityRec.active() || tickEvent.scheduled()) {
1624 DPRINTF(Activity, "CPU already running.\n");
1625 return;
1626 }
1627
1628 DPRINTF(Activity, "Waking up CPU\n");
1629
1630 Cycles cycles(curCycle() - lastRunningCycle);
1631 // @todo: This is an oddity that is only here to match the stats
1632 if (cycles > 1) {
1633 --cycles;
1634 idleCycles += cycles;
1635 numCycles += cycles;
1636 ppCycles->notify(cycles);
1637 }
1638
1639 schedule(tickEvent, clockEdge());
1640}
1641
1642template <class Impl>
1643void
1644FullO3CPU<Impl>::wakeup()
1645{
1646 if (this->thread[0]->status() != ThreadContext::Suspended)
1647 return;
1648
1649 this->wakeCPU();
1650
1651 DPRINTF(Quiesce, "Suspended Processor woken\n");
1652 this->threadContexts[0]->activate();
1653}
1654
1655template <class Impl>
1656ThreadID
1657FullO3CPU<Impl>::getFreeTid()
1658{
1659 for (ThreadID tid = 0; tid < numThreads; tid++) {
1660 if (!tids[tid]) {
1661 tids[tid] = true;
1662 return tid;
1663 }
1664 }
1665
1666 return InvalidThreadID;
1667}
1668
1669template <class Impl>
1670void
1671FullO3CPU<Impl>::updateThreadPriority()
1672{
1673 if (activeThreads.size() > 1) {
1674 //DEFAULT TO ROUND ROBIN SCHEME
1675 //e.g. Move highest priority to end of thread list
1676 list<ThreadID>::iterator list_begin = activeThreads.begin();
1677
1678 unsigned high_thread = *list_begin;
1679
1680 activeThreads.erase(list_begin);
1681
1682 activeThreads.push_back(high_thread);
1683 }
1684}
1685
1686// Forward declaration of FullO3CPU.
1687template class FullO3CPU<O3CPUImpl>;